mirror of
https://github.com/rdolbeau/VexRiscvBPluginGenerator.git
synced 2025-04-18 18:44:42 -04:00
441 lines
21 KiB
Scala
441 lines
21 KiB
Scala
package vexriscv.plugin
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import spinal.core._
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import vexriscv.{Stageable, DecoderService, VexRiscv}
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object BitManipZbpPlugin {
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object BitManipZbpCtrlbitwiseEnum extends SpinalEnum(binarySequential) {
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val CTRL_ANDN, CTRL_ORN, CTRL_XNOR = newElement()
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}
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object BitManipZbpCtrlrotationEnum extends SpinalEnum(binarySequential) {
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val CTRL_ROL, CTRL_ROR = newElement()
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}
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object BitManipZbpCtrlgrevrocEnum extends SpinalEnum(binarySequential) {
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val CTRL_GORC, CTRL_GREV = newElement()
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}
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object BitManipZbpCtrlshuffleEnum extends SpinalEnum(binarySequential) {
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val CTRL_SHFL, CTRL_UNSHFL = newElement()
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}
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object BitManipZbpCtrlpackEnum extends SpinalEnum(binarySequential) {
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val CTRL_PACK, CTRL_PACKH, CTRL_PACKU = newElement()
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}
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object BitManipZbpCtrlxpermEnum extends SpinalEnum(binarySequential) {
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val CTRL_XPERMdotB, CTRL_XPERMdotH, CTRL_XPERMdotN = newElement()
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}
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object BitManipZbpCtrlgrevorcEnum extends SpinalEnum(binarySequential) {
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val CTRL_GORC, CTRL_GREV = newElement()
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}
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object BitManipZbpCtrlEnum extends SpinalEnum(binarySequential) {
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val CTRL_bitwise, CTRL_rotation, CTRL_grevroc, CTRL_shuffle, CTRL_pack, CTRL_xperm, CTRL_grevorc = newElement()
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}
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object BitManipZbpCtrlbitwise extends Stageable(BitManipZbpCtrlbitwiseEnum())
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object BitManipZbpCtrlrotation extends Stageable(BitManipZbpCtrlrotationEnum())
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object BitManipZbpCtrlgrevroc extends Stageable(BitManipZbpCtrlgrevrocEnum())
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object BitManipZbpCtrlshuffle extends Stageable(BitManipZbpCtrlshuffleEnum())
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object BitManipZbpCtrlpack extends Stageable(BitManipZbpCtrlpackEnum())
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object BitManipZbpCtrlxperm extends Stageable(BitManipZbpCtrlxpermEnum())
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object BitManipZbpCtrlgrevorc extends Stageable(BitManipZbpCtrlgrevorcEnum())
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object BitManipZbpCtrl extends Stageable(BitManipZbpCtrlEnum())
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// Prologue
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// function implementing the semantic of 32-bits generalized reverse
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def fun_grev( a:Bits, b:Bits ) : Bits = {
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val x1 = ((b&B"32'x00000001")===B"32'x00000001") ? (((a & B"32'x55555555") |<< 1) | ((a & B"32'xAAAAAAAA") |>> 1)) | a
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val x2 = ((b&B"32'x00000002")===B"32'x00000002") ? (((x1 & B"32'x33333333") |<< 2) | ((x1 & B"32'xCCCCCCCC") |>> 2)) | x1
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val x4 = ((b&B"32'x00000004")===B"32'x00000004") ? (((x2 & B"32'x0F0F0F0F") |<< 4) | ((x2 & B"32'xF0F0F0F0") |>> 4)) | x2
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val x8 = ((b&B"32'x00000008")===B"32'x00000008") ? (((x4 & B"32'x00FF00FF") |<< 8) | ((x4 & B"32'xFF00FF00") |>> 8)) | x4
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val x16 = ((b&B"32'x00000010")===B"32'x00000010") ? (((x8 & B"32'x0000FFFF") |<<16) | ((x8 & B"32'xFFFF0000") |>>16)) | x8
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x16 // return value
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}
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// function implementing the semantic of 32-bits generalized OR-combine
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def fun_gorc( a:Bits, b:Bits ) : Bits = {
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val x1 = ((b&B"32'x00000001")===B"32'x00000001") ? (a | ((a & B"32'x55555555") |<< 1) | ((a & B"32'xAAAAAAAA") |>> 1)) | a
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val x2 = ((b&B"32'x00000002")===B"32'x00000002") ? (x1 | ((x1 & B"32'x33333333") |<< 2) | ((x1 & B"32'xCCCCCCCC") |>> 2)) | x1
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val x4 = ((b&B"32'x00000004")===B"32'x00000004") ? (x2 | ((x2 & B"32'x0F0F0F0F") |<< 4) | ((x2 & B"32'xF0F0F0F0") |>> 4)) | x2
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val x8 = ((b&B"32'x00000008")===B"32'x00000008") ? (x4 | ((x4 & B"32'x00FF00FF") |<< 8) | ((x4 & B"32'xFF00FF00") |>> 8)) | x4
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val x16 = ((b&B"32'x00000010")===B"32'x00000010") ? (x8 | ((x8 & B"32'x0000FFFF") |<<16) | ((x8 & B"32'xFFFF0000") |>>16)) | x8
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x16 // return value
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}
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// helper function for the implementation of the generalized shuffles
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def fun_shuffle32_stage(src:Bits, maskL:Bits, maskR:Bits, N:Int) : Bits = {
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val x = src & ~(maskL | maskR)
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val x2 = x | ((src |<< N) & maskL) | ((src |>> N) & maskR);
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x2 // return value
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}
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// function implementing the semantic of 32-bits generalized shuffle
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def fun_shfl32(a:Bits, b:Bits) : Bits = {
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val x = a;
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val x1 = ((b&B"32'x00000008")===B"32'x00000008") ? fun_shuffle32_stage(x , B"32'x00FF0000", B"32'x0000FF00", 8) | x;
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val x2 = ((b&B"32'x00000004")===B"32'x00000004") ? fun_shuffle32_stage(x1, B"32'x0F000F00", B"32'x00F000F0", 4) | x1;
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val x3 = ((b&B"32'x00000002")===B"32'x00000002") ? fun_shuffle32_stage(x2, B"32'x30303030", B"32'x0C0C0C0C", 2) | x2;
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val x4 = ((b&B"32'x00000001")===B"32'x00000001") ? fun_shuffle32_stage(x3, B"32'x44444444", B"32'x22222222", 1) | x3;
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x4 // return value
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}
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// function implementing the semantic of 32-bits generalized unshuffle
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def fun_unshfl32(a:Bits, b:Bits) : Bits = {
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val x = a;
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val x1 = ((b&B"32'x00000001")===B"32'x00000001") ? fun_shuffle32_stage(x , B"32'x44444444", B"32'x22222222", 1) | x;
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val x2 = ((b&B"32'x00000002")===B"32'x00000002") ? fun_shuffle32_stage(x1, B"32'x30303030", B"32'x0C0C0C0C", 2) | x1;
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val x3 = ((b&B"32'x00000004")===B"32'x00000004") ? fun_shuffle32_stage(x2, B"32'x0F000F00", B"32'x00F000F0", 4) | x2;
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val x4 = ((b&B"32'x00000008")===B"32'x00000008") ? fun_shuffle32_stage(x3, B"32'x00FF0000", B"32'x0000FF00", 8) | x3;
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x4 // return value
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}
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// this is trying to look like DOI 10.2478/jee-2015-0054
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def fun_clz_NLCi(x:Bits): Bits = {
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val r2 = (~(x(0) | x(1) | x(2) | x(3)))
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val r1 = (~(x(2) | x(3)))
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val r0 = (~(x(3) | (x(1) & ~x(2))))
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val r = r2 ## r1 ## r0
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r // return value
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}
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def fun_clz_BNE(a:Bits) : Bits = {
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val a01 = ~(a(0) & a(1))
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val a23 = ~(a(2) & a(3))
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val a45 = ~(a(4) & a(5))
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val a67 = ~(a(6) & a(7))
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val a0123 = ~(a01 | a23) // also r(2)
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val a4567 = ~(a45 | a67)
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val a56 = ~(a(5) & ~a(6))
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val a024 = (a(0) & a(2) & a(4)) // AND not NAND
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val a13 = ~(a(1) & a(3))
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val a12 = ~(a(1) & ~a(2))
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val r3 = ((a0123 & a4567)) // AND not NAND
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val r2 = (a0123)
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val r1 = (~(a01 | (~a23 & a45)))
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val r0 = (~((~((a56) & (a024))) & (~((a13) & (a12) & (a(0))))))
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val r = r3 ## r2 ## r1 ##r0
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r // return value
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}
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def fun_clz(in:Bits) : Bits = {
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val nlc7 = fun_clz_NLCi(in(31 downto 28))
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val nlc6 = fun_clz_NLCi(in(27 downto 24))
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val nlc5 = fun_clz_NLCi(in(23 downto 20))
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val nlc4 = fun_clz_NLCi(in(19 downto 16))
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val nlc3 = fun_clz_NLCi(in(15 downto 12))
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val nlc2 = fun_clz_NLCi(in(11 downto 8))
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val nlc1 = fun_clz_NLCi(in( 7 downto 4))
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val nlc0 = fun_clz_NLCi(in( 3 downto 0))
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val a = nlc0(2) ## nlc1(2) ## nlc2(2) ## nlc3(2) ## nlc4(2) ## nlc5(2) ## nlc6(2) ## nlc7(2)
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val bne = fun_clz_BNE(a)
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val muxo = (bne(2 downto 0)).mux(
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B"3'b000" -> nlc7(1 downto 0),
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B"3'b001" -> nlc6(1 downto 0),
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B"3'b010" -> nlc5(1 downto 0),
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B"3'b011" -> nlc4(1 downto 0),
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B"3'b100" -> nlc3(1 downto 0),
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B"3'b101" -> nlc2(1 downto 0),
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B"3'b110" -> nlc1(1 downto 0),
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B"3'b111" -> nlc0(1 downto 0)
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)
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val r = (bne(3)) ? B"6'b100000" | (B"1'b0" ## bne(2 downto 0) ## muxo(1 downto 0)) // 6 bits
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r.resize(32) // return value
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}
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// For trailing count, count using use leading count on bit-reversed value
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def fun_ctz(in:Bits) : Bits = {
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val inr = in(0) ## in(1) ## in(2) ## in(3) ## in(4) ## in(5) ## in(6) ## in(7) ## in(8) ## in(9) ## in(10) ## in(11) ## in(12) ## in(13) ## in(14) ## in(15) ## in(16) ## in(17) ## in(18) ## in(19) ## in(20) ## in(21) ## in(22) ## in(23) ## in(24) ## in(25) ## in(26) ## in(27) ## in(28) ## in(29) ## in(30) ## in(31)
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fun_clz(inr) // return value
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}
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// naive popcnt
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def fun_popcnt(in:Bits) : Bits = {
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val r = in(0).asBits.resize(6).asUInt + in(1).asBits.resize(6).asUInt + in(2).asBits.resize(6).asUInt + in(3).asBits.resize(6).asUInt +
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in(4).asBits.resize(6).asUInt + in(5).asBits.resize(6).asUInt + in(6).asBits.resize(6).asUInt + in(7).asBits.resize(6).asUInt +
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in(8).asBits.resize(6).asUInt + in(9).asBits.resize(6).asUInt + in(10).asBits.resize(6).asUInt + in(11).asBits.resize(6).asUInt +
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in(12).asBits.resize(6).asUInt + in(13).asBits.resize(6).asUInt + in(14).asBits.resize(6).asUInt + in(15).asBits.resize(6).asUInt +
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in(16).asBits.resize(6).asUInt + in(17).asBits.resize(6).asUInt + in(18).asBits.resize(6).asUInt + in(19).asBits.resize(6).asUInt +
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in(20).asBits.resize(6).asUInt + in(21).asBits.resize(6).asUInt + in(22).asBits.resize(6).asUInt + in(23).asBits.resize(6).asUInt +
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in(24).asBits.resize(6).asUInt + in(25).asBits.resize(6).asUInt + in(26).asBits.resize(6).asUInt + in(27).asBits.resize(6).asUInt +
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in(28).asBits.resize(6).asUInt + in(29).asBits.resize(6).asUInt + in(30).asBits.resize(6).asUInt + in(31).asBits.resize(6).asUInt
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r.asBits.resize(32) // return value
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}
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//XPERMs
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def fun_xperm_n(rs1:Bits, rs2:Bits) : Bits = {
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val i0 = rs2(3 downto 0).asUInt
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val i1 = rs2(7 downto 4).asUInt
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val i2 = rs2(11 downto 8).asUInt
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val i3 = rs2(15 downto 12).asUInt
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val i4 = rs2(19 downto 16).asUInt
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val i5 = rs2(23 downto 20).asUInt
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val i6 = rs2(27 downto 24).asUInt
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val i7 = rs2(31 downto 28).asUInt
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val r0 = (i0).mux(
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0 -> rs1(3 downto 0),
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1 -> rs1(7 downto 4),
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2 -> rs1(11 downto 8),
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3 -> rs1(15 downto 12),
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4 -> rs1(19 downto 16),
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5 -> rs1(23 downto 20),
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6 -> rs1(27 downto 24),
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7 -> rs1(31 downto 28),
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default -> B"4'b0000"
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)
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val r1 = (i1).mux(
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0 -> rs1(3 downto 0),
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1 -> rs1(7 downto 4),
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2 -> rs1(11 downto 8),
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3 -> rs1(15 downto 12),
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4 -> rs1(19 downto 16),
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5 -> rs1(23 downto 20),
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6 -> rs1(27 downto 24),
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7 -> rs1(31 downto 28),
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default -> B"4'b0000"
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)
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val r2 = (i2).mux(
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0 -> rs1(3 downto 0),
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1 -> rs1(7 downto 4),
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2 -> rs1(11 downto 8),
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3 -> rs1(15 downto 12),
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4 -> rs1(19 downto 16),
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5 -> rs1(23 downto 20),
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6 -> rs1(27 downto 24),
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7 -> rs1(31 downto 28),
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default -> B"4'b0000"
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)
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val r3 = (i3).mux(
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0 -> rs1(3 downto 0),
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1 -> rs1(7 downto 4),
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2 -> rs1(11 downto 8),
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3 -> rs1(15 downto 12),
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4 -> rs1(19 downto 16),
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5 -> rs1(23 downto 20),
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6 -> rs1(27 downto 24),
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7 -> rs1(31 downto 28),
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default -> B"4'b0000"
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)
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val r4 = (i4).mux(
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0 -> rs1(3 downto 0),
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1 -> rs1(7 downto 4),
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2 -> rs1(11 downto 8),
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3 -> rs1(15 downto 12),
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4 -> rs1(19 downto 16),
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5 -> rs1(23 downto 20),
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6 -> rs1(27 downto 24),
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7 -> rs1(31 downto 28),
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default -> B"4'b0000"
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)
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val r5 = (i5).mux(
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0 -> rs1(3 downto 0),
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1 -> rs1(7 downto 4),
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2 -> rs1(11 downto 8),
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3 -> rs1(15 downto 12),
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4 -> rs1(19 downto 16),
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5 -> rs1(23 downto 20),
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6 -> rs1(27 downto 24),
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7 -> rs1(31 downto 28),
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default -> B"4'b0000"
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)
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val r6 = (i6).mux(
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0 -> rs1(3 downto 0),
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1 -> rs1(7 downto 4),
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2 -> rs1(11 downto 8),
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3 -> rs1(15 downto 12),
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4 -> rs1(19 downto 16),
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5 -> rs1(23 downto 20),
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6 -> rs1(27 downto 24),
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7 -> rs1(31 downto 28),
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default -> B"4'b0000"
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)
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val r7 = (i7).mux(
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0 -> rs1(3 downto 0),
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1 -> rs1(7 downto 4),
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2 -> rs1(11 downto 8),
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3 -> rs1(15 downto 12),
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4 -> rs1(19 downto 16),
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5 -> rs1(23 downto 20),
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6 -> rs1(27 downto 24),
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7 -> rs1(31 downto 28),
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default -> B"4'b0000"
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)
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r7 ## r6 ## r5 ## r4 ## r3 ## r2 ## r1 ## r0 // return value
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}
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def fun_xperm_b(rs1:Bits, rs2:Bits) : Bits = {
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val i0 = rs2(7 downto 0).asUInt;
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val i1 = rs2(15 downto 0).asUInt;
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val i2 = rs2(23 downto 0).asUInt;
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val i3 = rs2(31 downto 0).asUInt;
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val r0 = (i0).mux(
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0 -> rs1(7 downto 0),
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1 -> rs1(15 downto 8),
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2 -> rs1(23 downto 16),
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3 -> rs1(31 downto 24),
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default -> B"8'b00000000"
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)
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val r1 = (i1).mux(
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0 -> rs1(7 downto 0),
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1 -> rs1(15 downto 8),
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2 -> rs1(23 downto 16),
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3 -> rs1(31 downto 24),
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default -> B"8'b00000000"
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)
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val r2 = (i2).mux(
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0 -> rs1(7 downto 0),
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1 -> rs1(15 downto 8),
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2 -> rs1(23 downto 16),
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3 -> rs1(31 downto 24),
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default -> B"8'b00000000"
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)
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val r3 = (i3).mux(
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0 -> rs1(7 downto 0),
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1 -> rs1(15 downto 8),
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2 -> rs1(23 downto 16),
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3 -> rs1(31 downto 24),
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default -> B"8'b00000000"
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)
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r3 ## r2 ## r1 ## r0 // return value
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}
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def fun_xperm_h(rs1:Bits, rs2:Bits) : Bits = {
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val i0 = rs2(15 downto 0).asUInt;
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val i1 = rs2(31 downto 16).asUInt;
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val r0 = (i0).mux(
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0 -> rs1(15 downto 0),
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1 -> rs1(31 downto 16),
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default -> B"16'x0000"
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)
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val r1 = (i1).mux(
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0 -> rs1(15 downto 0),
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1 -> rs1(31 downto 16),
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default -> B"16'x0000"
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)
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r1 ## r0 // return value
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}
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// End prologue
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} // object Plugin
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class BitManipZbpPlugin extends Plugin[VexRiscv] {
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import BitManipZbpPlugin._
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object IS_BitManipZbp extends Stageable(Bool)
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override def setup(pipeline: VexRiscv): Unit = {
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import pipeline.config._
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val immediateActions = List[(Stageable[_ <: BaseType],Any)](
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SRC1_CTRL -> Src1CtrlEnum.RS,
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SRC2_CTRL -> Src2CtrlEnum.IMI,
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REGFILE_WRITE_VALID -> True,
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BYPASSABLE_EXECUTE_STAGE -> True,
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BYPASSABLE_MEMORY_STAGE -> True,
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RS1_USE -> True,
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IS_BitManipZbp -> True
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)
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val binaryActions = List[(Stageable[_ <: BaseType],Any)](
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SRC1_CTRL -> Src1CtrlEnum.RS,
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SRC2_CTRL -> Src2CtrlEnum.RS,
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REGFILE_WRITE_VALID -> True,
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BYPASSABLE_EXECUTE_STAGE -> True,
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BYPASSABLE_MEMORY_STAGE -> True,
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RS1_USE -> True,
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RS2_USE -> True,
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IS_BitManipZbp -> True
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)
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val unaryActions = List[(Stageable[_ <: BaseType],Any)](
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SRC1_CTRL -> Src1CtrlEnum.RS,
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REGFILE_WRITE_VALID -> True,
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BYPASSABLE_EXECUTE_STAGE -> True,
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BYPASSABLE_MEMORY_STAGE -> True,
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RS1_USE -> True,
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IS_BitManipZbp -> True
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)
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def ANDN_KEY = M"0100000----------111-----0110011"
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def ORN_KEY = M"0100000----------110-----0110011"
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def XNOR_KEY = M"0100000----------100-----0110011"
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def ROL_KEY = M"0110000----------001-----0110011"
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def ROR_KEY = M"0110000----------101-----0110011"
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def GORC_KEY = M"0010100----------101-----0110011"
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def GREV_KEY = M"0110100----------101-----0110011"
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def SHFL_KEY = M"0000100----------001-----0110011"
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def UNSHFL_KEY = M"0000100----------101-----0110011"
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def PACK_KEY = M"0000100----------100-----0110011"
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def PACKU_KEY = M"0100100----------100-----0110011"
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def PACKH_KEY = M"0000100----------111-----0110011"
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def XPERMdotN_KEY = M"0010100----------010-----0110011"
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def XPERMdotB_KEY = M"0010100----------100-----0110011"
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def XPERMdotH_KEY = M"0010100----------110-----0110011"
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def RORI_KEY = M"01100------------101-----0010011"
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def GORCI_KEY = M"00101------------101-----0010011"
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def GREVI_KEY = M"01101------------101-----0010011"
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def SHFLI_KEY = M"000010-----------001-----0010011"
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def UNSHFLI_KEY = M"000010-----------101-----0010011"
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val decoderService = pipeline.service(classOf[DecoderService])
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decoderService.addDefault(IS_BitManipZbp, False)
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decoderService.add(List(
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ANDN_KEY -> (binaryActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_bitwise, BitManipZbpCtrlbitwise -> BitManipZbpCtrlbitwiseEnum.CTRL_ANDN)),
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ORN_KEY -> (binaryActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_bitwise, BitManipZbpCtrlbitwise -> BitManipZbpCtrlbitwiseEnum.CTRL_ORN)),
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XNOR_KEY -> (binaryActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_bitwise, BitManipZbpCtrlbitwise -> BitManipZbpCtrlbitwiseEnum.CTRL_XNOR)),
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ROL_KEY -> (binaryActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_rotation, BitManipZbpCtrlrotation -> BitManipZbpCtrlrotationEnum.CTRL_ROL)),
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ROR_KEY -> (binaryActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_rotation, BitManipZbpCtrlrotation -> BitManipZbpCtrlrotationEnum.CTRL_ROR)),
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RORI_KEY -> (immediateActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_rotation, BitManipZbpCtrlrotation -> BitManipZbpCtrlrotationEnum.CTRL_ROR)),
|
|
GORC_KEY -> (binaryActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_grevroc, BitManipZbpCtrlgrevroc -> BitManipZbpCtrlgrevrocEnum.CTRL_GORC)),
|
|
GREV_KEY -> (binaryActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_grevroc, BitManipZbpCtrlgrevroc -> BitManipZbpCtrlgrevrocEnum.CTRL_GREV)),
|
|
SHFL_KEY -> (binaryActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_shuffle, BitManipZbpCtrlshuffle -> BitManipZbpCtrlshuffleEnum.CTRL_SHFL)),
|
|
UNSHFL_KEY -> (binaryActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_shuffle, BitManipZbpCtrlshuffle -> BitManipZbpCtrlshuffleEnum.CTRL_UNSHFL)),
|
|
SHFLI_KEY -> (immediateActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_shuffle, BitManipZbpCtrlshuffle -> BitManipZbpCtrlshuffleEnum.CTRL_SHFL)),
|
|
UNSHFLI_KEY -> (immediateActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_shuffle, BitManipZbpCtrlshuffle -> BitManipZbpCtrlshuffleEnum.CTRL_UNSHFL)),
|
|
PACK_KEY -> (binaryActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_pack, BitManipZbpCtrlpack -> BitManipZbpCtrlpackEnum.CTRL_PACK)),
|
|
PACKU_KEY -> (binaryActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_pack, BitManipZbpCtrlpack -> BitManipZbpCtrlpackEnum.CTRL_PACKU)),
|
|
PACKH_KEY -> (binaryActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_pack, BitManipZbpCtrlpack -> BitManipZbpCtrlpackEnum.CTRL_PACKH)),
|
|
XPERMdotN_KEY -> (binaryActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_xperm, BitManipZbpCtrlxperm -> BitManipZbpCtrlxpermEnum.CTRL_XPERMdotN)),
|
|
XPERMdotB_KEY -> (binaryActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_xperm, BitManipZbpCtrlxperm -> BitManipZbpCtrlxpermEnum.CTRL_XPERMdotB)),
|
|
XPERMdotH_KEY -> (binaryActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_xperm, BitManipZbpCtrlxperm -> BitManipZbpCtrlxpermEnum.CTRL_XPERMdotH)),
|
|
GORCI_KEY -> (immediateActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_grevorc, BitManipZbpCtrlgrevorc -> BitManipZbpCtrlgrevorcEnum.CTRL_GORC)),
|
|
GREVI_KEY -> (immediateActions ++ List(BitManipZbpCtrl -> BitManipZbpCtrlEnum.CTRL_grevorc, BitManipZbpCtrlgrevorc -> BitManipZbpCtrlgrevorcEnum.CTRL_GREV))
|
|
))
|
|
} // override def setup
|
|
override def build(pipeline: VexRiscv): Unit = {
|
|
import pipeline._
|
|
import pipeline.config._
|
|
execute plug new Area{
|
|
import execute._
|
|
val val_bitwise = input(BitManipZbpCtrlbitwise).mux(
|
|
BitManipZbpCtrlbitwiseEnum.CTRL_ANDN -> (input(SRC1) & ~input(SRC2)),
|
|
BitManipZbpCtrlbitwiseEnum.CTRL_ORN -> (input(SRC1) | ~input(SRC2)),
|
|
BitManipZbpCtrlbitwiseEnum.CTRL_XNOR -> (input(SRC1) ^ ~input(SRC2))
|
|
) // mux bitwise
|
|
val val_rotation = input(BitManipZbpCtrlrotation).mux(
|
|
BitManipZbpCtrlrotationEnum.CTRL_ROL -> input(SRC1).rotateLeft((input(SRC2)&31)(4 downto 0).asUInt),
|
|
BitManipZbpCtrlrotationEnum.CTRL_ROR -> input(SRC1).rotateRight((input(SRC2)&31)(4 downto 0).asUInt)
|
|
) // mux rotation
|
|
val val_grevroc = input(BitManipZbpCtrlgrevroc).mux(
|
|
BitManipZbpCtrlgrevrocEnum.CTRL_GORC -> fun_gorc(input(SRC1), input(SRC2)),
|
|
BitManipZbpCtrlgrevrocEnum.CTRL_GREV -> fun_grev(input(SRC1), input(SRC2))
|
|
) // mux grevroc
|
|
val val_shuffle = input(BitManipZbpCtrlshuffle).mux(
|
|
BitManipZbpCtrlshuffleEnum.CTRL_SHFL -> fun_shfl32(input(SRC1), input(SRC2)),
|
|
BitManipZbpCtrlshuffleEnum.CTRL_UNSHFL -> fun_unshfl32(input(SRC1), input(SRC2))
|
|
) // mux shuffle
|
|
val val_pack = input(BitManipZbpCtrlpack).mux(
|
|
BitManipZbpCtrlpackEnum.CTRL_PACK -> (input(SRC2)(15 downto 0) ## input(SRC1)(15 downto 0)),
|
|
BitManipZbpCtrlpackEnum.CTRL_PACKH -> B"16'x0000" ## (input(SRC2)(7 downto 0) ## input(SRC1)(7 downto 0)),
|
|
BitManipZbpCtrlpackEnum.CTRL_PACKU -> (input(SRC2)(31 downto 16) ## input(SRC1)(31 downto 16))
|
|
) // mux pack
|
|
val val_xperm = input(BitManipZbpCtrlxperm).mux(
|
|
BitManipZbpCtrlxpermEnum.CTRL_XPERMdotB -> fun_xperm_b(input(SRC1), input(SRC2)),
|
|
BitManipZbpCtrlxpermEnum.CTRL_XPERMdotH -> fun_xperm_h(input(SRC1), input(SRC2)),
|
|
BitManipZbpCtrlxpermEnum.CTRL_XPERMdotN -> fun_xperm_n(input(SRC1), input(SRC2))
|
|
) // mux xperm
|
|
val val_grevorc = input(BitManipZbpCtrlgrevorc).mux(
|
|
BitManipZbpCtrlgrevorcEnum.CTRL_GORC -> fun_gorc(input(SRC1), input(SRC2)),
|
|
BitManipZbpCtrlgrevorcEnum.CTRL_GREV -> fun_grev(input(SRC1), input(SRC2))
|
|
) // mux grevorc
|
|
when (input(IS_BitManipZbp)) {
|
|
execute.output(REGFILE_WRITE_DATA) := input(BitManipZbpCtrl).mux(
|
|
BitManipZbpCtrlEnum.CTRL_bitwise -> val_bitwise.asBits,
|
|
BitManipZbpCtrlEnum.CTRL_rotation -> val_rotation.asBits,
|
|
BitManipZbpCtrlEnum.CTRL_grevroc -> val_grevroc.asBits,
|
|
BitManipZbpCtrlEnum.CTRL_shuffle -> val_shuffle.asBits,
|
|
BitManipZbpCtrlEnum.CTRL_pack -> val_pack.asBits,
|
|
BitManipZbpCtrlEnum.CTRL_xperm -> val_xperm.asBits,
|
|
BitManipZbpCtrlEnum.CTRL_grevorc -> val_grevorc.asBits
|
|
) // primary mux
|
|
} // when input is
|
|
} // execute plug newArea
|
|
} // override def build
|
|
} // class Plugin
|