mirror of
https://github.com/rdolbeau/VexRiscvBPluginGenerator.git
synced 2025-04-18 18:44:42 -04:00
49 lines
2.5 KiB
Text
49 lines
2.5 KiB
Text
//for vX.Y of P
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// low-order bit of Rd (7) is 0 to ensure even-numbered Rd
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// bit 25 is used for crossing so -
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I SMULx8 SMULx8 101010-----------000----01110111 pdpismul8 Zp64
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I UMULx8 UMULx8 101110-----------000----01110111 pdpiumul8 Zp64
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I SMULx16 SMULx16 101000-----------000----01110111 pdpismul16 Zp64
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I UMULx16 UMULx16 101100-----------000----01110111 pdpiumul16 Zp64
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// binary
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S SMULx8 "fun_smulx8(input(SRC1), input(SRC2), input(INSTRUCTION)(25).asUInt)"
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S UMULx8 "fun_umulx8(input(SRC1), input(SRC2), input(INSTRUCTION)(25).asUInt)"
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S SMULx16 "fun_smulx16(input(SRC1), input(SRC2), input(INSTRUCTION)(25).asUInt)"
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S UMULx16 "fun_umulx16(input(SRC1), input(SRC2), input(INSTRUCTION)(25).asUInt)"
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P """
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def fun_smulx8(rs1: Bits, rs2: Bits, cross: UInt) : Bits = {
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val rs2x = ((cross === 0) ? (rs2) | (rs2(23 downto 16) ## rs2(31 downto 24) ## rs2(7 downto 0) ## rs2(15 downto 8)))
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val h0 = (rs1( 7 downto 0).asSInt * rs2x( 7 downto 0).asSInt).asBits.resize(16)
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val h1 = (rs1(15 downto 8).asSInt * rs2x(15 downto 8).asSInt).asBits.resize(16)
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val h2 = (rs1(23 downto 16).asSInt * rs2x(23 downto 16).asSInt).asBits.resize(16)
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val h3 = (rs1(31 downto 24).asSInt * rs2x(31 downto 24).asSInt).asBits.resize(16)
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h3 ## h2 ## h1 ## h0 // return value
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}
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def fun_umulx8(rs1: Bits, rs2: Bits, cross: UInt) : Bits = {
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val rs2x = ((cross === 0) ? (rs2) | (rs2(23 downto 16) ## rs2(31 downto 24) ## rs2(7 downto 0) ## rs2(15 downto 8)))
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val h0 = (rs1( 7 downto 0).asUInt * rs2x( 7 downto 0).asUInt).asBits.resize(16)
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val h1 = (rs1(15 downto 8).asUInt * rs2x(15 downto 8).asUInt).asBits.resize(16)
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val h2 = (rs1(23 downto 16).asUInt * rs2x(23 downto 16).asUInt).asBits.resize(16)
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val h3 = (rs1(31 downto 24).asUInt * rs2x(31 downto 24).asUInt).asBits.resize(16)
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h3 ## h2 ## h1 ## h0 // return value
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}
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def fun_smulx16(rs1: Bits, rs2: Bits, cross: UInt) : Bits = {
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val rs2x = ((cross === 0) ? (rs2) | (rs2(15 downto 0) ## rs2(31 downto 16)))
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val w0 = (rs1(15 downto 0).asSInt * rs2x(15 downto 0).asSInt).asBits.resize(32)
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val w1 = (rs1(31 downto 16).asSInt * rs2x(31 downto 16).asSInt).asBits.resize(32)
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w1 ## w0 // return value
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}
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def fun_umulx16(rs1: Bits, rs2: Bits, cross: UInt) : Bits = {
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val rs2x = ((cross === 0) ? (rs2) | (rs2(15 downto 0) ## rs2(31 downto 16)))
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val w0 = (rs1(15 downto 0).asUInt * rs2x(15 downto 0).asUInt).asBits.resize(32)
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val w1 = (rs1(31 downto 16).asUInt * rs2x(31 downto 16).asUInt).asBits.resize(32)
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w1 ## w0 // return value
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}
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"""
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