mirror of
https://github.com/rdolbeau/VexRiscvBPluginGenerator.git
synced 2025-04-18 18:44:42 -04:00
80 lines
3.1 KiB
Text
80 lines
3.1 KiB
Text
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I SMAQA SMAQA 1100100----------000----01110111 pdpimul8 Zpn
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I UMAQA UMAQA 1100110----------000----01110111 pdpimul8 Zpn
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I MADDR32 MADDR32 1100010----------000-----1110111 pdpimul32 Zpn
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I MSUBR32 MSUBR32 1100011----------000-----1110111 pdpimul32 Zpn
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S SMAQA "fun_smaqa1(input(SRC1), input(SRC2), input(SRC3))"
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S UMAQA "fun_umaqa1(input(SRC1), input(SRC2), input(SRC3))"
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T SMAQA 96 "fun_smaqa2"
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T UMAQA 96 "fun_umaqa2"
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S MADDR32 "fun_maddr321(input(SRC1), input(SRC2), input(SRC3))"
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T MADDR32 128 "fun_maddr322"
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S MSUBR32 "fun_maddr321(input(SRC1), input(SRC2), input(SRC3))"
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T MSUBR32 128 "fun_msubr322"
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P """
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def fun_smaqa1(rs1: Bits, rs2: Bits, rs3: Bits) : Bits = {
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// 18 bits needed so that intermediate sums don't overflow
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val h0 = (rs1( 7 downto 0).asSInt * rs2( 7 downto 0).asSInt)
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val h1 = (rs1(15 downto 8).asSInt * rs2(15 downto 8).asSInt)
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val h2 = (rs1(23 downto 16).asSInt * rs2(23 downto 16).asSInt)
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val h3 = (rs1(31 downto 24).asSInt * rs2(31 downto 24).asSInt)
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rs3 ## h3 ## h2 ## h1 ## h0 // return value 96 bits
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}
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def fun_smaqa2(input:Bits ) : Bits = {
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val r = input(95 downto 64).asSInt + (
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input(63 downto 48).asSInt.resize(18) +
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input(47 downto 32).asSInt.resize(18) +
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input(31 downto 16).asSInt.resize(18) +
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input(15 downto 0).asSInt.resize(18))
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r.asBits.resize(32) // return value
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}
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def fun_umaqa1(rs1: Bits, rs2: Bits, rs3: Bits) : Bits = {
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// 18 bits needed so that intermediate sums don't overflow
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val h0 = (rs1( 7 downto 0).asUInt * rs2( 7 downto 0).asUInt)
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val h1 = (rs1(15 downto 8).asUInt * rs2(15 downto 8).asUInt)
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val h2 = (rs1(23 downto 16).asUInt * rs2(23 downto 16).asUInt)
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val h3 = (rs1(31 downto 24).asUInt * rs2(31 downto 24).asUInt)
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rs3 ## h3 ## h2 ## h1 ## h0 // return value 96 bits
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}
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def fun_umaqa2(input:Bits ) : Bits = {
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val r = input(95 downto 64).asUInt + (
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input(63 downto 48).asUInt.resize(18) +
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input(47 downto 32).asUInt.resize(18) +
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input(31 downto 16).asUInt.resize(18) +
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input(15 downto 0).asUInt.resize(18))
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r.asBits.resize(32) // return value
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}
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def fun_maddr321(rs1: Bits, rs2: Bits, rs3: Bits) : Bits = {
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val MUL_LL = rs1(15 downto 0).asUInt * rs2(15 downto 0).asUInt
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val MUL_LH = rs1(15 downto 0).asUInt * rs2(31 downto 16).asUInt
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val MUL_HL = rs1(31 downto 16).asUInt * rs2(15 downto 0).asUInt
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rs3 ## MUL_HL ## MUL_LH ## MUL_LL // return value 128 bits
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}
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def fun_maddr322(input:Bits ) : Bits = {
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val rs3 = input(127 downto 96)
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val MUL_HL = input(95 downto 64)
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val MUL_LH = input(63 downto 32)
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val MUL_LL = input(31 downto 0)
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val r = rs3.asUInt + MUL_LL.asUInt + (MUL_LH.asUInt << 16) + (MUL_HL.asUInt << 16)
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r.asBits.resize(32) // return value
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}
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def fun_msubr322(input:Bits ) : Bits = {
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val rs3 = input(127 downto 96)
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val MUL_HL = input(95 downto 64)
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val MUL_LH = input(63 downto 32)
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val MUL_LL = input(31 downto 0)
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val r = rs3.asUInt - MUL_LL.asUInt - (MUL_LH.asUInt << 16) - (MUL_HL.asUInt << 16)
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r.asBits.resize(32) // return value
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}
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"""
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