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synced 2025-04-22 04:57:18 -04:00
Updated taiga.mak. Removed untested simulated DDR features.
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0d48705a33
commit
01700d108e
1 changed files with 17 additions and 14 deletions
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@ -1,4 +1,3 @@
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###############################################################
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VERILATOR_DIR=$(TAIGA_DIR)/test_benches/verilator
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@ -16,11 +15,11 @@ TRACE_ENABLE?=False
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TAIGA_SIM_DIR?=$(VERILATOR_DIR)/build
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TAIGA_SIM?=$(TAIGA_SIM_DIR)/taiga-sim
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#DDR Pre-Initialization
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LOAD_DDR_FROM_FILE = False
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DDR_FILE = "\"path_to_DDR_init_file\""
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DDR_FILE_STARTING_LOCATION = 0
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DDR_FILE_NUM_BYTES = 0
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#(to-do)DDR Pre-Initialization
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#LOAD_DDR_FROM_FILE = False
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#DDR_FILE = "\"path_to_DDR_init_file\""
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#DDR_FILE_STARTING_LOCATION = 0
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#DDR_FILE_NUM_BYTES = 0
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#AXI DDR Parameters
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DDR_SIZE_GB = 4
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@ -42,13 +41,15 @@ max_delay_read = MAX_DELAY_RD=$(MAX_RD_DELAY)
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min_delay_write = MIN_DELAY_WR=$(MIN_WR_DELAY)
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max_delay_write = MAX_DELAY_WR=$(MAX_WR_DELAY)
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delay_seed = DELAY_SEED=$(DELAY_SEED)
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ddr_init_file = DDR_INIT_FILE=$(DDR_FILE)
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ddr_start_loc = DDR_FILE_STARTING_LOCATION=$(DDR_FILE_STARTING_LOCATION)
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ddr_num_bytes = DDR_FILE_NUM_BYTES=$(DDR_FILE_NUM_BYTES)
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#(to-do)
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#ddr_init_file = DDR_INIT_FILE=$(DDR_FILE)
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#ddr_start_loc = DDR_FILE_STARTING_LOCATION=$(DDR_FILE_STARTING_LOCATION)
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#ddr_num_bytes = DDR_FILE_NUM_BYTES=$(DDR_FILE_NUM_BYTES)
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CFLAGS = -g0 -O3 -std=c++11 -march=native -D$(ddr_size_def) -D$(page_size_def) -D$(max_inflight_read_requests) -D$(max_inflight_write_requests)\
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-D$(mix_delay_read) -D$(max_delay_read) -D$(min_delay_write) -D$(max_delay_write) -D$(delay_seed)\
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-D$(ddr_init_file) -D$(ddr_start_loc) -D$(ddr_num_bytes)
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-D$(mix_delay_read) -D$(max_delay_read) -D$(min_delay_write) -D$(max_delay_write) -D$(delay_seed)
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#(to-do)-D$(ddr_init_file) -D$(ddr_start_loc) -D$(ddr_num_bytes)
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#Verilator
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################################################################################
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@ -60,9 +61,11 @@ else
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endif
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VERILATOR_LINT_IGNORE= -Wno-LITENDIAN -Wno-SYMRSVDWORD
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ifeq ($(LOAD_DDR_FROM_FILE), True)
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VERILATOR_CFLAGS := $(VERILATOR_CFLAGS) -D LOAD_DDR_FROM_FILE"
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endif
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#(to-do)
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#ifeq ($(LOAD_DDR_FROM_FILE), True)
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# VERILATOR_CFLAGS := $(VERILATOR_CFLAGS) -D LOAD_DDR_FROM_FILE"
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#endif
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##################################################################################
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