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enabled assertions

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This commit is contained in:
Eric Matthews 2019-09-28 17:58:49 -07:00
parent e0359764ff
commit 02377934ec
3 changed files with 12 additions and 5 deletions
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6
core/csr_regs.sv
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@ -211,7 +211,7 @@ generate if (ENABLE_M_MODE) begin
assign interrupt_privilege_level = interrupt_delegated ? SUPERVISOR_PRIVILEGE : MACHINE_PRIVILEGE;
always_comb begin
unique if(mret | sret)
if(mret | sret)
next_privilege_level = trap_return_privilege_level;
else if (interrupt)
next_privilege_level = interrupt_privilege_level;
@ -249,7 +249,7 @@ generate if (ENABLE_M_MODE) begin
//return from trap
always_comb begin
mstatus_return = mstatus;
unique if (sret) begin
if (sret) begin
mstatus_return.sie = mstatus_return.spie;
mstatus_return.spie = 1;
mstatus_return.spp = 0;
@ -265,7 +265,7 @@ generate if (ENABLE_M_MODE) begin
assign mstatus_mask = mwrite_decoder[MSTATUS[5:0]] ? mstatus_mmask : mstatus_smask;
always_comb begin
unique if (mwrite_decoder[MSTATUS[5:0]] | swrite_decoder[SSTATUS[5:0]])
if (mwrite_decoder[MSTATUS[5:0]] | swrite_decoder[SSTATUS[5:0]])
mstatus_new = updated_csr & mstatus_mask;
else if (interrupt | gc_exception.valid)
mstatus_new = mstatus_exception;

9
test_benches/verilator/taiga_local_mem.cc
View file

@ -6,10 +6,17 @@
#include "verilated_vcd_c.h"
#include "TaigaTracer.h"
TaigaTracer<Vtaiga_local_mem> *taigaTracer;
//For time index on assertions
double sc_time_stamp () {
return taigaTracer->get_cycle_count();
}
//#define TRACE_ON
using namespace std;
int main(int argc, char **argv) {
TaigaTracer<Vtaiga_local_mem> *taigaTracer;
ofstream logFile, sigFile;
ifstream programFile;

2
tools/Makefile
View file

@ -113,7 +113,7 @@ build_taiga_sim:
cp $(VERILATOR_DIR)/SimMem.h verilator_local_mem_test/
cp $(VERILATOR_DIR)/SimMem.cc verilator_local_mem_test/
cp $(VERILATOR_DIR)/taiga_local_mem.cc verilator_local_mem_test/
verilator --cc --exe --Mdir verilator_local_mem_test $(VERILATOR_LINT_IGNORE) $(VERILATOR_CFLAGS) $(TAIGA_SRCS) \
verilator --cc --exe --Mdir verilator_local_mem_test --assert $(VERILATOR_LINT_IGNORE) $(VERILATOR_CFLAGS) $(TAIGA_SRCS) \
../test_benches/verilator/taiga_local_mem.sv --top-module taiga_local_mem taiga_local_mem.cc SimMem.cc
$(MAKE) -C verilator_local_mem_test -f Vtaiga_local_mem.mk