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MMU updates
This commit is contained in:
Eric Matthews
parent
8bf7050a0e
commit
02d51444d4
3 changed files with 64 additions and 40 deletions
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@ -143,7 +143,7 @@ interface mmu_interface;
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//TLB response
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logic write_entry;
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logic [19:0] new_phys_addr;
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logic [19:0] upper_physical_address;
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logic is_fault;
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//From CSR
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@ -152,8 +152,8 @@ interface mmu_interface;
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logic sum; //permit Supervisor User Memory access
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logic [1:0] privilege;
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modport mmu (input virtual_address, new_request, execute, rnw, ppn, mxr, sum, privilege, output write_entry, new_phys_addr, is_fault);
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modport tlb (input write_entry, new_phys_addr, is_fault, output new_request, virtual_address, execute, rnw);
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modport mmu (input virtual_address, new_request, execute, rnw, ppn, mxr, sum, privilege, output write_entry, upper_physical_address, is_fault);
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modport tlb (input write_entry, upper_physical_address, is_fault, output new_request, virtual_address, execute, rnw);
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modport csr (output ppn, mxr, sum, privilege);
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endinterface
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96
core/mmu.sv
96
core/mmu.sv
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@ -48,9 +48,17 @@ module mmu
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logic v;
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} pte_t;
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typedef enum {IDLE, SEND_REQUEST_1, WAIT_REQUEST_1, SEND_REQUEST_2, WAIT_REQUEST_2, COMPLETE_SUCCESS, COMPLETE_FAULT} mmu_state_t;
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mmu_state_t state;
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mmu_state_t next_state;
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typedef enum {
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IDLE = 0,
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SEND_REQUEST_1 = 1,
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WAIT_REQUEST_1 = 2,
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SEND_REQUEST_2 = 3,
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WAIT_REQUEST_2 = 4,
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COMPLETE_SUCCESS = 5,
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COMPLETE_FAULT = 6
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} mmu_state_t;
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logic [6:0] state;
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logic [6:0] next_state;
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pte_t pte;
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logic access_valid;
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@ -66,28 +74,27 @@ module mmu
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assign l1_request.is_amo = 0;
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assign l1_request.amo = 0;
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always_ff @ (posedge clk) begin
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if (rst | l1_request.ack)
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l1_request.request <= 0;
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else if (next_state inside {SEND_REQUEST_1, SEND_REQUEST_2})
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l1_request.request <= 1;
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end
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assign l1_request.request = state[SEND_REQUEST_1] | state[SEND_REQUEST_2];
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//Page Table addresses
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always_ff @ (posedge clk) begin
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if (next_state == SEND_REQUEST_2)
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l1_request.addr <= {{pte.ppn1[9:0], pte.ppn0}, mmu.virtual_address[21:12], 2'b00};
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else
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l1_request.addr <= {mmu.ppn[19:0], mmu.virtual_address[31:22], 2'b00};
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if (state[IDLE] | l1_response.data_valid) begin
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if (state[IDLE])
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l1_request.addr <= {mmu.ppn[19:0], mmu.virtual_address[31:22], 2'b00};
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else
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l1_request.addr <= {{pte.ppn1[9:0], pte.ppn0}, mmu.virtual_address[21:12], 2'b00};
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end
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end
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assign pte = l1_response.data;
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////////////////////////////////////////////////////
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//Access and permission checks
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//A and D bits are software managed
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assign access_valid =
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(mmu.execute & pte.x) | //fetch
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(mmu.rnw & (pte.r | (pte.x & mmu.mxr))) | //load
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((~mmu.rnw & ~mmu.execute) & pte.w); //store
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(mmu.execute & pte.x & pte.a) | //fetch
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(mmu.rnw & (pte.r | (pte.x & mmu.mxr)) & pte.a) | //load
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((~mmu.rnw & ~mmu.execute) & pte.w & pte.a & pte.d); //store
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assign privilege_valid =
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(mmu.privilege == MACHINE_PRIVILEGE) |
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@ -98,30 +105,47 @@ module mmu
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//State Machine
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always_comb begin
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next_state = state;
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case (state)
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IDLE : if (mmu.new_request) next_state = WAIT_REQUEST_1;
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SEND_REQUEST_1 : if (l1_request.ack) next_state = WAIT_REQUEST_1;
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WAIT_REQUEST_1 : begin
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case (1'b1)
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state[IDLE] :
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if (mmu.new_request) begin
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next_state = 2**SEND_REQUEST_1;
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end
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state[SEND_REQUEST_1] :
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if (l1_request.ack) begin
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next_state = 2**WAIT_REQUEST_1;
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end
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state[WAIT_REQUEST_1] :
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if (l1_response.data_valid) begin
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if (~pte.v | (~pte.r & pte.w)) //page not valid OR invalid xwr pattern
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next_state = COMPLETE_FAULT;
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else if (pte.v & (pte.r | pte.x)) //superpage (all remaining xwr patterns other than all zeros)
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next_state = (access_valid & privilege_valid) ? COMPLETE_SUCCESS : COMPLETE_FAULT;
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next_state = 2**COMPLETE_FAULT;
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else if (pte.v & (pte.r | pte.x)) begin//superpage (all remaining xwr patterns other than all zeros)
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if (access_valid & privilege_valid)
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next_state = 2**COMPLETE_SUCCESS;
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else
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next_state = 2**COMPLETE_FAULT;
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end
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else //(pte.v & ~pte.x & ~pte.w & ~pte.r) pointer to next level in page table
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next_state = SEND_REQUEST_2;
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next_state = 2**SEND_REQUEST_2;
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end
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end
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SEND_REQUEST_2 : if (l1_request.ack) next_state = WAIT_REQUEST_2;
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WAIT_REQUEST_2 : if (l1_response.data_valid) next_state = (access_valid & privilege_valid) ? COMPLETE_SUCCESS : COMPLETE_FAULT;
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COMPLETE_SUCCESS : next_state = IDLE;
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COMPLETE_FAULT : next_state = IDLE;
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default : next_state = IDLE;
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state[SEND_REQUEST_2] :
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if (l1_request.ack) begin
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next_state = 2**WAIT_REQUEST_2;
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end
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state[WAIT_REQUEST_2] :
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if (l1_response.data_valid) begin
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if (access_valid & privilege_valid)
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next_state = 2**COMPLETE_SUCCESS;
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else
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next_state = 2**COMPLETE_FAULT;
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end
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state[COMPLETE_SUCCESS], state[COMPLETE_FAULT] :
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next_state = 2**IDLE;
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endcase
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end
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always_ff @ (posedge clk) begin
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if (rst)
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state <= IDLE;
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state <= 2**IDLE;
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else
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state <= next_state;
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end
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@ -130,12 +154,12 @@ module mmu
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//TLB return path
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always_ff @ (posedge clk) begin
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if (l1_response.data_valid) begin
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mmu.new_phys_addr[19:10] <= pte.ppn1[9:0];
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mmu.new_phys_addr[9:0] <= (state == WAIT_REQUEST_2) ? pte.ppn0 : mmu.virtual_address[21:12];
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mmu.upper_physical_address[19:10] <= pte.ppn1[9:0];
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mmu.upper_physical_address[9:0] <= state[WAIT_REQUEST_2] ? pte.ppn0 : mmu.virtual_address[21:12];
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end
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end
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assign mmu.write_entry = (state == COMPLETE_SUCCESS);
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assign mmu.is_fault = (state == COMPLETE_FAULT);
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assign mmu.write_entry = state[COMPLETE_SUCCESS];
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assign mmu.is_fault = state[COMPLETE_FAULT];
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////////////////////////////////////////////////////
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//End of Implementation
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@ -144,7 +168,7 @@ module mmu
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////////////////////////////////////////////////////
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//Assertions
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mmu_spurious_l1_response:
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assert property (@(posedge clk) disable iff (rst) (l1_response.data_valid) |-> (state inside {WAIT_REQUEST_1, WAIT_REQUEST_2}))
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assert property (@(posedge clk) disable iff (rst) (l1_response.data_valid) |-> (state[WAIT_REQUEST_1] | state[WAIT_REQUEST_2]))
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else $error("mmu recieved response without a request");
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endmodule
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@ -79,7 +79,7 @@ module tlb_lut_ram #(
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assign new_entry.valid = ~gc_tlb_flush;
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assign new_entry.tag = virtual_tag;
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assign new_entry.phys_addr = mmu.new_phys_addr;
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assign new_entry.phys_addr = mmu.upper_physical_address;
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genvar i;
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generate
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