Wishbone bus signals renamed

Signed-off-by: Eric Matthews <ematthew@sfu.ca>

core/cva5.sv

@@ -42,7 +42,7 @@ module cva5
 
         axi_interface.master m_axi,
         avalon_interface.master m_avalon,
-        wishbone_interface.master m_wishbone,
+        wishbone_interface.master dwishbone,
         wishbone_interface.master iwishbone,
 
         output trace_outputs_t tr,
@@ -493,7 +493,7 @@ module cva5
         .sc_success (sc_success),                                       
         .m_axi (m_axi),
         .m_avalon (m_avalon),
-        .m_wishbone (m_wishbone),                                       
+        .dwishbone (dwishbone),                                       
         .data_bram (data_bram),
         .wb_snoop (wb_snoop),
         .retire_ids (retire_ids),

core/external_interfaces.sv

@@ -112,22 +112,25 @@ interface avalon_interface;
 endinterface
 
 interface wishbone_interface;
-    logic [31:0] addr;
-    logic we;
+    logic [31:0] adr;
+    logic [31:0] dat_w;
     logic [3:0] sel;
-    logic [31:0] readdata;
-    logic [31:0] writedata;
-    logic stb;
     logic cyc;
+    logic stb;
+    logic we;
+    logic cti;
+    logic bte;
+    logic [31:0] dat_r;
     logic ack;
+    logic err;
 
-    modport master (input readdata, ack,
-            output addr, we, sel, writedata, stb, cyc);
-    modport slave (output readdata, ack,
-            input addr, we, sel, writedata, stb, cyc);
+    modport master (input dat_r, ack, err,
+            output adr, dat_w, sel, cyc, stb, we, cti, bte);
+    modport slave (output dat_r, ack, err,
+            input adr, dat_w, sel, cyc, stb, we, cti, bte);
 
 `ifdef __CVA5_FORMAL__
-    modport formal (input readdata, ack, addr, we, sel, writedata, stb, cyc);
+    modport formal (input adr, dat_w, sel, cyc, stb, we, cti, bte, dat_r, ack, err);
 `endif
 
 endinterface

core/fetch.sv

@@ -239,7 +239,7 @@ module fetch
         wishbone_master iwishbone_bus (
             .clk (clk),
             .rst (rst),
-            .m_wishbone (iwishbone),
+            .wishbone (iwishbone),
             .ls (sub_unit[BUS_ID])
         );
     end

core/load_store_unit.sv

@@ -50,7 +50,7 @@ module load_store_unit
 
         axi_interface.master m_axi,
         avalon_interface.master m_avalon,
-        wishbone_interface.master m_wishbone,
+        wishbone_interface.master dwishbone,
 
         local_memory_interface.master data_bram,
 
@@ -338,7 +338,7 @@ endgenerate
                 wishbone_master wishbone_bus (
                     .clk (clk),
                     .rst (rst),
-                    .m_wishbone (m_wishbone),
+                    .wishbone (dwishbone),
                     .ls (sub_unit[BUS_ID])
                 );
             else if (CONFIG.PERIPHERAL_BUS_TYPE == AVALON_BUS)  begin

core/wishbone_master.sv

@@ -30,7 +30,7 @@ module wishbone_master
         input logic clk,
         input logic rst,
 
-        wishbone_interface.master m_wishbone,
+        wishbone_interface.master wishbone,
         memory_sub_unit_interface.responder ls
     );
     //implementation
@@ -38,16 +38,16 @@ module wishbone_master
 
     always_ff @ (posedge clk) begin
         if (ls.new_request) begin
-            m_wishbone.addr <= ls.addr;
-            m_wishbone.we <= ls.we;
-            m_wishbone.sel <= ls.be;
-            m_wishbone.writedata <= ls.data_in;
+            wishbone.adr <= ls.addr;
+            wishbone.we <= ls.we;
+            wishbone.sel <= ls.be;
+            wishbone.dat_w <= ls.data_in;
         end
     end
 
     set_clr_reg_with_rst #(.SET_OVER_CLR(0), .WIDTH(1), .RST_VALUE(1)) ready_m (
       .clk, .rst,
-      .set(m_wishbone.ack),
+      .set(wishbone.ack),
       .clr(ls.new_request),
       .result(ls.ready)
     );
@@ -55,31 +55,31 @@ module wishbone_master
     always_ff @ (posedge clk) begin
         if (rst)
             ls.data_valid <= 0;
-        else if (~m_wishbone.we & m_wishbone.ack)
+        else if (~wishbone.we & wishbone.ack)
             ls.data_valid <= 1;
         else
             ls.data_valid <= 0;
     end
 
     always_ff @ (posedge clk) begin
-        if (m_wishbone.ack)
-            ls.data_out <= m_wishbone.readdata;
+        if (wishbone.ack)
+            ls.data_out <= wishbone.dat_r;
         else
             ls.data_out <= 0;
     end
 
     always_ff @ (posedge clk) begin
         if (rst) begin
-            m_wishbone.stb <= 0;
-            m_wishbone.cyc <= 0;
+            wishbone.stb <= 0;
+            wishbone.cyc <= 0;
         end
         else if (ls.new_request) begin
-            m_wishbone.stb <= 1;
-            m_wishbone.cyc <= 1;
+            wishbone.stb <= 1;
+            wishbone.cyc <= 1;
         end
-        else if (m_wishbone.ack) begin
-            m_wishbone.stb <= 0;
-            m_wishbone.cyc <= 0;
+        else if (wishbone.ack) begin
+            wishbone.stb <= 0;
+            wishbone.cyc <= 0;
         end
     end
 

core/xilinx/cva5_wrapper_xilinx.sv

@@ -82,7 +82,7 @@ module cva5_wrapper_xilinx
 
     //Unused outputs
     avalon_interface m_avalon ();
-    wishbone_interface m_wishbone ();
+    wishbone_interface dwishbone ();
     wishbone_interface iwishbone ();
     trace_outputs_t tr;
     logic timer_interrupt;

examples/zedboard/cva5_wrapper.sv

@@ -66,7 +66,7 @@ module cva5_wrapper (
 
     axi_interface m_axi();
     avalon_interface m_avalon();
-    wishbone_interface m_wishbone();
+    wishbone_interface dwishbone();
     wishbone_interface iwishbone();
     l2_requester_interface l2[L2_NUM_PORTS-1:0]();
     l2_memory_interface mem();

test_benches/cva5_tb.sv

@@ -172,7 +172,7 @@ module cva5_tb
 
     axi_interface m_axi();
     avalon_interface m_avalon();
-    wishbone_interface m_wishbone();
+    wishbone_interface dwishbone();
 
     l2_requester_interface l2[L2_NUM_PORTS-1:0]();
     l2_memory_interface mem();

test_benches/verilator/AXI_DDR_simulation/axi_l2_test.sv

@@ -184,7 +184,7 @@ module axi_l2_test # (
     axi_interface m_axi();
     //axi_interface ddr_axi();
     avalon_interface m_avalon();
-    wishbone_interface m_wishbone();
+    wishbone_interface dwishbone();
 
     trace_outputs_t tr;
 

test_benches/verilator/cva5_sim.sv

@@ -235,7 +235,7 @@ module cva5_sim
     axi_interface m_axi();
     //axi_interface ddr_axi();
     avalon_interface m_avalon();
-    wishbone_interface m_wishbone();
+    wishbone_interface dwishbone();
     wishbone_interface iwishbone();
 
     trace_outputs_t tr;