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Revert supervisor timer interrupt changes

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This commit is contained in:
Chris Keilbart 2024-11-05 15:05:16 -08:00
parent 5bcb65ee55
commit 0cd4dafff2
2 changed files with 4 additions and 2 deletions
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2
core/execution_units/csr_unit.sv
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@ -545,6 +545,8 @@ if (CONFIG.MODES == MSU) begin : gen_supervisor_interrupts
//STIP
if (CONFIG.CSRS.INCLUDE_SSTC & menvcfgh.stce)
stip <= stip_stimecmp;
else if (s_interrupt.timer) //Temporary workaround; supervisor timer interrupts should not be external
stip <= 1;
else if (mwrite_en(MIP))
stip <= next_csr_mip_casted.stip;

4
examples/litex/litex_wrapper.sv
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@ -195,10 +195,10 @@ module litex_wrapper
};
assign m_interrupt[i].software = msip[i];
assign m_interrupt[i].timer = mtip[i];
assign m_interrupt[i].timer = 0; //Temporary workaround; should be MTIP
assign m_interrupt[i].external = meip[i];
assign s_interrupt[i].software = 0; //Not possible
assign s_interrupt[i].timer = 0; //Handled internally
assign s_interrupt[i].timer = mtip[i]; //Temporary workaround; should be 0
assign s_interrupt[i].external = seip[i];
cva5 #(.CONFIG(STANDARD_CONFIG_I)) cpu(