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Merge pull request #3 from e-matthews/rename

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Taiga to CVA5 renaming
This commit is contained in:
Mike Thompson 2022-03-07 16:41:14 -05:00 • committed by GitHub
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93 changed files with 645 additions and 636 deletions
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2
README.md
View file

@ -8,7 +8,7 @@ The CVA5 is derived from the Taiga Project from Simon Fraser University.
The pipeline has been designed to support parallel, variable-latency execution units and to readily support the inclusion of new execution units.
![CVA5 Block Diagram](examples/zedboard/taiga_small.png)
![CVA5 Block Diagram](examples/zedboard/cva5_small.png)
## Documentation and Project Setup

4
core/addr_hash.sv
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@ -22,9 +22,9 @@
module addr_hash
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
(
input logic clk,

4
core/alu_unit.sv
View file

@ -22,9 +22,9 @@
module alu_unit
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
(
input logic clk,

4
core/amo_alu.sv
View file

@ -22,9 +22,9 @@
module amo_alu
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
(
input amo_alu_inputs_t amo_alu_inputs,

4
core/avalon_master.sv
View file

@ -22,9 +22,9 @@
module avalon_master
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
(
input logic clk,

4
core/axi_master.sv
View file

@ -22,9 +22,9 @@
module axi_master
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
(
input logic clk,

4
core/axi_to_arb.sv
View file

@ -22,9 +22,9 @@
module axi_to_arb
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
import l2_config_and_types::*;
(

4
core/barrel_shifter.sv
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@ -22,9 +22,9 @@
module barrel_shifter
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
(
input logic[31:0] shifter_input,

4
core/binary_occupancy.sv
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@ -22,8 +22,8 @@
module binary_occupancy
import taiga_config::*;
import taiga_types::*;
import cva5_config::*;
import cva5_types::*;
#(parameter DEPTH = 4)
(

4
core/branch_comparator.sv
View file

@ -22,9 +22,9 @@
module branch_comparator
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
(
input logic less_than,

4
core/branch_predictor.sv
View file

@ -22,9 +22,9 @@
module branch_predictor
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
# (
parameter cpu_config_t CONFIG = EXAMPLE_CONFIG

4
core/branch_predictor_ram.sv
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@ -22,8 +22,8 @@
module branch_predictor_ram
import taiga_config::*;
import taiga_types::*;
import cva5_config::*;
import cva5_types::*;
#(
parameter C_DATA_WIDTH = 20,

4
core/branch_unit.sv
View file

@ -22,9 +22,9 @@
module branch_unit
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
# (
parameter cpu_config_t CONFIG = EXAMPLE_CONFIG

4
core/byte_en_BRAM.sv
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@ -24,8 +24,8 @@
module byte_en_BRAM
import taiga_config::*;
import taiga_types::*;
import cva5_config::*;
import cva5_types::*;
import riscv_types::*;
#(

2
core/csr_types.sv
View file

@ -21,7 +21,7 @@
*/
package csr_types;
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
const logic [1:0] CSR_READ_ONLY = 2'b11;

4
core/csr_unit.sv
View file

@ -22,9 +22,9 @@
module csr_unit
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
import csr_types::*;
# (

8
core/taiga.sv → core/cva5.sv
View file

@ -22,12 +22,12 @@
module taiga
module cva5
import taiga_config::*;
import cva5_config::*;
import l2_config_and_types::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
#(
parameter cpu_config_t CONFIG = EXAMPLE_CONFIG
@ -640,7 +640,7 @@ module taiga
////////////////////////////////////////////////////
//Trace Interface
generate if (ENABLE_TRACE_INTERFACE) begin : gen_taiga_trace
generate if (ENABLE_TRACE_INTERFACE) begin : gen_cva5_trace
always_ff @(posedge clk) begin
tr.events.early_branch_correction <= tr_early_branch_correction;
tr.events.operand_stall <= tr_operand_stall;

2
core/taiga_config.sv → core/cva5_config.sv
View file

@ -20,7 +20,7 @@
* Eric Matthews <ematthew@sfu.ca>
*/
package taiga_config;
package cva5_config;
////////////////////////////////////////////////////
//Vendor Selection

6
core/taiga_fifo.sv → core/cva5_fifo.sv
View file

@ -25,11 +25,11 @@
* Intended for small FIFO depths.
* For continuous operation when full, enqueing side must inspect pop signal
*/
module taiga_fifo
module cva5_fifo
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
#(
parameter DATA_WIDTH = 70,

8
core/taiga_types.sv → core/cva5_types.sv
View file

@ -20,8 +20,8 @@
* Eric Matthews <ematthew@sfu.ca>
*/
package taiga_types;
import taiga_config::*;
package cva5_types;
import cva5_config::*;
import riscv_types::*;
import csr_types::*;
@ -313,7 +313,7 @@ package taiga_types;
logic rs2_forwarding_needed;
logic rs1_and_rs2_forwarding_needed;
} taiga_trace_events_t;
} cva5_trace_events_t;
typedef struct packed {
logic [31:0] pc;
@ -324,7 +324,7 @@ package taiga_types;
typedef struct packed {
logic [31:0] instruction_pc_dec;
logic [31:0] instruction_data_dec;
taiga_trace_events_t events;
cva5_trace_events_t events;
} trace_outputs_t;
endpackage

4
core/dbram.sv
View file

@ -22,8 +22,8 @@
module dbram
import taiga_config::*;
import taiga_types::*;
import cva5_config::*;
import cva5_types::*;
(
input logic clk,

4
core/dcache.sv
View file

@ -22,9 +22,9 @@
module dcache
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
# (
parameter cpu_config_t CONFIG = EXAMPLE_CONFIG

4
core/ddata_bank.sv
View file

@ -22,8 +22,8 @@
module ddata_bank
import taiga_config::*;
import taiga_types::*;
import cva5_config::*;
import cva5_types::*;
#(
parameter LINES = 2048

4
core/decode_and_issue.sv
View file

@ -22,9 +22,9 @@
module decode_and_issue
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
import csr_types::*;
# (

6
core/div_unit.sv
View file

@ -22,9 +22,9 @@
module div_unit
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
(
input logic clk,
@ -121,7 +121,7 @@ module div_unit
//Input FIFO
//Currently just a register (DEPTH=1). As one div instruction can be in-progress
//and one in this input "fifo," we can support two in-flight div ops.
taiga_fifo #(.DATA_WIDTH($bits(div_fifo_inputs_t)), .FIFO_DEPTH(1))
cva5_fifo #(.DATA_WIDTH($bits(div_fifo_inputs_t)), .FIFO_DEPTH(1))
div_input_fifo (
.clk (clk),
.rst (rst),

4
core/dtag_banks.sv
View file

@ -22,8 +22,8 @@
module dtag_banks
import taiga_config::*;
import taiga_types::*;
import cva5_config::*;
import cva5_types::*;
# (
parameter cpu_config_t CONFIG = EXAMPLE_CONFIG,

17
core/external_interfaces.sv
View file

@ -21,7 +21,7 @@
*/
interface axi_interface;
import taiga_config::*;
import cva5_config::*;
logic arready;
logic arvalid;
@ -68,7 +68,6 @@ interface axi_interface;
output arvalid, araddr, arlen, arsize, arburst, arcache, arid, rready, awvalid, awaddr, awlen, awsize, awburst, awcache, awid,
wvalid, wdata, wstrb, wlast, bready);
modport slave (input arvalid, araddr, arlen, arsize, arburst, arcache,
rready,
awvalid, awaddr, awlen, awsize, awburst, awcache, arid,
@ -79,11 +78,13 @@ interface axi_interface;
wready,
bvalid, bresp, bid);
`ifdef __CVA5_FORMAL__
modport formal (input arready, arvalid, araddr, arlen, arsize, arburst, arcache,
rready, rvalid, rdata, rresp, rlast, rid,
awready, awvalid, awaddr, awlen, awsize, awburst, awcache, arid,
wready, wvalid, wdata, wstrb, wlast, awid,
bready, bvalid, bresp, bid);
`endif
endinterface
@ -102,8 +103,11 @@ interface avalon_interface;
output addr, read, write, byteenable, writedata);
modport slave (output readdata, waitrequest, readdatavalid, writeresponsevalid,
input addr, read, write, byteenable, writedata);
`ifdef __CVA5_FORMAL__
modport formal (input readdata, waitrequest, readdatavalid, writeresponsevalid,
addr, read, write, byteenable, writedata);
`endif
endinterface
@ -121,7 +125,10 @@ interface wishbone_interface;
output addr, we, sel, writedata, stb, cyc);
modport slave (output readdata, ack,
input addr, we, sel, writedata, stb, cyc);
`ifdef __CVA5_FORMAL__
modport formal (input readdata, ack, addr, we, sel, writedata, stb, cyc);
`endif
endinterface
@ -141,7 +148,10 @@ interface l1_arbiter_request_interface;
modport master (output addr, data, rnw, be, size, is_amo, amo, request, input ack);
modport slave (input addr, data, rnw, be, size, is_amo, amo, request, output ack);
`ifdef __CVA5_FORMAL__
modport formal (input addr, data, rnw, be, size, is_amo, amo, request, ack);
`endif
endinterface
@ -154,7 +164,10 @@ interface l1_arbiter_return_interface;
modport master (input inv_addr, inv_valid, data, data_valid, output inv_ack);
modport slave (output inv_addr, inv_valid, data, data_valid, input inv_ack);
`ifdef __CVA5_FORMAL__
modport formal (input inv_addr, inv_valid, data, data_valid, inv_ack);
`endif
endinterface

6
core/fetch.sv
View file

@ -22,9 +22,9 @@
module fetch
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
# (
parameter cpu_config_t CONFIG = EXAMPLE_CONFIG
@ -197,7 +197,7 @@ module fetch
assign fetch_attr_fifo.data_in = fetch_attr_next;
taiga_fifo #(.DATA_WIDTH($bits(fetch_attributes_t)), .FIFO_DEPTH(NEXT_ID_DEPTH))
cva5_fifo #(.DATA_WIDTH($bits(fetch_attributes_t)), .FIFO_DEPTH(NEXT_ID_DEPTH))
attributes_fifo (
.clk (clk),
.rst (flush_or_rst),

4
core/gc_unit.sv
View file

@ -22,9 +22,9 @@
module gc_unit
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
import csr_types::*;
# (

4
core/ibram.sv
View file

@ -22,8 +22,8 @@
module ibram
import taiga_config::*;
import taiga_types::*;
import cva5_config::*;
import cva5_types::*;
(
input logic clk,

4
core/icache.sv
View file

@ -22,9 +22,9 @@
module icache
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
# (
parameter cpu_config_t CONFIG = EXAMPLE_CONFIG

2
core/illegal_instruction_checker.sv
View file

@ -22,7 +22,7 @@
module illegal_instruction_checker
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
# (

4
core/instruction_metadata_and_id_management.sv
View file

@ -22,9 +22,9 @@
module instruction_metadata_and_id_management
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
# (
parameter cpu_config_t CONFIG = EXAMPLE_CONFIG

4
core/intel/intel_byte_enable_ram.sv
View file

@ -24,9 +24,9 @@
module intel_byte_enable_ram
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
#(
parameter LINES = 8192,

22
core/interfaces.sv
View file

@ -21,7 +21,7 @@
*/
interface branch_predictor_interface;
import taiga_types::*;
import cva5_types::*;
//Fetch signals
logic [31:0] if_pc;
@ -52,7 +52,7 @@ interface branch_predictor_interface;
endinterface
interface unit_issue_interface;
import taiga_types::*;
import cva5_types::*;
logic possible_issue;
logic new_request;
@ -67,7 +67,7 @@ endinterface
interface unit_writeback_interface;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
logic ack;
@ -102,7 +102,7 @@ endinterface
interface exception_interface;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
logic valid;
logic ack;
@ -117,7 +117,7 @@ endinterface
interface csr_exception_interface;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
logic valid;
exception_code_t code;
@ -193,7 +193,7 @@ endinterface
interface load_store_queue_interface;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
logic [31:0] addr;
logic load;
@ -223,7 +223,7 @@ endinterface
interface writeback_store_interface;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
id_t id_needed;
logic possibly_waiting;
@ -321,9 +321,9 @@ interface unsigned_division_interface #(parameter DATA_WIDTH = 32);
endinterface
interface renamer_interface #(parameter NUM_WB_GROUPS = 2);
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
rs_addr_t rd_addr;
rs_addr_t rs_addr [REGFILE_READ_PORTS];
@ -347,9 +347,9 @@ interface renamer_interface #(parameter NUM_WB_GROUPS = 2);
endinterface
interface register_file_issue_interface #(parameter NUM_WB_GROUPS = 2);
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
//read interface
phys_addr_t phys_rs_addr [REGFILE_READ_PORTS];

4
core/itag_banks.sv
View file

@ -22,8 +22,8 @@
module itag_banks
import taiga_config::*;
import taiga_types::*;
import cva5_config::*;
import cva5_types::*;
# (
parameter cpu_config_t CONFIG = EXAMPLE_CONFIG,

4
core/l1_arbiter.sv
View file

@ -22,9 +22,9 @@
module l1_arbiter
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
import l2_config_and_types::*;
# (

6
core/load_queue.sv
View file

@ -22,9 +22,9 @@
module load_queue
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
# (
parameter SQ_DEPTH = 4
@ -46,7 +46,7 @@ module load_queue
////////////////////////////////////////////////////
//Implementation
taiga_fifo #(.DATA_WIDTH(LQ_WIDTH), .FIFO_DEPTH(MAX_IDS)) load_queue_fifo (
cva5_fifo #(.DATA_WIDTH(LQ_WIDTH), .FIFO_DEPTH(MAX_IDS)) load_queue_fifo (
.clk(clk),
.rst(rst),
.fifo(load_fifo)

4
core/load_store_queue.sv
View file

@ -22,9 +22,9 @@
module load_store_queue //ID-based input buffer for Load/Store Unit
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
(
input logic clk,

6
core/load_store_unit.sv
View file

@ -22,9 +22,9 @@
module load_store_unit
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
# (
parameter cpu_config_t CONFIG = EXAMPLE_CONFIG
@ -268,7 +268,7 @@ endgenerate
.one_hot (sub_unit_address_match),
.int_out (load_attributes_in.subunit_id)
);
taiga_fifo #(.DATA_WIDTH($bits(load_attributes_t)), .FIFO_DEPTH(ATTRIBUTES_DEPTH)) attributes_fifo (
cva5_fifo #(.DATA_WIDTH($bits(load_attributes_t)), .FIFO_DEPTH(ATTRIBUTES_DEPTH)) attributes_fifo (
.clk (clk),
.rst (rst),
.fifo (load_attributes)

2
core/lutrams/lutram_1w_mr.sv
View file

@ -22,7 +22,7 @@
module lutram_1w_mr
import taiga_config::*;
import cva5_config::*;
#(
parameter WIDTH = 32,

4
core/mmu.sv
View file

@ -22,9 +22,9 @@
module mmu
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
import csr_types::*;
(

4
core/mul_unit.sv
View file

@ -22,9 +22,9 @@
module mul_unit
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
(
input logic clk,

6
core/ras.sv
View file

@ -22,9 +22,9 @@
module ras
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
# (
parameter cpu_config_t CONFIG = EXAMPLE_CONFIG
@ -52,7 +52,7 @@ module ras
//On a speculative branch, save the current stack pointer
//Restored if branch is misspredicted (gc_fetch_flush)
taiga_fifo #(.DATA_WIDTH(RAS_DEPTH_W), .FIFO_DEPTH(MAX_IDS))
cva5_fifo #(.DATA_WIDTH(RAS_DEPTH_W), .FIFO_DEPTH(MAX_IDS))
read_index_fifo (.clk, .rst(rst | gc.fetch_flush | early_branch_flush_ras_adjust), .fifo(ri_fifo));
assign ri_fifo.data_in = read_index;

4
core/reg_inuse.sv
View file

@ -20,8 +20,8 @@
* Eric Matthews <ematthew@sfu.ca>
*/
import taiga_config::*;
import taiga_types::*;
import cva5_config::*;
import cva5_types::*;
module reg_inuse (
input logic clk,

4
core/register_bank.sv
View file

@ -22,9 +22,9 @@
module register_bank
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
#(
parameter NUM_READ_PORTS = 2

4
core/register_file.sv
View file

@ -22,9 +22,9 @@
module register_file
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
# (
parameter cpu_config_t CONFIG = EXAMPLE_CONFIG

4
core/register_free_list.sv
View file

@ -27,9 +27,9 @@
*/
module register_free_list
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
#(
parameter DATA_WIDTH = 70,

6
core/renamer.sv
View file

@ -22,9 +22,9 @@
module renamer
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
# (
parameter cpu_config_t CONFIG = EXAMPLE_CONFIG
@ -100,7 +100,7 @@ module renamer
////////////////////////////////////////////////////
//Inuse list FIFO
taiga_fifo #(.DATA_WIDTH($bits(renamer_metadata_t)), .FIFO_DEPTH(32)) inuse_list_fifo (
cva5_fifo #(.DATA_WIDTH($bits(renamer_metadata_t)), .FIFO_DEPTH(32)) inuse_list_fifo (
.clk (clk),
.rst (rst),
.fifo (inuse_list)

2
core/riscv_types.sv
View file

@ -21,7 +21,7 @@
*/
package riscv_types;
import taiga_config::*;
import cva5_config::*;
localparam XLEN = 32;
localparam PAGE_ADDR_W = 12;

4
core/set_clr_reg_with_rst.sv
View file

@ -27,8 +27,8 @@
*/
module set_clr_reg_with_rst
import taiga_config::*;
import taiga_types::*;
import cva5_config::*;
import cva5_types::*;
#(parameter SET_OVER_CLR = 0, parameter WIDTH = 16, parameter logic[WIDTH-1:0] RST_VALUE = '0)
(

4
core/shift_counter.sv
View file

@ -22,8 +22,8 @@
module shift_counter
import taiga_config::*;
import taiga_types::*;
import cva5_config::*;
import cva5_types::*;
#(parameter DEPTH = 16)
(

4
core/store_queue.sv
View file

@ -22,9 +22,9 @@
module store_queue
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
# (
parameter DEPTH = 4

4
core/tlb_lut_ram.sv
View file

@ -24,9 +24,9 @@
module tlb_lut_ram
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
#(
parameter WAYS = 2,

4
core/toggle_memory.sv
View file

@ -22,8 +22,8 @@
module toggle_memory
import taiga_config::*;
import taiga_types::*;
import cva5_config::*;
import cva5_types::*;
# (
parameter DEPTH = 8,

4
core/toggle_memory_set.sv
View file

@ -22,8 +22,8 @@
module toggle_memory_set
import taiga_config::*;
import taiga_types::*;
import cva5_config::*;
import cva5_types::*;
# (
parameter DEPTH = 64,

4
core/wishbone_master.sv
View file

@ -22,9 +22,9 @@
module wishbone_master
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
(
input logic clk,

4
core/writeback.sv
View file

@ -22,9 +22,9 @@
module writeback
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
# (
parameter cpu_config_t CONFIG = EXAMPLE_CONFIG,

8
core/xilinx/taiga_wrapper_xilinx.sv → core/xilinx/cva5_wrapper_xilinx.sv
View file

@ -22,10 +22,10 @@
module taiga_wrapper_xilinx
module cva5_wrapper_xilinx
import taiga_config::*;
import taiga_types::*;
import cva5_config::*;
import cva5_types::*;
import l2_config_and_types::*;
(
@ -128,7 +128,7 @@ module taiga_wrapper_xilinx
assign m_axi_bresp = m_axi.bresp;
//assign m_axi_bid = m_axi.bid;
taiga cpu(.*);
cva5 cpu(.*);
endmodule

4
core/xilinx/xilinx_byte_enable_ram.sv
View file

@ -22,9 +22,9 @@
module xilinx_byte_enable_ram
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
#(
parameter LINES = 4096,

2
debug_module/debug_module.sv
View file

@ -31,7 +31,7 @@ module debug_module (
//assign DMC.zero2 = 0;
//read-only reg
//same for all Taiga cores
//same for all cva5 cores
hart_info_t hart_info;
assign hart_info.zero1 = 0;

2
examples/zedboard/README.md
View file

@ -1,7 +1,7 @@
Creating a Hardware Project for the Zedboard
-----------
We have provided a TCL script that automates the creation of a Taiga system on a zedBoard through Vivado.
We have provided a TCL script that automates the creation of a CVA5 system on a zedBoard through Vivado.
We also provide the manual steps that the script automate.
Hardware setup scripts and steps found here: [Hardware Setup](https://gitlab.com/sfu-rcl/taiga-project/-/wikis/Hardware-Setup)

0
examples/zedboard/taiga.png → examples/zedboard/cva5.png
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Before

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After

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Before After
Before After

0
examples/zedboard/taiga_small.png → examples/zedboard/cva5_small.png
View file

Side by side Swipe Overlay

Before

Width:  |  Height:  |  Size: 43 KiB

After

Width:  |  Height:  |  Size: 43 KiB

Before After
Before After

8
examples/zedboard/taiga_wrapper.sv → examples/zedboard/cva5_wrapper.sv
View file

@ -20,11 +20,11 @@
* Eric Matthews <ematthew@sfu.ca>
*/
import taiga_config::*;
import taiga_types::*;
import cva5_config::*;
import cva5_types::*;
import l2_config_and_types::*;
module taiga_wrapper (
module cva5_wrapper (
input logic sys_clk,
input logic ext_reset,
@ -230,7 +230,7 @@ module taiga_wrapper (
local_memory_interface instruction_bram();
local_memory_interface data_bram();
taiga cpu(.*, .l2(l2[0]));
cva5 cpu(.*, .l2(l2[0]));
//design_2 infra(.*);

58
examples/zedboard/scripts/taiga-ip-core-base.tcl → examples/zedboard/scripts/cva5-ip-core-base.tcl
View file

@ -1,7 +1,7 @@
#*****************************************************************************************
# Vivado (TM) v2019.2.1 (64-bit)
#
# taiga-ip-core-base.tcl: Tcl script for re-creating project 'taiga-ip-core-base'
# cva5-ip-core-base.tcl: Tcl script for re-creating project 'cva5-ip-core-base'
#
# Generated by Vivado on Fri Jul 24 11:19:38 PDT 2020
# IP Build 2729494 on Thu Dec 5 07:38:25 MST 2019
@ -14,27 +14,11 @@
# original project, however they will not be launched automatically. To regenerate the
# run results please launch the synthesis/implementation runs as needed.
#
#*****************************************************************************************
# NOTE: In order to use this script for source control purposes, please make sure that the
# following files are added to the source control system:-
#
# 1. This project restoration tcl script (taiga-ip-core-base.tcl) that was generated.
#
# 2. The following source(s) files that were local or imported into the original project.
# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
#
# "/home/zaguila/Documents/Research/taiga-example-systems/zedboard-no-cache/taiga-ip-core-base/taiga-ip-core-base.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v"
# "/home/zaguila/Documents/Research/taiga-example-systems/zedboard-no-cache/taiga-ip-core-base/taiga-ip-core-base.srcs/constrs_1/imports/Research/zedboard_master_XDC_RevC_D_v3.xdc"
#
# 3. The following remote source files that were added to the original project:-
#
# <none>
#
#*****************************************************************************************
# Set the reference directory for source file relative paths (by default the value is script directory path)
set origin_dir [ file dirname [ file normalize [ info script ] ] ]
source $origin_dir/../../../scripts/xilinx/taiga_wrapper_IP.tcl
source $origin_dir/../../../scripts/xilinx/cva5_wrapper_IP.tcl
set origin_dir [ file dirname [ file normalize [ info script ] ] ]
source $origin_dir/../../../scripts/xilinx/local_memory_IP.tcl
@ -46,7 +30,7 @@ if { [info exists ::origin_dir_loc] } {
}
# Set the project name
set _xil_proj_name_ "taiga-ip-core-base-test"
set _xil_proj_name_ "cva5-ip-core-base-test"
# Use project name variable, if specified in the tcl shell
if { [info exists ::user_project_name] } {
@ -54,7 +38,7 @@ if { [info exists ::user_project_name] } {
}
variable script_file
set script_file "taiga-ip-core-base.tcl"
set script_file "cva5-ip-core-base.tcl"
# Help information for this script
proc print_help {} {
@ -102,7 +86,7 @@ if { $::argc > 0 } {
}
# Set the directory path for the original project from where this script was exported
#Not used: set orig_proj_dir "[file normalize "$origin_dir/taiga-ip-core-test"]"
#Not used: set orig_proj_dir "[file normalize "$origin_dir/cva5-ip-core-test"]"
# Create project
set project_location "$origin_dir"
@ -174,7 +158,7 @@ if {[string equal [get_filesets -quiet sources_1] ""]} {
# Set IP repository paths
set obj [get_filesets sources_1]
set_property "ip_repo_paths" "[file normalize "$origin_dir/../../../scripts/xilinx/local_memory_IP"] [file normalize "$origin_dir/../../../scripts/xilinx/taiga_wrapper_IP"]" $obj
set_property "ip_repo_paths" "[file normalize "$origin_dir/../../../scripts/xilinx/local_memory_IP"] [file normalize "$origin_dir/../../../scripts/xilinx/cva5_wrapper_IP"]" $obj
# Rebuild user ip_repo's index before adding any source files
update_ip_catalog -rebuild
@ -333,7 +317,7 @@ proc cr_bd_design_1 { parentCell } {
user.org:user:local_mem:1.0\
xilinx.com:ip:proc_sys_reset:5.0\
xilinx.com:ip:processing_system7:5.5\
user.org:user:taiga_wrapper_xilinx:1.0\
user.org:user:cva5_wrapper_xilinx:1.0\
"
set list_ips_missing ""
@ -416,26 +400,26 @@ proc cr_bd_design_1 { parentCell } {
CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
] $processing_system7_0
# Create instance: taiga_wrapper_xilinx_0, and set properties
set taiga_wrapper_xilinx_0 [ create_bd_cell -type ip -vlnv user.org:user:taiga_wrapper_xilinx:1.0 taiga_wrapper_xilinx_0 ]
# Create instance: cva5_wrapper_xilinx_0, and set properties
set cva5_wrapper_xilinx_0 [ create_bd_cell -type ip -vlnv user.org:user:cva5_wrapper_xilinx:1.0 cva5_wrapper_xilinx_0 ]
# Create interface connections
connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins axi_interconnect_0/M00_AXI] [get_bd_intf_pins axi_uart16550_0/S_AXI]
connect_bd_intf_net -intf_net taiga_wrapper_xilinx_0_data_bram [get_bd_intf_pins local_mem_0/portB] [get_bd_intf_pins taiga_wrapper_xilinx_0/data_bram]
connect_bd_intf_net -intf_net taiga_wrapper_xilinx_0_instruction_bram [get_bd_intf_pins local_mem_0/portA] [get_bd_intf_pins taiga_wrapper_xilinx_0/instruction_bram]
connect_bd_intf_net -intf_net taiga_wrapper_xilinx_0_m_axi [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins taiga_wrapper_xilinx_0/m_axi]
connect_bd_intf_net -intf_net cva5_wrapper_xilinx_0_data_bram [get_bd_intf_pins local_mem_0/portB] [get_bd_intf_pins cva5_wrapper_xilinx_0/data_bram]
connect_bd_intf_net -intf_net cva5_wrapper_xilinx_0_instruction_bram [get_bd_intf_pins local_mem_0/portA] [get_bd_intf_pins cva5_wrapper_xilinx_0/instruction_bram]
connect_bd_intf_net -intf_net cva5_wrapper_xilinx_0_m_axi [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins cva5_wrapper_xilinx_0/m_axi]
# Create port connections
connect_bd_net -net axi_uart16550_0_sout [get_bd_ports sout] [get_bd_pins axi_uart16550_0/sout]
connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins proc_sys_reset_0/interconnect_aresetn]
connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins axi_uart16550_0/s_axi_aresetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
connect_bd_net -net proc_sys_reset_0_peripheral_reset [get_bd_pins local_mem_0/rst] [get_bd_pins proc_sys_reset_0/peripheral_reset] [get_bd_pins taiga_wrapper_xilinx_0/rst]
connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_uart16550_0/s_axi_aclk] [get_bd_pins local_mem_0/clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins taiga_wrapper_xilinx_0/clk]
connect_bd_net -net proc_sys_reset_0_peripheral_reset [get_bd_pins local_mem_0/rst] [get_bd_pins proc_sys_reset_0/peripheral_reset] [get_bd_pins cva5_wrapper_xilinx_0/rst]
connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_uart16550_0/s_axi_aclk] [get_bd_pins local_mem_0/clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins cva5_wrapper_xilinx_0/clk]
connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins processing_system7_0/FCLK_RESET0_N]
connect_bd_net -net sin_0_1 [get_bd_ports sin] [get_bd_pins axi_uart16550_0/sin]
# Create address segments
assign_bd_address -offset 0x60000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces taiga_wrapper_xilinx_0/m_axi] [get_bd_addr_segs axi_uart16550_0/S_AXI/Reg] -force
assign_bd_address -offset 0x60000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cva5_wrapper_xilinx_0/m_axi] [get_bd_addr_segs axi_uart16550_0/S_AXI/Reg] -force
# Perform GUI Layout
regenerate_bd_layout -layout_string {
@ -452,7 +436,7 @@ preplace inst proc_sys_reset_0 -pg 1 -lvl 2 -x 320 -y 110 -defaultsOSRD
preplace inst axi_uart16550_0 -pg 1 -lvl 1 -x 0 -y 260 -defaultsOSRD
preplace inst axi_interconnect_0 -pg 1 -lvl 4 -x 1130 -y 440 -defaultsOSRD
preplace inst local_mem_0 -pg 1 -lvl 4 -x 1130 -y 60 -defaultsOSRD
preplace inst taiga_wrapper_xilinx_0 -pg 1 -lvl 4 -x 1130 -y 220 -defaultsOSRD
preplace inst cva5_wrapper_xilinx_0 -pg 1 -lvl 4 -x 1130 -y 220 -defaultsOSRD
preplace netloc processing_system7_0_FCLK_CLK0 1 0 4 -130 70 130 10 520 10 960
preplace netloc processing_system7_0_FCLK_RESET0_N 1 1 3 140 0 NJ 0 930
preplace netloc proc_sys_reset_0_peripheral_reset 1 2 2 530J 30 950
@ -460,9 +444,9 @@ preplace netloc proc_sys_reset_0_peripheral_aresetn 1 0 3 -150 -10 NJ -10 500
preplace netloc sin_0_1 1 0 2 NJ 400 130
preplace netloc axi_uart16550_0_sout 1 1 4 NJ 270 NJ 270 930J 600 1300J
preplace netloc proc_sys_reset_0_interconnect_aresetn 1 2 2 510J 20 940
preplace netloc taiga_wrapper_xilinx_0_data_bram 1 3 2 970 -40 1300
preplace netloc taiga_wrapper_xilinx_0_m_axi 1 3 2 980 580 1290
preplace netloc taiga_wrapper_xilinx_0_instruction_bram 1 3 2 980 -30 1280
preplace netloc cva5_wrapper_xilinx_0_data_bram 1 3 2 970 -40 1300
preplace netloc cva5_wrapper_xilinx_0_m_axi 1 3 2 980 580 1290
preplace netloc cva5_wrapper_xilinx_0_instruction_bram 1 3 2 980 -30 1280
preplace netloc axi_interconnect_0_M00_AXI 1 0 5 -140 590 NJ 590 NJ 590 NJ 590 1280
levelinfo -pg 1 -170 0 320 730 1130 1320
pagesize -pg 1 -db -bbox -sgen -240 -270 1400 640
@ -482,7 +466,7 @@ set_property EXCLUDE_DEBUG_LOGIC "0" [get_files design_1.bd ]
set_property GENERATE_SYNTH_CHECKPOINT "1" [get_files design_1.bd ]
set_property IS_ENABLED "1" [get_files design_1.bd ]
set_property IS_GLOBAL_INCLUDE "0" [get_files design_1.bd ]
set_property IS_LOCKED "0" [get_files design_1.bd ]
# set_property IS_LOCKED "0" [get_files design_1.bd ]
set_property LIBRARY "xil_defaultlib" [get_files design_1.bd ]
set_property PATH_MODE "RelativeFirst" [get_files design_1.bd ]
set_property PFM_NAME "" [get_files design_1.bd ]

4
formal/interfaces/axi4_basic_props.sv
View file

@ -20,8 +20,8 @@
// Stuart Hoad <shoad@sfu.ca>
//
import taiga_config::*;
import taiga_types::*;
import cva5_config::*;
import cva5_types::*;
module axi4_basic_props(
input logic clk,

10
formal/models/taiga_fbm.sv → formal/models/cva5_fbm.sv
View file

@ -19,17 +19,17 @@
// Author(s):
// Stuart Hoad <shoad@sfu.ca>
//
// Taiga Formal Behavioural Model
// CVA5 Formal Behavioural Model
//****************************************************************************
//****************************************************************************
import taiga_config::*;
import cva5_config::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
module taiga_fbm (
module cva5_fbm (
input logic clk,
input logic rst,
@ -53,7 +53,7 @@ module taiga_fbm (
//****************************************************************************
// AXI constraints.
// Taiga does not deal with bad AXI responses, so need to constrain to avoid them
// CVA5 does not deal with bad AXI responses, so need to constrain to avoid them
// REVISIT add AXI protocol properties
axi4_basic_props
u_ppb_axi (

18
formal/models/taiga_formal_wrapper.sv → formal/models/cva5_formal_wrapper.sv
View file

@ -20,10 +20,10 @@
// Stuart Hoad <shoad@sfu.ca>
//
import taiga_config::*;
import taiga_types::*;
import cva5_config::*;
import cva5_types::*;
module taiga_formal_wrapper (
module cva5_formal_wrapper (
input logic clk,
input logic rst
@ -43,9 +43,9 @@ module taiga_formal_wrapper (
logic timer_interrupt;
logic ext_interrupt;
// Instance of Taiga core
taiga
u_taiga_core (
// Instance of CVA5 core
cva5
u_cva5_core (
.clk (clk),
.rst (rst),
.instruction_bram (instruction_bram.master),
@ -59,9 +59,9 @@ module taiga_formal_wrapper (
.interrupt (ext_interrupt)
);
// Instance of Taiga FBM
taiga_fbm
u_taiga_fbm (
// Instance of CVA5 FBM
cva5_fbm
u_cva5_fbm (
.clk (clk),
.rst (rst),
.instruction_bram (instruction_bram.formal),

73
formal/scripts/cva5_rtl.vfile Normal file
View file

@ -0,0 +1,73 @@
+incdir+${JG_CVA5_RTL_PATH}\
${JG_CVA5_RTL_PATH}/core/cva5_config.sv \
${JG_CVA5_RTL_PATH}/core/riscv_types.sv \
${JG_CVA5_RTL_PATH}/core/cva5_types.sv \
${JG_CVA5_RTL_PATH}/l2_arbiter/l2_config_and_types.sv \
${JG_CVA5_RTL_PATH}/l2_arbiter/l2_interfaces.sv \
${JG_CVA5_RTL_PATH}/l2_arbiter/l2_external_interfaces.sv \
${JG_CVA5_RTL_PATH}/local_memory/local_memory_interface.sv \
${JG_CVA5_RTL_PATH}/local_memory/local_mem.sv \
${JG_CVA5_RTL_PATH}/core/interfaces.sv \
${JG_CVA5_RTL_PATH}/core/external_interfaces.sv \
${JG_CVA5_RTL_PATH}/core/csr_types.sv \
${JG_CVA5_RTL_PATH}/core/csr_regs.sv \
${JG_CVA5_RTL_PATH}/core/gc_unit.sv \
${JG_CVA5_RTL_PATH}/core/branch_comparator.sv \
${JG_CVA5_RTL_PATH}/core/branch_unit.sv \
${JG_CVA5_RTL_PATH}/core/barrel_shifter.sv \
${JG_CVA5_RTL_PATH}/core/alu_unit.sv \
${JG_CVA5_RTL_PATH}/core/axi_master.sv \
${JG_CVA5_RTL_PATH}/core/avalon_master.sv \
${JG_CVA5_RTL_PATH}/core/wishbone_master.sv \
${JG_CVA5_RTL_PATH}/core/axi_to_arb.sv \
${JG_CVA5_RTL_PATH}/core/one_hot_occupancy.sv \
${JG_CVA5_RTL_PATH}/core/binary_occupancy.sv \
${JG_CVA5_RTL_PATH}/core/cva5_fifo.sv \
${JG_CVA5_RTL_PATH}/core/shift_counter.sv \
${JG_CVA5_RTL_PATH}/core/set_clr_reg_with_rst.sv \
${JG_CVA5_RTL_PATH}/core/intel/intel_byte_enable_ram.sv \
${JG_CVA5_RTL_PATH}/core/xilinx/xilinx_byte_enable_ram.sv \
${JG_CVA5_RTL_PATH}/core/byte_en_BRAM.sv \
${JG_CVA5_RTL_PATH}/core/one_hot_to_integer.sv \
${JG_CVA5_RTL_PATH}/core/cycler.sv \
${JG_CVA5_RTL_PATH}/core/tag_bank.sv \
${JG_CVA5_RTL_PATH}/core/dbram.sv \
${JG_CVA5_RTL_PATH}/core/ddata_bank.sv \
${JG_CVA5_RTL_PATH}/core/dtag_banks.sv \
${JG_CVA5_RTL_PATH}/core/amo_alu.sv \
${JG_CVA5_RTL_PATH}/core/dcache.sv \
${JG_CVA5_RTL_PATH}/core/addr_hash.sv \
${JG_CVA5_RTL_PATH}/core/load_queue.sv \
${JG_CVA5_RTL_PATH}/core/store_queue.sv \
${JG_CVA5_RTL_PATH}/core/load_store_queue.sv \
${JG_CVA5_RTL_PATH}/core/load_store_unit.sv \
${JG_CVA5_RTL_PATH}/core/ibram.sv \
${JG_CVA5_RTL_PATH}/core/itag_banks.sv \
${JG_CVA5_RTL_PATH}/core/icache.sv \
${JG_CVA5_RTL_PATH}/core/div_algorithms/div_radix2.sv \
${JG_CVA5_RTL_PATH}/core/clz.sv \
${JG_CVA5_RTL_PATH}/core/div_algorithms/div_quick_clz.sv \
${JG_CVA5_RTL_PATH}/core/div_algorithms/div_algorithm.sv \
${JG_CVA5_RTL_PATH}/core/div_unit.sv \
${JG_CVA5_RTL_PATH}/core/lut_ram.sv \
${JG_CVA5_RTL_PATH}/core/tlb_lut_ram.sv \
${JG_CVA5_RTL_PATH}/core/mmu.sv \
${JG_CVA5_RTL_PATH}/core/mul_unit.sv \
${JG_CVA5_RTL_PATH}/core/l1_arbiter.sv \
${JG_CVA5_RTL_PATH}/core/ras.sv \
${JG_CVA5_RTL_PATH}/core/branch_predictor_ram.sv \
${JG_CVA5_RTL_PATH}/core/branch_predictor.sv \
${JG_CVA5_RTL_PATH}/core/fetch.sv \
${JG_CVA5_RTL_PATH}/core/illegal_instruction_checker.sv \
${JG_CVA5_RTL_PATH}/core/decode_and_issue.sv \
${JG_CVA5_RTL_PATH}/core/regfile_bank_sel.sv \
${JG_CVA5_RTL_PATH}/core/register_file.sv \
${JG_CVA5_RTL_PATH}/core/register_file_and_writeback.sv \
${JG_CVA5_RTL_PATH}/core/placer_randomizer.sv \
${JG_CVA5_RTL_PATH}/l2_arbiter/l2_fifo.sv \
${JG_CVA5_RTL_PATH}/l2_arbiter/l2_reservation_logic.sv \
${JG_CVA5_RTL_PATH}/l2_arbiter/l2_round_robin.sv \
${JG_CVA5_RTL_PATH}/l2_arbiter/l2_arbiter.sv \
${JG_CVA5_RTL_PATH}/core/toggle_memory.sv \
${JG_CVA5_RTL_PATH}/core/instruction_metadata_and_id_management.sv \
${JG_CVA5_RTL_PATH}/core/cva5.sv \

16
formal/scripts/setup_taiga_dev.tcl → formal/scripts/setup_cva5_dev.tcl
View file

@ -19,25 +19,25 @@
# Author(s):
# Stuart Hoad <shoad@sfu.ca>
# Jasper FPV script for Taiga
# Jasper FPV script for CVA5
clear -all
set_engine_mode {Hp Ht L B I N Tri}
set SCRIPTS_PATH ../../Taiga-dev/formal/scripts
set JG_TAIGA_RTL_PATH ../../Taiga-dev
set SCRIPTS_PATH ../../cva5/formal/scripts
set JG_TAIGA_RTL_PATH ../../cva5
analyze -sv -f ${SCRIPTS_PATH}/taiga_rtl.vfile
analyze -sv ${JG_TAIGA_RTL_PATH}/formal/models/taiga_fbm.sv
analyze -sv -f ${SCRIPTS_PATH}/cva5_rtl.vfile
analyze -sv ${JG_TAIGA_RTL_PATH}/formal/models/cva5_fbm.sv
analyze -sv ${JG_TAIGA_RTL_PATH}/formal/interfaces/axi4_basic_props.sv
analyze -sv ${JG_TAIGA_RTL_PATH}/formal/models/taiga_formal_wrapper.sv
elaborate -top taiga_formal_wrapper \
analyze -sv ${JG_TAIGA_RTL_PATH}/formal/models/cva5_formal_wrapper.sv
elaborate -top cva5_formal_wrapper \
-bbox_a 17000 -bbox_mul 67 \
-bbox_m sixinput_pop_count
reset rst
clock clk
assume -from_assert <embedded>::taiga_formal_wrapper.u_taiga_fbm.u_ppb_axi.env_*
assume -from_assert <embedded>::cva5_formal_wrapper.u_cva5_fbm.u_ppb_axi.env_*
#assume -env {u_ppb_axi.axi_if.arvalid == 1'b0}
#assume -env {u_ppb_axi.axi_if.awvalid == 1'b0}

73
formal/scripts/taiga_rtl.vfile
View file

@ -1,73 +0,0 @@
+incdir+${JG_TAIGA_RTL_PATH}\
${JG_TAIGA_RTL_PATH}/core/taiga_config.sv \
${JG_TAIGA_RTL_PATH}/core/riscv_types.sv \
${JG_TAIGA_RTL_PATH}/core/taiga_types.sv \
${JG_TAIGA_RTL_PATH}/l2_arbiter/l2_config_and_types.sv \
${JG_TAIGA_RTL_PATH}/l2_arbiter/l2_interfaces.sv \
${JG_TAIGA_RTL_PATH}/l2_arbiter/l2_external_interfaces.sv \
${JG_TAIGA_RTL_PATH}/local_memory/local_memory_interface.sv \
${JG_TAIGA_RTL_PATH}/local_memory/local_mem.sv \
${JG_TAIGA_RTL_PATH}/core/interfaces.sv \
${JG_TAIGA_RTL_PATH}/core/external_interfaces.sv \
${JG_TAIGA_RTL_PATH}/core/csr_types.sv \
${JG_TAIGA_RTL_PATH}/core/csr_regs.sv \
${JG_TAIGA_RTL_PATH}/core/gc_unit.sv \
${JG_TAIGA_RTL_PATH}/core/branch_comparator.sv \
${JG_TAIGA_RTL_PATH}/core/branch_unit.sv \
${JG_TAIGA_RTL_PATH}/core/barrel_shifter.sv \
${JG_TAIGA_RTL_PATH}/core/alu_unit.sv \
${JG_TAIGA_RTL_PATH}/core/axi_master.sv \
${JG_TAIGA_RTL_PATH}/core/avalon_master.sv \
${JG_TAIGA_RTL_PATH}/core/wishbone_master.sv \
${JG_TAIGA_RTL_PATH}/core/axi_to_arb.sv \
${JG_TAIGA_RTL_PATH}/core/one_hot_occupancy.sv \
${JG_TAIGA_RTL_PATH}/core/binary_occupancy.sv \
${JG_TAIGA_RTL_PATH}/core/taiga_fifo.sv \
${JG_TAIGA_RTL_PATH}/core/shift_counter.sv \
${JG_TAIGA_RTL_PATH}/core/set_clr_reg_with_rst.sv \
${JG_TAIGA_RTL_PATH}/core/intel/intel_byte_enable_ram.sv \
${JG_TAIGA_RTL_PATH}/core/xilinx/xilinx_byte_enable_ram.sv \
${JG_TAIGA_RTL_PATH}/core/byte_en_BRAM.sv \
${JG_TAIGA_RTL_PATH}/core/one_hot_to_integer.sv \
${JG_TAIGA_RTL_PATH}/core/cycler.sv \
${JG_TAIGA_RTL_PATH}/core/tag_bank.sv \
${JG_TAIGA_RTL_PATH}/core/dbram.sv \
${JG_TAIGA_RTL_PATH}/core/ddata_bank.sv \
${JG_TAIGA_RTL_PATH}/core/dtag_banks.sv \
${JG_TAIGA_RTL_PATH}/core/amo_alu.sv \
${JG_TAIGA_RTL_PATH}/core/dcache.sv \
${JG_TAIGA_RTL_PATH}/core/addr_hash.sv \
${JG_TAIGA_RTL_PATH}/core/load_queue.sv \
${JG_TAIGA_RTL_PATH}/core/store_queue.sv \
${JG_TAIGA_RTL_PATH}/core/load_store_queue.sv \
${JG_TAIGA_RTL_PATH}/core/load_store_unit.sv \
${JG_TAIGA_RTL_PATH}/core/ibram.sv \
${JG_TAIGA_RTL_PATH}/core/itag_banks.sv \
${JG_TAIGA_RTL_PATH}/core/icache.sv \
${JG_TAIGA_RTL_PATH}/core/div_algorithms/div_radix2.sv \
${JG_TAIGA_RTL_PATH}/core/clz.sv \
${JG_TAIGA_RTL_PATH}/core/div_algorithms/div_quick_clz.sv \
${JG_TAIGA_RTL_PATH}/core/div_algorithms/div_algorithm.sv \
${JG_TAIGA_RTL_PATH}/core/div_unit.sv \
${JG_TAIGA_RTL_PATH}/core/lut_ram.sv \
${JG_TAIGA_RTL_PATH}/core/tlb_lut_ram.sv \
${JG_TAIGA_RTL_PATH}/core/mmu.sv \
${JG_TAIGA_RTL_PATH}/core/mul_unit.sv \
${JG_TAIGA_RTL_PATH}/core/l1_arbiter.sv \
${JG_TAIGA_RTL_PATH}/core/ras.sv \
${JG_TAIGA_RTL_PATH}/core/branch_predictor_ram.sv \
${JG_TAIGA_RTL_PATH}/core/branch_predictor.sv \
${JG_TAIGA_RTL_PATH}/core/fetch.sv \
${JG_TAIGA_RTL_PATH}/core/illegal_instruction_checker.sv \
${JG_TAIGA_RTL_PATH}/core/decode_and_issue.sv \
${JG_TAIGA_RTL_PATH}/core/regfile_bank_sel.sv \
${JG_TAIGA_RTL_PATH}/core/register_file.sv \
${JG_TAIGA_RTL_PATH}/core/register_file_and_writeback.sv \
${JG_TAIGA_RTL_PATH}/core/placer_randomizer.sv \
${JG_TAIGA_RTL_PATH}/l2_arbiter/l2_fifo.sv \
${JG_TAIGA_RTL_PATH}/l2_arbiter/l2_reservation_logic.sv \
${JG_TAIGA_RTL_PATH}/l2_arbiter/l2_round_robin.sv \
${JG_TAIGA_RTL_PATH}/l2_arbiter/l2_arbiter.sv \
${JG_TAIGA_RTL_PATH}/core/toggle_memory.sv \
${JG_TAIGA_RTL_PATH}/core/instruction_metadata_and_id_management.sv \
${JG_TAIGA_RTL_PATH}/core/taiga.sv \

18
l2_arbiter/l2_arbiter.sv
View file

@ -24,7 +24,7 @@ module l2_arbiter
import l2_config_and_types::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
(
input logic clk,
@ -105,7 +105,7 @@ module l2_arbiter
assign request[i].request_full = input_fifos[i].full;
//FIFO instantiation
taiga_fifo #(.DATA_WIDTH($bits(l2_request_t)), .FIFO_DEPTH(L2_INPUT_FIFO_DEPTHS)) input_fifo (.*, .fifo(input_fifos[i]));
cva5_fifo #(.DATA_WIDTH($bits(l2_request_t)), .FIFO_DEPTH(L2_INPUT_FIFO_DEPTHS)) input_fifo (.*, .fifo(input_fifos[i]));
//Arbiter FIFO side
assign requests[i] = input_fifos[i].data_out;
@ -126,7 +126,7 @@ module l2_arbiter
assign request[i].data_full = input_data_fifos[i].full;
//FIFO instantiation
taiga_fifo #(.DATA_WIDTH(32), .FIFO_DEPTH(L2_INPUT_FIFO_DEPTHS)) input_data_fifo (.*, .fifo(input_data_fifos[i]));
cva5_fifo #(.DATA_WIDTH(32), .FIFO_DEPTH(L2_INPUT_FIFO_DEPTHS)) input_data_fifo (.*, .fifo(input_data_fifos[i]));
//Arbiter FIFO side
assign input_data_fifos[i].pop = (data_attributes.valid && (current_attr.id == i) && ~mem_data_fifo.full);
@ -169,7 +169,7 @@ module l2_arbiter
assign mem.amo_type_or_burst_size = mem_addr_fifo_data_out.amo_type_or_burst_size;
assign mem.id = mem_addr_fifo_data_out.id;
taiga_fifo #(.DATA_WIDTH($bits(l2_mem_request_t)), .FIFO_DEPTH(L2_MEM_ADDR_FIFO_DEPTH)) input_fifo (.*, .fifo(mem_addr_fifo));
cva5_fifo #(.DATA_WIDTH($bits(l2_mem_request_t)), .FIFO_DEPTH(L2_MEM_ADDR_FIFO_DEPTH)) input_fifo (.*, .fifo(mem_addr_fifo));
/*************************************
@ -226,7 +226,7 @@ module l2_arbiter
assign request[i].inv_valid = inv_response_fifos[i].valid;
//FIFO instantiation
taiga_fifo #(.DATA_WIDTH(30), .FIFO_DEPTH(L2_INVALIDATION_FIFO_DEPTHS)) inv_response_fifo (.*, .fifo(inv_response_fifos[i]));
cva5_fifo #(.DATA_WIDTH(30), .FIFO_DEPTH(L2_INVALIDATION_FIFO_DEPTHS)) inv_response_fifo (.*, .fifo(inv_response_fifos[i]));
//Arbiter side
assign inv_response_fifos[i].push = reserv_valid & reserv_store & ~reserv_id_v[i];
assign inv_response_fifos[i].potential_push = reserv_valid & reserv_store & ~reserv_id_v[i];
@ -245,7 +245,7 @@ module l2_arbiter
assign data_attributes.push = reserv_valid & ~reserv_request.rnw & ~mem.abort;
assign data_attributes.potential_push = reserv_valid & ~reserv_request.rnw & ~mem.abort;
taiga_fifo #(.DATA_WIDTH($bits(l2_data_attributes_t)), .FIFO_DEPTH(L2_DATA_ATTRIBUTES_FIFO_DEPTH)) data_attributes_fifo (.*, .fifo(data_attributes));
cva5_fifo #(.DATA_WIDTH($bits(l2_data_attributes_t)), .FIFO_DEPTH(L2_DATA_ATTRIBUTES_FIFO_DEPTH)) data_attributes_fifo (.*, .fifo(data_attributes));
assign data_attributes.pop = write_done;
assign current_attr = data_attributes.data_out;
@ -261,7 +261,7 @@ module l2_arbiter
assign write_done = data_attributes.valid & ~mem_data_fifo.full & (burst_count == current_attr.burst_size);
taiga_fifo #(.DATA_WIDTH($bits(32)), .FIFO_DEPTH(L2_MEM_ADDR_FIFO_DEPTH)) mem_data (.*, .fifo(mem_data_fifo));
cva5_fifo #(.DATA_WIDTH($bits(32)), .FIFO_DEPTH(L2_MEM_ADDR_FIFO_DEPTH)) mem_data (.*, .fifo(mem_data_fifo));
assign mem_data_fifo.push = data_attributes.valid & ~mem_data_fifo.full & ~current_attr.abort;
assign mem_data_fifo.potential_push = data_attributes.valid & ~mem_data_fifo.full & ~current_attr.abort;
@ -276,7 +276,7 @@ module l2_arbiter
/*************************************
* Read response
*************************************/
taiga_fifo # (.DATA_WIDTH(32 + L2_ID_W), .FIFO_DEPTH(L2_MEM_ADDR_FIFO_DEPTH)) mem_returndata (.*, .fifo(mem_returndata_fifo));
cva5_fifo # (.DATA_WIDTH(32 + L2_ID_W), .FIFO_DEPTH(L2_MEM_ADDR_FIFO_DEPTH)) mem_returndata (.*, .fifo(mem_returndata_fifo));
assign mem_returndata_fifo.push = mem.rd_data_valid;
assign mem_returndata_fifo.potential_push = mem.rd_data_valid;
@ -298,7 +298,7 @@ module l2_arbiter
assign request[i].rd_data_valid = returndata_fifos[i].valid;
//FIFO instantiation
taiga_fifo #(.DATA_WIDTH(32 + L2_SUB_ID_W), .FIFO_DEPTH(L2_READ_RETURN_FIFO_DEPTHS)) returndata_fifo (.*, .fifo(returndata_fifos[i]));
cva5_fifo #(.DATA_WIDTH(32 + L2_SUB_ID_W), .FIFO_DEPTH(L2_READ_RETURN_FIFO_DEPTHS)) returndata_fifo (.*, .fifo(returndata_fifos[i]));
//Arbiter side
assign returndata_fifos[i].push = return_push[i];
assign returndata_fifos[i].potential_push = return_push[i];

4
l2_arbiter/l2_external_interfaces.sv
View file

@ -64,12 +64,14 @@ interface l2_requester_interface;
input wr_data, wr_data_push, output data_full,
output rd_data, rd_sub_id, rd_data_valid, input rd_data_ack);
`ifdef __CVA5_FORMAL__
modport formal (input addr, be, rnw, is_amo, amo_type_or_burst_size, sub_id,
request_push, output request_full,
inv_addr, inv_valid, input inv_ack,
con_result, con_valid,
wr_data, wr_data_push, output data_full,
rd_data, rd_sub_id, rd_data_valid, input rd_data_ack);
`endif
endinterface
@ -108,10 +110,12 @@ interface l2_memory_interface;
input wr_data, wr_data_valid, output wr_data_read,
output rd_data, rd_id, rd_data_valid);
`ifdef __CVA5_FORMAL__
modport formal (input addr, be, rnw, is_amo, amo_type_or_burst_size, id,
request_valid, abort, output request_pop,
wr_data, wr_data_valid, output wr_data_read,
rd_data, rd_id, rd_data_valid);
`endif
endinterface

4
local_memory/local_memory_interface.sv
View file

@ -30,7 +30,11 @@ interface local_memory_interface;
modport slave (input addr, en, be, data_in, output data_out);
modport master (output addr, en, be, data_in, input data_out);
`ifdef __CVA5_FORMAL__
modport formal (input addr, en, be, data_in, data_out);
`endif
endinterface

29
scripts/xilinx/taiga_wrapper_IP.tcl → scripts/xilinx/cva5_wrapper_IP.tcl
View file

@ -27,7 +27,7 @@ if { [info exists ::origin_dir_loc] } {
}
# Set the project name
set _xil_proj_name_ "taiga_wrapper_IP"
set _xil_proj_name_ "cva5_wrapper_IP"
# Use project name variable, if specified in the tcl shell
if { [info exists ::user_project_name] } {
@ -35,7 +35,7 @@ if { [info exists ::user_project_name] } {
}
variable script_file
set script_file "taiga_wrapper_IP.tcl"
set script_file "cva5_wrapper_IP.tcl"
# Help information for this script
proc print_help {} {
@ -97,7 +97,7 @@ set proj_dir [get_property directory [current_project]]
# Set project properties
set obj [current_project]
set_property -name "board_part" -value "em.avnet.com:zed:part0:1.4" -objects $obj
set_property -name "board_part" -value "digilentinc.com:zedboard:part0:1.0" -objects $obj
set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
set_property -name "ip_cache_permissions" -value "read write" -objects $obj
set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
@ -110,23 +110,26 @@ if {[string equal [get_filesets -quiet sources_1] ""]} {
create_fileset -srcset sources_1
}
#import all sources from taiga repo directory
#import all sources from cva5 repo directory
#Zavier: Eric says we only want the wrapper, and whatever type/interface file we need at first.
#The reasoning is: less files ati ntial package, less worry
#The reasoning is: less files at initial package, less worry
#import_files -fileset [get_filesets sources_1] $origin_dir/core
#import_files -fileset [get_filesets sources_1] $origin_dir/l2_arbiter
#import_files -fileset [get_filesets sources_1] $origin_dir/local_memory
import_files -norecurse $origin_dir/../../core/xilinx/taiga_wrapper_xilinx.sv -force
import_files -norecurse $origin_dir/../../core/xilinx/cva5_wrapper_xilinx.sv -force
import_files -norecurse $origin_dir/../../l2_arbiter/l2_external_interfaces.sv -force
import_files -norecurse $origin_dir/../../local_memory/local_memory_interface.sv -force
import_files -norecurse $origin_dir/../../core/external_interfaces.sv -force
import_files -norecurse $origin_dir/../../core/taiga_config.sv -force
import_files -norecurse $origin_dir/../../core/cva5_config.sv -force
import_files -norecurse $origin_dir/../../core/riscv_types.sv -force
import_files -norecurse $origin_dir/../../core/cva5_types.sv -force
import_files -norecurse $origin_dir/../../core/csr_types.sv -force
import_files -norecurse $origin_dir/../../l2_arbiter/l2_config_and_types.sv -force
# Set IP repository paths
set obj [get_filesets sources_1]
set_property "ip_repo_paths" "[file normalize "$origin_dir/taiga_wrapper_IP"]" $obj
set_property "ip_repo_paths" "[file normalize "$origin_dir/cva5_wrapper_IP"]" $obj
# Rebuild user ip_repo's index before adding any source files
update_ip_catalog -rebuild
@ -142,12 +145,12 @@ update_ip_catalog -rebuild
# Set 'sources_1' fileset properties
set obj [get_filesets sources_1]
set_property -name "top" -value "taiga_wrapper_xilinx" -objects $obj
set_property -name "top" -value "cva5_wrapper_xilinx" -objects $obj
set_property -name "top_auto_set" -value "0" -objects $obj
set_property -name "top_file" -value " ${origin_dir}/core/taiga_wrapper_xilinx.sv" -objects $obj
set_property -name "top_file" -value " ${origin_dir}/core/cva5_wrapper_xilinx.sv" -objects $obj
# Remove interface files for taiga
# Remove interface files for cva5
puts "INFO: Project created:${_xil_proj_name_}"
#Removal of SystemVerilog interface files, so initial IP packaging can be done
@ -257,7 +260,7 @@ set_property core_revision 3 [ipx::current_core]
ipx::create_xgui_files [ipx::current_core]
ipx::update_checksums [ipx::current_core]
ipx::save_core [ipx::current_core]
current_project taiga_wrapper_IP
set_property "ip_repo_paths" "[file normalize "$origin_dir/taiga_wrapper_IP"]" $obj
current_project cva5_wrapper_IP
set_property "ip_repo_paths" "[file normalize "$origin_dir/cva5_wrapper_IP"]" $obj
update_ip_catalog -rebuild

13
scripts/xilinx/local_memory_IP.tcl
View file

@ -96,7 +96,7 @@ set proj_dir [get_property directory [current_project]]
# Set project properties
set obj [current_project]
set_property -name "board_part" -value "em.avnet.com:zed:part0:1.4" -objects $obj
set_property -name "board_part" -value "digilentinc.com:zedboard:part0:1.0" -objects $obj
set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
set_property -name "ip_cache_permissions" -value "read write" -objects $obj
set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
@ -109,17 +109,18 @@ if {[string equal [get_filesets -quiet sources_1] ""]} {
create_fileset -srcset sources_1
}
#import all sources from taiga repo directory
#import all sources from cva5 repo directory
import_files -fileset [get_filesets sources_1] $origin_dir/../../local_memory
import_files -norecurse $origin_dir/../../core/byte_en_BRAM.sv -force
import_files -norecurse $origin_dir/../../core/xilinx/xilinx_byte_enable_ram.sv -force
import_files -norecurse $origin_dir/../../core/taiga_config.sv -force
import_files -norecurse $origin_dir/../../core/taiga_types.sv -force
import_files -norecurse $origin_dir/../../core/cva5_config.sv -force
import_files -norecurse $origin_dir/../../core/cva5_types.sv -force
import_files -norecurse $origin_dir/../../core/riscv_types.sv -force
import_files -norecurse $origin_dir/../../core/csr_types.sv -force
# Set IP repository paths
#set obj [get_filesets sources_1]
#set_property "ip_repo_paths" "[file normalize "$origin_dir/Clean_Taiga_IP"]" $obj
#set_property "ip_repo_paths" "[file normalize "$origin_dir/Clean_CVA5_IP"]" $obj
# Rebuild user ip_repo's index before adding any source files
update_ip_catalog -rebuild
@ -138,7 +139,7 @@ set_property -name "top_auto_set" -value "0" -objects $obj
set_property -name "top_file" -value "${origin_dir}/local_memory/local_mem.sv" -objects $obj
# Remove interface files for taiga
# Remove interface files for cva5
puts "INFO: Project created:${_xil_proj_name_}"
##############IP Packaging########################################

2
test_benches/axi_mem_sim.sv
View file

@ -22,7 +22,7 @@
//No error checking for incorrect ordering of axi control signals from Master side of interface
import tb_tools::*;
import taiga_config::*;
import cva5_config::*;
module axi_mem_sim
#(parameter string file_name = "")

8
test_benches/taiga_tb.sv → test_benches/cva5_tb.sv
View file

@ -25,13 +25,13 @@
`define MEMORY_FILE "/home/ematthew/Research/RISCV/software/riscv-tools/riscv-tests/benchmarks/dhrystone.riscv.sim_init"
`define UART_LOG "/home/ematthew/uart.log"
module taiga_tb
module cva5_tb
import tb_tools::*;
import taiga_config::*;
import cva5_config::*;
import l2_config_and_types::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
( );
@ -216,7 +216,7 @@ module taiga_tb
end
end
taiga uut (.*, .l2(l2[0]));
cva5 uut (.*, .l2(l2[0]));
design_2 infra(.*);

448
test_benches/taiga_tb.wcfg → test_benches/cva5_tb.wcfg
View file

File diff suppressed because it is too large Load diff

4
test_benches/unit_test_benches/alu_unit_tb.sv
View file

@ -23,8 +23,8 @@
`timescale 1ns / 1ps
import taiga_config::*;
import taiga_types::*;
import cva5_config::*;
import cva5_types::*;
typedef struct packed{
alu_inputs_t module_input;

4
test_benches/unit_test_benches/div_unit_tb.sv
View file

@ -23,8 +23,8 @@
`timescale 1ns / 1ps
import taiga_config::*;
import taiga_types::*;
import cva5_config::*;
import cva5_types::*;
typedef struct packed{
div_inputs_t module_input;

4
test_benches/unit_test_benches/mul_unit_tb.sv
View file

@ -23,8 +23,8 @@
`timescale 1ns / 1ps
import taiga_config::*;
import taiga_types::*;
import cva5_config::*;
import cva5_types::*;
typedef struct packed{
mul_inputs_t module_input;

8
test_benches/verilator/AXI_DDR_simulation/axi_ddr_sim.cc
View file

@ -4,13 +4,13 @@
#include <assert.h>
#include "verilated.h"
#include "verilated_vcd_c.h"
#include "Vtaiga_sim.h"
#include "Vcva5_sim.h"
#include "axi_ddr_sim.h"
#include "ddr_page.h"
using namespace std;
axi_ddr_sim::axi_ddr_sim(Vtaiga_sim * tb){
axi_ddr_sim::axi_ddr_sim(Vcva5_sim * tb){
this->tb = tb;
}
@ -26,7 +26,7 @@ void axi_ddr_sim::init_signals(){
}
axi_ddr_sim::axi_ddr_sim(string filepath, uint32_t starting_memory_location, int number_of_bytes, Vtaiga_sim * tb){
axi_ddr_sim::axi_ddr_sim(string filepath, uint32_t starting_memory_location, int number_of_bytes, Vcva5_sim * tb){
ifstream input_memory_file;
input_memory_file.open(filepath);
string line;
@ -55,7 +55,7 @@ axi_ddr_sim::axi_ddr_sim(string filepath, uint32_t starting_memory_location, int
axi_ddr_sim::axi_ddr_sim(ifstream & input_memory_file, Vtaiga_sim * tb){
axi_ddr_sim::axi_ddr_sim(ifstream & input_memory_file, Vcva5_sim * tb){
string line;
uint32_t max_pages = DDR_SIZE/PAGE_SIZE;

10
test_benches/verilator/AXI_DDR_simulation/axi_ddr_sim.h
View file

@ -32,7 +32,7 @@
#include <random>
#include "verilated.h"
#include "verilated_vcd_c.h"
#include "Vtaiga_sim.h"
#include "Vcva5_sim.h"
#include "axi_interface.h"
#include "ddr_page.h"
@ -55,11 +55,11 @@ struct addr_calculation_parameters{
//Init instructions-----------------
axi_ddr_sim();
//Initialize DDR
axi_ddr_sim(Vtaiga_sim * tb);
axi_ddr_sim(Vcva5_sim * tb);
//Initialize DDR from file
axi_ddr_sim(string filepath, uint32_t starting_memory_location, int number_of_bytes, Vtaiga_sim * tb);
axi_ddr_sim(ifstream & input_memory_file, Vtaiga_sim * tb);
axi_ddr_sim(string filepath, uint32_t starting_memory_location, int number_of_bytes, Vcva5_sim * tb);
axi_ddr_sim(ifstream & input_memory_file, Vcva5_sim * tb);
void step();
int get_data(uint32_t data_address);
@ -83,7 +83,7 @@ struct addr_calculation_parameters{
uniform_int_distribution<int> write_distribution;
//Pointers to Data
map<uint32_t,ddr_page> ddr_pages;
Vtaiga_sim *tb;
Vcva5_sim *tb;
void parse_output_signals();
void parse_input_signals();

14
test_benches/verilator/AXI_DDR_simulation/axi_l2_test.sv
View file

@ -20,8 +20,8 @@
* Eric Matthews <ematthew@sfu.ca>
*/
import taiga_config::*;
import taiga_types::*;
import cva5_config::*;
import cva5_types::*;
import l2_config_and_types::*;
@ -121,7 +121,7 @@ module axi_l2_test # (
//Trace Interface
output logic instruction_issued,
output logic taiga_events [0:$bits(taiga_trace_events_t)-1],
output logic cva5_events [0:$bits(cva5_trace_events_t)-1],
output logic [31:0] instruction_pc_dec,
output logic [31:0] instruction_data_dec
);
@ -301,11 +301,11 @@ module axi_l2_test # (
assign instruction_pc_dec = tr.instruction_pc_dec;
assign instruction_data_dec = tr.instruction_data_dec;
assign instruction_issued = tr.events.instruction_issued_dec;
logic [$bits(taiga_trace_events_t)-1:0] taiga_events_packed;
assign taiga_events_packed = tr.events;
logic [$bits(cva5_trace_events_t)-1:0] cva5_events_packed;
assign cva5_events_packed = tr.events;
always_comb begin
foreach(taiga_events_packed[i])
taiga_events[$bits(taiga_trace_events_t)-1-i] = taiga_events_packed[i];
foreach(cva5_events_packed[i])
cva5_events[$bits(cva5_trace_events_t)-1-i] = cva5_events_packed[i];
end
endmodule

40
test_benches/verilator/TaigaTracer.cc → test_benches/verilator/CVA5Tracer.cc
View file

@ -21,11 +21,11 @@
*/
#include <iostream>
#include "TaigaTracer.h"
#include "CVA5Tracer.h"
//#define TRACE_ON
bool TaigaTracer::check_if_instruction_retired(uint32_t instruction) {
bool CVA5Tracer::check_if_instruction_retired(uint32_t instruction) {
bool result = false;
for (int i =0; i < tb->NUM_RETIRE_PORTS; i++) {
result |= (tb->retire_ports_instruction[i] == instruction) && tb->retire_ports_valid[i];
@ -34,7 +34,7 @@ bool TaigaTracer::check_if_instruction_retired(uint32_t instruction) {
}
bool TaigaTracer::has_terminated() {
bool CVA5Tracer::has_terminated() {
if (check_if_instruction_retired(ERROR_TERMINATION_NOP)) {
std::cout << "\n\nError!!!!\n\n";
@ -50,7 +50,7 @@ bool TaigaTracer::has_terminated() {
}
bool TaigaTracer::has_stalled() {
bool CVA5Tracer::has_stalled() {
if (!tb->instruction_issued) {
if (stall_count > stall_limit) {
stall_count = 0;
@ -66,26 +66,26 @@ bool TaigaTracer::has_stalled() {
return false;
}
bool TaigaTracer::store_queue_empty() {
bool CVA5Tracer::store_queue_empty() {
return tb->store_queue_empty;
}
void TaigaTracer::reset_stats() {
void CVA5Tracer::reset_stats() {
for (int i=0; i < numEvents; i++)
event_counters[i] = 0;
}
void TaigaTracer::update_stats() {
void CVA5Tracer::update_stats() {
if (collect_stats) {
for (int i=0; i < numEvents; i++)
event_counters[i] += tb->taiga_events[i];
event_counters[i] += tb->cva5_events[i];
}
}
void TaigaTracer::print_stats() {
std::cout << " Taiga trace stats\n";
void CVA5Tracer::print_stats() {
std::cout << " CVA5 trace stats\n";
std::cout << "--------------------------------------------------------------\n";
for (int i=0; i < numEvents; i++)
std::cout << " " << eventNames[i] << ":" << event_counters[i] << std::endl;
@ -95,7 +95,7 @@ void TaigaTracer::print_stats() {
void TaigaTracer::reset() {
void CVA5Tracer::reset() {
tb->clk = 0;
tb->rst = 1;
for (int i=0; i <reset_length; i++){
@ -109,12 +109,12 @@ void TaigaTracer::reset() {
}
void TaigaTracer::set_log_file(std::ofstream* logFile) {
void CVA5Tracer::set_log_file(std::ofstream* logFile) {
this->logFile = logFile;
}
void TaigaTracer::update_UART() {
void CVA5Tracer::update_UART() {
if (tb->write_uart) {
std::cout << tb->uart_byte << std::flush;
*logFile << tb->uart_byte;
@ -122,7 +122,7 @@ void TaigaTracer::update_UART() {
}
void TaigaTracer::update_memory() {
void CVA5Tracer::update_memory() {
tb->instruction_bram_data_out = instruction_r;
if (tb->instruction_bram_en)
instruction_r = mem->read(tb->instruction_bram_addr);
@ -135,7 +135,7 @@ void TaigaTracer::update_memory() {
}
void TaigaTracer::tick() {
void CVA5Tracer::tick() {
cycle_count++;
tb->clk = 1;
@ -173,7 +173,7 @@ void TaigaTracer::tick() {
}
void TaigaTracer::start_tracer(const char *trace_file) {
void CVA5Tracer::start_tracer(const char *trace_file) {
#ifdef TRACE_ON
verilatorWaveformTracer = new VerilatedVcdC;
tb->trace(verilatorWaveformTracer, 99);
@ -183,18 +183,18 @@ void TaigaTracer::start_tracer(const char *trace_file) {
uint64_t TaigaTracer::get_cycle_count() {
uint64_t CVA5Tracer::get_cycle_count() {
return cycle_count;
}
TaigaTracer::TaigaTracer(std::ifstream& programFile) {
CVA5Tracer::CVA5Tracer(std::ifstream& programFile) {
#ifdef TRACE_ON
Verilated::traceEverOn(true);
#endif
tb = new Vtaiga_sim;
tb = new Vcva5_sim;
#ifdef DDR_LOAD_FILE
axi_ddr = new axi_ddr_sim(DDR_INIT_FILE,DDR_FILE_STARTING_LOCATION,DDR_FILE_NUM_BYTES);
@ -211,7 +211,7 @@ TaigaTracer::TaigaTracer(std::ifstream& programFile) {
}
TaigaTracer::~TaigaTracer() {
CVA5Tracer::~CVA5Tracer() {
#ifdef TRACE_ON
verilatorWaveformTracer->flush();
verilatorWaveformTracer->close();

16
test_benches/verilator/TaigaTracer.h → test_benches/verilator/CVA5Tracer.h
View file

@ -20,14 +20,14 @@
* Eric Matthews <ematthew@sfu.ca>
*/
#ifndef TaigaTracer_H
#define TaigaTracer_H
#ifndef CVA5Tracer_H
#define CVA5Tracer_H
#include <stdlib.h>
#include <iostream>
#include <iterator>
#include "verilated.h"
#include "verilated_vcd_c.h"
#include "Vtaiga_sim.h"
#include "Vcva5_sim.h"
#include "SimMem.h"
#include "AXI_DDR_simulation/axi_ddr_sim.h"
//#define TRACE_ON
@ -72,11 +72,11 @@ static const char * const eventNames[] = {
};
static const int numEvents = arraySize(eventNames);
//Testbench with Taiga trace outputs on toplevel
class TaigaTracer {
//Testbench with CVA5 trace outputs on toplevel
class CVA5Tracer {
public:
TaigaTracer(std::ifstream& programFile);
~TaigaTracer();
CVA5Tracer(std::ifstream& programFile);
~CVA5Tracer();
bool check_if_instruction_retired(uint32_t instruction);
bool has_terminated();
bool has_stalled();
@ -91,7 +91,7 @@ public:
uint64_t get_cycle_count();
//DDR Simulation
Vtaiga_sim *tb;
Vcva5_sim *tb;
private:
axi_ddr_sim * axi_ddr;
SimMem *mem;

32
test_benches/verilator/taiga_sim.cc → test_benches/verilator/cva5_sim.cc
View file

@ -3,14 +3,14 @@
#include <fstream>
#include "verilated.h"
#include "verilated_vcd_c.h"
#include "Vtaiga_sim.h"
#include "TaigaTracer.h"
#include "Vcva5_sim.h"
#include "CVA5Tracer.h"
TaigaTracer *taigaTracer;
CVA5Tracer *cva5Tracer;
//For time index on assertions
double sc_time_stamp () {
return taigaTracer->get_cycle_count();
return cva5Tracer->get_cycle_count();
}
//#define TRACE_ON
@ -61,12 +61,12 @@ int main(int argc, char **argv) {
}
// Create an instance of our module under test
taigaTracer = new TaigaTracer(programFile);
taigaTracer->set_log_file(&logFile);
cva5Tracer = new CVA5Tracer(programFile);
cva5Tracer->set_log_file(&logFile);
#ifdef TRACE_ON
taigaTracer->start_tracer(argv[4]);
cva5Tracer->start_tracer(argv[4]);
#endif
taigaTracer->reset();
cva5Tracer->reset();
cout << "--------------------------------------------------------------\n";
cout << " Starting Simulation, logging to " << argv[1] << "\n";
cout << "--------------------------------------------------------------\n";
@ -74,27 +74,27 @@ int main(int argc, char **argv) {
// Tick the clock until we are done
bool sig_phase_complete = false;
while(!(taigaTracer->has_stalled() || taigaTracer->has_terminated())) {
taigaTracer->tick();
while(!(cva5Tracer->has_stalled() || cva5Tracer->has_terminated())) {
cva5Tracer->tick();
//Compliance Tests Signature Printing Phase
sig_phase_complete |= taigaTracer->check_if_instruction_retired(COMPLIANCE_SIG_PHASE_NOP);
if (sig_phase_complete && taigaTracer->store_queue_empty()) {
sig_phase_complete |= cva5Tracer->check_if_instruction_retired(COMPLIANCE_SIG_PHASE_NOP);
if (sig_phase_complete && cva5Tracer->store_queue_empty()) {
std::cout << "\n--------------------------------------------------------------\n";
std::cout << " Signature\n";
std::cout << "--------------------------------------------------------------\n";
taigaTracer->set_log_file(&sigFile);
cva5Tracer->set_log_file(&sigFile);
}
}
cout << "--------------------------------------------------------------\n";
cout << " Simulation Completed " << taigaTracer->get_cycle_count() << " cycles.\n";
taigaTracer->print_stats();
cout << " Simulation Completed " << cva5Tracer->get_cycle_count() << " cycles.\n";
cva5Tracer->print_stats();
logFile.close();
sigFile.close();
programFile.close();
delete taigaTracer;
delete cva5Tracer;
exit(EXIT_SUCCESS);
}

18
test_benches/verilator/taiga_sim.sv → test_benches/verilator/cva5_sim.sv
View file

@ -20,12 +20,12 @@
* Eric Matthews <ematthew@sfu.ca>
*/
module taiga_sim
module cva5_sim
import taiga_config::*;
import cva5_config::*;
import l2_config_and_types::*;
import riscv_types::*;
import taiga_types::*;
import cva5_types::*;
# (
parameter MEMORY_FILE = "/home/ematthew/Research/RISCV/software/riscv-tools/riscv-tests/benchmarks/dhrystone.riscv.hw_init" //change this to appropriate location "/home/ematthew/Downloads/dhrystone.riscv.sim_init"
@ -171,7 +171,7 @@ module taiga_sim
output logic load_store_idle,
output logic instruction_issued,
output logic taiga_events [0:$bits(taiga_trace_events_t)-1],
output logic cva5_events [0:$bits(cva5_trace_events_t)-1],
output logic [31:0] instruction_pc_dec,
output logic [31:0] instruction_data_dec
);
@ -294,7 +294,7 @@ module taiga_sim
assign data_bram_data_in = data_bram.data_in;
assign data_bram.data_out = data_bram_data_out;
taiga #(.CONFIG(EXAMPLE_CONFIG)) cpu(.*, .l2(l2[0]));
cva5 #(.CONFIG(EXAMPLE_CONFIG)) cpu(.*, .l2(l2[0]));
//read channel
logic[3:0] read_counter;
@ -434,11 +434,11 @@ module taiga_sim
assign instruction_pc_dec = tr.instruction_pc_dec;
assign instruction_data_dec = tr.instruction_data_dec;
assign instruction_issued = tr.events.instruction_issued_dec;
logic [$bits(taiga_trace_events_t)-1:0] taiga_events_packed;
assign taiga_events_packed = tr.events;
logic [$bits(cva5_trace_events_t)-1:0] cva5_events_packed;
assign cva5_events_packed = tr.events;
always_comb begin
foreach(taiga_events_packed[i])
taiga_events[$bits(taiga_trace_events_t)-1-i] = taiga_events_packed[i];
foreach(cva5_events_packed[i])
cva5_events[$bits(cva5_trace_events_t)-1-i] = cva5_events_packed[i];
end
////////////////////////////////////////////////////

8
tools/taiga_compile_order → tools/compile_order
View file

@ -1,7 +1,7 @@
core/taiga_config.sv
core/cva5_config.sv
core/riscv_types.sv
core/csr_types.sv
core/taiga_types.sv
core/cva5_types.sv
l2_arbiter/l2_config_and_types.sv
l2_arbiter/l2_interfaces.sv
l2_arbiter/l2_external_interfaces.sv
@ -33,7 +33,7 @@ core/axi_to_arb.sv
core/one_hot_occupancy.sv
core/binary_occupancy.sv
core/taiga_fifo.sv
core/cva5_fifo.sv
core/shift_counter.sv
core/priority_encoder.sv
@ -108,5 +108,5 @@ core/toggle_memory.sv
core/toggle_memory_set.sv
core/instruction_metadata_and_id_management.sv
core/taiga.sv
core/cva5.sv

48
tools/taiga.mak → tools/cva5.mak
View file

@ -1,10 +1,10 @@
###############################################################
VERILATOR_DIR=$(TAIGA_DIR)/test_benches/verilator
VERILATOR_DIR=$(CVA5_DIR)/test_benches/verilator
# Sources for verilator
TAIGA_HW_SRCS = $(addprefix $(TAIGA_DIR)/, $(shell cat $(TAIGA_DIR)/tools/taiga_compile_order))
TAIGA_SIM_SRCS = $(addprefix $(VERILATOR_DIR)/, TaigaTracer.cc SimMem.cc taiga_sim.cc AXI_DDR_simulation/axi_ddr_sim.cc AXI_DDR_simulation/ddr_page.cc)
TAIGA_INCLUDED_SIM_SRCS = $(addprefix $(VERILATOR_DIR)/, taiga_sim.cc AXI_DDR_simulation/ddr_page.cc SimMem.cc)
CVA5_HW_SRCS = $(addprefix $(CVA5_DIR)/, $(shell cat $(CVA5_DIR)/tools/compile_order))
CVA5_SIM_SRCS = $(addprefix $(VERILATOR_DIR)/, CVA5Tracer.cc SimMem.cc cva5_sim.cc AXI_DDR_simulation/axi_ddr_sim.cc AXI_DDR_simulation/ddr_page.cc)
CVA5_INCLUDED_SIM_SRCS = $(addprefix $(VERILATOR_DIR)/, cva5_sim.cc AXI_DDR_simulation/ddr_page.cc SimMem.cc)
#Tracing: Set to True or False
@ -12,8 +12,8 @@ TRACE_ENABLE?=False
#Simulation Binary Name
TAIGA_SIM_DIR?=$(VERILATOR_DIR)/build
TAIGA_SIM?=$(TAIGA_SIM_DIR)/taiga-sim
CVA5_SIM_DIR?=$(VERILATOR_DIR)/build
CVA5_SIM?=$(CVA5_SIM_DIR)/cva5-sim
#(to-do)DDR Pre-Initialization
#LOAD_DDR_FROM_FILE = False
@ -69,32 +69,32 @@ VERILATOR_LINT_IGNORE= -Wno-LITENDIAN -Wno-SYMRSVDWORD
##################################################################################
#taiga_sim included as linter requires top-level to have no interfaces
#cva5_sim included as linter requires top-level to have no interfaces
.PHONY: lint
lint:
verilator -cc $(TAIGA_HW_SRCS) \
$(VERILATOR_DIR)/taiga_sim.sv \
--top-module taiga_sim \
verilator -cc $(CVA5_HW_SRCS) \
$(VERILATOR_DIR)/cva5_sim.sv \
--top-module cva5_sim \
--lint-only
.PHONY: lint-full
lint-full:
verilator -cc $(TAIGA_HW_SRCS) \
$(VERILATOR_DIR)/taiga_sim.sv \
--top-module taiga_sim \
verilator -cc $(CVA5_HW_SRCS) \
$(VERILATOR_DIR)/cva5_sim.sv \
--top-module cva5_sim \
--lint-only -Wall
#Build Taiga Sim
$(TAIGA_SIM): $(TAIGA_HW_SRCS) $(TAIGA_SIM_SRCS)
mkdir -p $(TAIGA_SIM_DIR)
verilator --cc --exe --Mdir $(TAIGA_SIM_DIR) -DENABLE_SIMULATION_ASSERTIONS --assert \
-o taiga-sim \
#Build CVA5 Sim
$(CVA5_SIM): $(CVA5_HW_SRCS) $(CVA5_SIM_SRCS)
mkdir -p $(CVA5_SIM_DIR)
verilator --cc --exe --Mdir $(CVA5_SIM_DIR) -DENABLE_SIMULATION_ASSERTIONS --assert \
-o cva5-sim \
$(VERILATOR_LINT_IGNORE) $(VERILATOR_CFLAGS) \
$(TAIGA_SIM_SRCS) \
$(TAIGA_HW_SRCS) $(VERILATOR_DIR)/taiga_sim.sv --top-module taiga_sim
$(MAKE) -C $(TAIGA_SIM_DIR) -f Vtaiga_sim.mk
$(CVA5_SIM_SRCS) \
$(CVA5_HW_SRCS) $(VERILATOR_DIR)/cva5_sim.sv --top-module cva5_sim
$(MAKE) -C $(CVA5_SIM_DIR) -f Vcva5_sim.mk
.PHONY: clean-taiga-sim
clean-taiga-sim:
rm -rf $(TAIGA_SIM_DIR)
.PHONY: clean-cva5-sim
clean-cva5-sim:
rm -rf $(CVA5_SIM_DIR)

0
tools/taiga_binary_converter.py → tools/elf-to-hw-init.py
View file