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dcache cleanups
This commit is contained in:
Eric Matthews
parent
9903073465
commit
162c360a66
2 changed files with 77 additions and 84 deletions
118
core/dcache.sv
118
core/dcache.sv
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@ -40,6 +40,11 @@ module dcache(
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ls_sub_unit_interface.sub_unit ls
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);
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localparam DCACHE_SIZE_IN_WORDS = DCACHE_LINES*DCACHE_LINE_W*DCACHE_WAYS;
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logic [$clog2(DCACHE_SIZE_IN_WORDS)-1:0] data_bank_addr_a;
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logic [$clog2(DCACHE_SIZE_IN_WORDS)-1:0] data_bank_addr_b;
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logic tag_hit;
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logic [DCACHE_WAYS-1:0] tag_hit_way;
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@ -94,12 +99,11 @@ module dcache(
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logic store_complete;
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amo_alu_inputs_t amo_alu_inputs;
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////////////////////////////////////////////////////
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//Implementation
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const bit[DCACHE_SUB_LINE_ADDR_W-1:0] SUBLINE_PADDING= '0;
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/*************************************
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* 2nd cycle signals
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*************************************/
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////////////////////////////////////////////////////
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//2nd Cycle Control Signals
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always_ff @ (posedge clk) begin
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if (ls.new_request) begin
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stage2_addr <= ls_inputs.addr;
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@ -112,26 +116,17 @@ module dcache(
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end
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end
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/*************************************
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* General Control Logic
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*************************************/
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//LR and AMO ops are forced misses (if there is a tag hit they will reuse the same way however)
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//Signal is valid only for a single cycle, RAM enables are used to hold outputs in case of pipeline stalls
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////////////////////////////////////////////////////
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//General Control Logic
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//LR and AMO ops are forced misses (if there is a tag hit they will reuse the same way)
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//Signal is valid for a single cycle, RAM enables are used to hold outputs in case of pipeline stalls
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always_ff @ (posedge clk) begin
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if (rst)
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read_hit_allowed <= 0;
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else
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read_hit_allowed <= ls.new_request & ls_inputs.load & dcache_on & ~(amo.is_lr | amo.is_amo);
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read_hit_allowed <= ls.new_request & ls_inputs.load & dcache_on & ~(amo.is_lr | amo.is_amo);
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read_hit_data_valid <= read_hit_allowed;
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second_cycle <= ls.new_request;
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tag_update <= second_cycle & dcache_on & stage2_load & ~tag_hit;//Cache enabled, read miss
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end
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always_ff @ (posedge clk) begin
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if (rst)
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read_hit_data_valid <= 0;
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else
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read_hit_data_valid <= read_hit_allowed;
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end
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//LR reservation, cleared on exceptions
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always_ff @ (posedge clk) begin
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if (rst)
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@ -142,25 +137,8 @@ module dcache(
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reservation <= 0;
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end
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always_ff @ (posedge clk) begin
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if (rst)
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second_cycle <= 0;
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else
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second_cycle <= ls.new_request;
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end
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always_ff @ (posedge clk) begin
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if (rst)
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tag_update <= 0;
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else if (second_cycle)
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tag_update <= dcache_on & stage2_load & ~tag_hit; //Cache enabled, read miss
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else
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tag_update <= 0;
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end
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/*************************************
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* L1 Arbiter Interface
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*************************************/
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////////////////////////////////////////////////////
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//L1 Arbiter Interface
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assign l1_request.addr = {stage2_addr[31:2], 2'b0} ;//Memory interface aligns request to burst size (done there to support AMO line-read word-write)
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assign l1_request.data = stage2_data;
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assign l1_request.rnw = stage2_load;
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@ -187,10 +165,8 @@ module dcache(
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end
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assign l1_request.request = request | (second_cycle & (~(tag_hit & read_hit_allowed) | ~dcache_on));
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/*************************************
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* Cache Components
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*************************************/
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//Free running one hot cycler.
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////////////////////////////////////////////////////
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//Replacement policy (free runing one-hot cycler, i.e. pseudo random)
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cycler #(DCACHE_WAYS) replacement_policy (.*, .en(1'b1), .one_hot(replacement_way));
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//One-hot tag hit / update logic to binary int
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@ -208,7 +184,7 @@ module dcache(
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end
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end
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////////////////////////////////////////////////////
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//Tag banks
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dtag_banks dcache_tag_banks (.*,
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.stage1_addr(ls_inputs.addr),
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@ -222,10 +198,8 @@ module dcache(
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.extern_inv_complete(l1_response.inv_ack)
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);
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assign write_hit_be = stage2_be & {4{tag_hit}};
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//AMO op processing on incoming data
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////////////////////////////////////////////////////
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//AMO logic
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always_ff @ (posedge clk) begin
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amo_rs2 <= stage2_data;
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end
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@ -247,16 +221,23 @@ module dcache(
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new_line_data = l1_response.data;
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end
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assign sc_write_index = stage2_addr[DCACHE_SUB_LINE_ADDR_W+1:2];
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assign update_word_index = stage2_amo.is_sc ? sc_write_index : word_count;
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////////////////////////////////////////////////////////
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////////////////////////////////////////////////////
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//Data Bank(s)
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ddata_bank #(DCACHE_LINES*DCACHE_LINE_W*DCACHE_WAYS) data_bank (
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//Tag bank selection done with upper address bits
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//On miss, word index in line provided by: update_word_index
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assign write_hit_be = stage2_be & {4{tag_hit}};
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assign update_word_index = stage2_amo.is_sc ? sc_write_index : word_count;
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assign data_bank_addr_a = {tag_hit_way_int, stage2_addr[DCACHE_LINE_ADDR_W+DCACHE_SUB_LINE_ADDR_W+2-1:2]};
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assign data_bank_addr_b = {tag_update_way_int, stage2_addr[DCACHE_LINE_ADDR_W+DCACHE_SUB_LINE_ADDR_W+2-1:DCACHE_SUB_LINE_ADDR_W+2], update_word_index};
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ddata_bank #(.LINES(DCACHE_SIZE_IN_WORDS)) data_bank (
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.clk(clk),
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.addr_a({tag_hit_way_int, stage2_addr[DCACHE_LINE_ADDR_W+DCACHE_SUB_LINE_ADDR_W+2-1:2]}),
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.addr_b({tag_update_way_int, stage2_addr[DCACHE_LINE_ADDR_W+DCACHE_SUB_LINE_ADDR_W+2-1:DCACHE_SUB_LINE_ADDR_W+2], update_word_index}),
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.addr_a(data_bank_addr_a),
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.addr_b(data_bank_addr_b),
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.en_a(second_cycle),
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.en_b(l1_response.data_valid | (sc_complete & sc_success)),
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.be_a(write_hit_be),
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@ -265,10 +246,8 @@ module dcache(
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.data_out_a(dbank_data_out)
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);
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/*************************************
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* Output Muxing
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*************************************/
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////////////////////////////////////////////////////
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//Output
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always_ff @ (posedge clk) begin
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if (l1_response.data_valid & is_target_word)
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miss_data <= l1_response.data;
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@ -280,19 +259,11 @@ module dcache(
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assign data_out = miss_data | ({32{read_hit_data_valid}} & dbank_data_out);
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/*************************************
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* Pipeline Advancement
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*************************************/
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////////////////////////////////////////////////////
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//Pipeline Advancement
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assign line_complete = (l1_response.data_valid && (word_count == (DCACHE_LINE_W-1))); //covers load, LR, AMO
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assign store_complete = l1_request.ack & stage2_store & ~stage2_amo.is_sc;
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always_ff @ (posedge clk) begin
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if (rst)
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ls.data_valid <= 0;
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else
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ls.data_valid <= ((l1_response.data_valid & is_target_word) | (read_hit_allowed & tag_hit) | sc_complete);
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end
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//read miss complete includes store conditional complete
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always_ff @ (posedge clk) begin
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if (rst)
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@ -301,6 +272,13 @@ module dcache(
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read_miss_complete <= line_complete | sc_complete;
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end
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always_ff @ (posedge clk) begin
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if (rst)
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ls.data_valid <= 0;
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else
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ls.data_valid <= ((l1_response.data_valid & is_target_word) | (read_hit_allowed & tag_hit) | sc_complete);
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end
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assign ls.ready = (read_hit_allowed & tag_hit) | store_complete | (read_miss_complete) | idle;
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always_ff @ (posedge clk) begin
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@ -44,7 +44,10 @@ module dtag_banks(
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output logic[DCACHE_WAYS-1:0] tag_hit_way
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);
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typedef logic [DCACHE_TAG_W : 0] dtag_entry_t;
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typedef struct packed{
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logic valid;
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logic [DCACHE_TAG_W-1:0] tag;
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} dtag_entry_t;
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function logic[DCACHE_TAG_W-1:0] getTag(logic[31:0] addr);
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return addr[31 : 32 - DCACHE_TAG_W];
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@ -57,8 +60,7 @@ module dtag_banks(
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dtag_entry_t tag_line[DCACHE_WAYS - 1:0];
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dtag_entry_t inv_tag_line[DCACHE_WAYS - 1:0];
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dtag_entry_t stage2_tag;
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dtag_entry_t new_tag;
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dtag_entry_t new_tagline;
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logic miss_or_extern_invalidate;
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logic [DCACHE_WAYS - 1:0] update_tag_way;
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@ -68,15 +70,18 @@ module dtag_banks(
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logic[DCACHE_WAYS-1:0] inv_hit_way;
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logic[DCACHE_WAYS-1:0] inv_hit_way_r;
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logic [DCACHE_LINE_ADDR_W-1:0] update_port_addr;
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////////////////////////////////////////////////////
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//Implementation
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////////////////////////////////////////////////////
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//Muxing of cache miss or invalidation control logic and tags
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assign miss_or_extern_invalidate = update | extern_inv;
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assign update_port_addr = update ? getLineAddr(stage2_addr) : getLineAddr(inv_addr);
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assign stage2_tag = {1'b1, getTag(stage2_addr)};
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assign new_tag = {update, getTag(stage2_addr)};
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assign new_tagline.valid = update;//If not update then an invalidation is being performed
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assign new_tagline.tag = getTag(stage2_addr);
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always_ff @ (posedge clk) begin
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if (rst)
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@ -87,29 +92,39 @@ module dtag_banks(
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assign extern_inv_complete = (extern_inv & ~update) & inv_tags_accessed;
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genvar i;
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////////////////////////////////////////////////////
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//Memory instantiation and hit detection
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generate
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for (i=0; i < DCACHE_WAYS; i=i+1) begin : tag_bank_gen
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genvar i;
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dtag_entry_t stage2_hit_comparison_tagline;
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dtag_entry_t inv_hit_comparison_tagline;
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assign stage2_hit_comparison_tagline.valid = 1;
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assign stage2_hit_comparison_tagline.tag = getTag(stage2_addr);
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assign inv_hit_comparison_tagline.valid = 1;
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assign inv_hit_comparison_tagline.tag = getTag(inv_addr);
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for (i=0; i < DCACHE_WAYS; i=i+1) begin : dtag_bank_gen
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assign update_tag_way[i] = update_way[i] | (inv_hit_way[i] & extern_inv_complete);
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tag_bank #(DCACHE_TAG_W+1, DCACHE_LINES) dtag_bank (.*,
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tag_bank #($bits(dtag_entry_t), DCACHE_LINES) dtag_bank (.*,
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.en_a(stage1_adv), .wen_a(stage1_inv),
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.addr_a(getLineAddr(stage1_addr)),
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.data_in_a('0), .data_out_a(tag_line[i]),
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.en_b(miss_or_extern_invalidate), .wen_b(update_tag_way[i]),
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.addr_b(update_port_addr),
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.data_in_b(new_tag), .data_out_b(inv_tag_line[i])
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.data_in_b(new_tagline), .data_out_b(inv_tag_line[i])
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);
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assign inv_hit_way[i] = ({1'b1, getTag(inv_addr)} == inv_tag_line[i]);
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assign tag_hit_way[i] = (stage2_tag == tag_line[i]);
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assign inv_hit_way[i] = (inv_hit_comparison_tagline == inv_tag_line[i]);
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assign tag_hit_way[i] = (stage2_hit_comparison_tagline == tag_line[i]);
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end
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endgenerate
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assign tag_hit = |tag_hit_way;
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////////////////////////////////////////////////////
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//Assertions
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endmodule
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