updated makefile

This commit is contained in:
Eric Matthews 2019-09-04 13:56:52 -07:00
parent c9015dc180
commit 1df419913d
2 changed files with 16 additions and 6 deletions

View file

@ -1,6 +1,7 @@
#MAKEFLAGS += --silent
-include internal.mak
MAKEFILE_DIR=$(pwd)
TAIGA_DIR=/home/ematthew/taiga
@ -31,7 +32,7 @@ COMPLIANCE_TARGET=rv32im
#Benchmark parameters
#Assumes binaries are in the BENCHMARK_DIR
###############################################################
EMBENCH_DIR=/home/ematthew/Research/RISCV/sfu-rcl/taiga-embench/build/src
EMBENCH_DIR=/home/ematthew/Research/RISCV/sfu-rcl/taiga-embench
EMBENCH_BENCHMARKS = \
aha-mont64 \
crc32 \
@ -94,7 +95,7 @@ lint_full:
#Create hw_init files for benchmarks
$(embench_hw) : %.hw_init : %
$(ELF_TO_HW_INIT) $(EMBENCH_DIR)/$</$< $@ $<.sim_init
$(ELF_TO_HW_INIT) $(EMBENCH_DIR)/build/src/$</$< $@ $<.sim_init
#Run verilator
$(embench_logs) : %_full.log : % $(embench_hw)
@ -103,10 +104,6 @@ $(embench_logs) : %_full.log : % $(embench_hw)
run_embench_verilator: $(embench_logs)
cat $^ > embench.log
.PHONY: run_dhrystone_verilator
run_dhrystone_verilator :
$(call verilator_local_mem_test,dhrystone,\"/home/ematthew/Research/RISCV/software/taiga-benchmarks/dhrystone.riscv.hw_init\","/dev/null","/dev/null")
CRUFT= $(EMBENCH_BENCHMARKS) $(embench_hw) $(embench_sim) $(embench_logs) embench.log
#Called by compliance makefile

13
tools/internal.mak Normal file
View file

@ -0,0 +1,13 @@
.PHONY: run_dhrystone_verilator
run_dhrystone_verilator :
$(call verilator_local_mem_test,dhrystone,\"/home/ematthew/Research/RISCV/software/taiga-benchmarks/dhrystone.riscv.hw_init\","/dev/null","/dev/null")
.PHONY: build_embench
build_embench :
cd $(EMBENCH_DIR);\
rm -rf build;\
mkdir build;\
cd build;\
../configure --host=riscv32-unknown-elf --with-chip=speed-test --with-board=taiga-sim;\
make