Additional tracing support

core/branch_unit.sv

@@ -37,6 +37,7 @@ module branch_unit(
         //Trace signals
         output logic tr_branch_correct,
         output logic tr_branch_misspredict,
+        output logic tr_return_correct,
         output logic tr_return_misspredict
         );
 
@@ -194,6 +195,7 @@ module branch_unit(
     generate if (ENABLE_TRACE_INTERFACE) begin
         assign tr_branch_correct = instruction_is_completing & ~is_return & ~miss_predict;
         assign tr_branch_misspredict = instruction_is_completing & ~is_return & miss_predict;
+        assign tr_return_correct = instruction_is_completing & is_return & ~miss_predict;
         assign tr_return_misspredict = instruction_is_completing & is_return & miss_predict;
     end
     endgenerate

core/decode_and_issue.sv

@@ -67,6 +67,14 @@ module decode_and_issue (
         output logic tr_ls_operand_stall,
         output logic tr_div_operand_stall,
 
+        output logic tr_alu_op,
+        output logic tr_branch_or_jump_op,
+        output logic tr_load_op,
+        output logic tr_store_op,
+        output logic tr_mul_op,
+        output logic tr_div_op,
+        output logic tr_misc_op,
+
         output logic tr_instruction_issued_dec,
         output logic [31:0] tr_instruction_pc_dec,
         output logic [31:0] tr_instruction_data_dec
@@ -413,13 +421,22 @@ module decode_and_issue (
         assign tr_operand_stall = |(unit_needed & unit_ready) & issue_valid & ~load_store_operands_ready;
         assign tr_unit_stall = ~|(unit_needed & unit_ready) & issue_valid & load_store_operands_ready;
         assign tr_no_id_stall = |(unit_needed & unit_ready) & (fb_valid & ~ti.id_available & ~gc_issue_hold & ~gc_fetch_flush) & load_store_operands_ready;
-        assign tr_no_instruction_stall = ~fb_valid;
-        assign tr_other_stall = fb_valid & ~instruction_issued & ~(tr_operand_stall | tr_unit_stall | tr_no_id_stall | tr_no_instruction_stall) & ~gc_fetch_flush;
+        assign tr_no_instruction_stall = ~fb_valid | gc_fetch_flush;
+        assign tr_other_stall = fb_valid & ~instruction_issued & ~(tr_operand_stall | tr_unit_stall | tr_no_id_stall | tr_no_instruction_stall);
         assign tr_branch_operand_stall = tr_operand_stall & unit_needed[BRANCH_UNIT_ID];
         assign tr_alu_operand_stall = tr_operand_stall & unit_needed[ALU_UNIT_WB_ID] & ~unit_needed[BRANCH_UNIT_ID];
         assign tr_ls_operand_stall = tr_operand_stall & unit_needed[LS_UNIT_WB_ID];
         assign tr_div_operand_stall = tr_operand_stall & unit_needed[DIV_UNIT_WB_ID];
 
+        //Instruction Mix
+        assign tr_alu_op = instruction_issued && (opcode_trim inside {ARITH_T, ARITH_IMM_T, AUIPC_T, LUI_T} && ~tr_mul_op && ~tr_div_op);
+        assign tr_branch_or_jump_op = instruction_issued && (opcode_trim inside {JAL_T, JALR_T, BRANCH_T});
+        assign tr_load_op = instruction_issued && (opcode_trim inside {LOAD_T, AMO_T});
+        assign tr_store_op = instruction_issued && (opcode_trim inside {STORE_T});
+        assign tr_mul_op = instruction_issued && unit_needed[MUL_UNIT_WB_ID];
+        assign tr_div_op = instruction_issued && unit_needed[DIV_UNIT_WB_ID];
+        assign tr_misc_op = instruction_issued & ~(tr_alu_op | tr_branch_or_jump_op | tr_load_op | tr_store_op | tr_mul_op | tr_div_op);
+
         assign tr_instruction_issued_dec = instruction_issued;
         assign tr_instruction_pc_dec = fb.pc;
         assign tr_instruction_data_dec = fb.instruction;

core/taiga.sv

@@ -132,18 +132,30 @@ module taiga (
     logic tr_ls_operand_stall;
     logic tr_div_operand_stall;
 
+    logic tr_alu_op;
+    logic tr_branch_or_jump_op;
+    logic tr_load_op;
+    logic tr_store_op;
+    logic tr_mul_op;
+    logic tr_div_op;
+    logic tr_misc_op;
+
     logic tr_instruction_issued_dec;
     logic [31:0] tr_instruction_pc_dec;
     logic [31:0] tr_instruction_data_dec;
 
     logic tr_branch_correct;
     logic tr_branch_misspredict;
+    logic tr_return_correct;
     logic tr_return_misspredict;
-    logic tr_wb_mux_contention;
 
     logic tr_rs1_forwarding_needed;
     logic tr_rs2_forwarding_needed;
     logic tr_rs1_and_rs2_forwarding_needed;
+
+    unit_id_t tr_num_instructions_completing;
+    instruction_id_t tr_num_instructions_in_flight;
+    instruction_id_t tr_num_of_instructions_pending_writeback;
     ////////////////////////////////////////////////////
     //Implementation
 
@@ -231,13 +243,23 @@ module taiga (
             tr.events.alu_operand_stall <= tr_alu_operand_stall;
             tr.events.ls_operand_stall <= tr_ls_operand_stall;
             tr.events.div_operand_stall <= tr_div_operand_stall;
+            tr.events.alu_op <= tr_alu_op;
+            tr.events.branch_or_jump_op <= tr_branch_or_jump_op;
+            tr.events.load_op <= tr_load_op;
+            tr.events.store_op <= tr_store_op;
+            tr.events.mul_op <= tr_mul_op;
+            tr.events.div_op <= tr_div_op;
+            tr.events.misc_op <= tr_misc_op;
             tr.events.branch_correct <= tr_branch_correct;
             tr.events.branch_misspredict <= tr_branch_misspredict;
+            tr.events.return_correct <= tr_return_correct;
             tr.events.return_misspredict <= tr_return_misspredict;
-            tr.events.wb_mux_contention <= tr_wb_mux_contention;
             tr.events.rs1_forwarding_needed <= tr_rs1_forwarding_needed;
             tr.events.rs2_forwarding_needed <= tr_rs2_forwarding_needed;
             tr.events.rs1_and_rs2_forwarding_needed <= tr_rs1_and_rs2_forwarding_needed;
+            tr.events.num_instructions_completing <= tr_num_instructions_completing;
+            tr.events.num_instructions_in_flight <= tr_num_instructions_in_flight;
+            tr.events.num_of_instructions_pending_writeback <= tr_num_of_instructions_pending_writeback;
             tr.instruction_pc_dec <= tr_instruction_pc_dec;
             tr.instruction_data_dec <= tr_instruction_data_dec;
         end

core/taiga_types.sv

@@ -237,18 +237,30 @@ package taiga_types;
         logic ls_operand_stall;
         logic div_operand_stall;
 
+        //Instruction mix
+        logic alu_op;
+        logic branch_or_jump_op;
+        logic load_op;
+        logic store_op;
+        logic mul_op;
+        logic div_op;
+        logic misc_op;
+
         //Branch Unit
         logic branch_correct;
         logic branch_misspredict;
+        logic return_correct;
         logic return_misspredict;
 
-        //Writeback
-        logic wb_mux_contention;
-
         //Register File
         logic rs1_forwarding_needed;
         logic rs2_forwarding_needed;
         logic rs1_and_rs2_forwarding_needed;
+
+        //Writeback
+        unit_id_t num_instructions_completing;
+        instruction_id_t num_instructions_in_flight;
+        instruction_id_t num_of_instructions_pending_writeback;
     } taiga_trace_events_t;
 
     typedef struct packed {

core/write_back.sv

@@ -42,7 +42,9 @@ module write_back(
         input logic store_complete,
 
         //Trace signals
-        output logic tr_wb_mux_contention
+        output unit_id_t tr_num_instructions_completing,
+        output instruction_id_t tr_num_instructions_in_flight,
+        output instruction_id_t tr_num_of_instructions_pending_writeback
         );
     //////////////////////////////////////
 
@@ -208,11 +210,16 @@ module write_back(
     generate if (ENABLE_TRACE_INTERFACE) begin
         //Checks if any two pairs are set indicating mux contention
         always_comb begin
-            tr_wb_mux_contention = 0;
+            tr_num_instructions_completing = 0;
+            for (int i=0; i<NUM_WB_UNITS; i++) begin
+                tr_num_instructions_completing += unit_done[i];
+            end
+
+            tr_num_instructions_in_flight = 0;
+            tr_num_of_instructions_pending_writeback = 0;
             for (int i=0; i<MAX_INFLIGHT_COUNT-1; i++) begin
-                    for (int j=i+1; j<MAX_INFLIGHT_COUNT; j++) begin
-                        tr_wb_mux_contention |= (id_writeback_pending[i] & id_writeback_pending[j]);
-                    end
+                tr_num_instructions_in_flight += id_inuse[i];
+                tr_num_of_instructions_pending_writeback += id_writeback_pending[i];
             end
         end
     end

test_benches/verilator/TaigaTracer.cc

@@ -67,8 +67,10 @@ void TaigaTracer<TB>::reset_stats() {
 
 template <class TB>
 void TaigaTracer<TB>::update_stats() {
-    for (int i=0; i < numEvents; i++)
-        event_counters[i] += tb->taiga_events[i];
+    if (collect_stats) {
+        for (int i=0; i < numEvents; i++)
+            event_counters[i] += tb->taiga_events[i];
+    }
 }
 
 template <class TB>
@@ -129,6 +131,13 @@ void TaigaTracer<TB>::tick() {
 
 		cycle_count++;
 
+        if (check_instruction_issued(BENCHMARK_START_COLLECTION_NOP)) {
+            collect_stats = true;
+            reset_stats();
+        }
+        if (check_instruction_issued(BENCHMARK_END_COLLECTION_NOP)) {
+            collect_stats = false;
+        }
 		update_stats();
 		update_UART();
 		update_memory();

test_benches/verilator/TaigaTracer.h

@@ -30,6 +30,8 @@
 //#define TRACE_ON
 
 #define COMPLIANCE_SIG_PHASE_NOP 0x00B00013U
+#define BENCHMARK_START_COLLECTION_NOP 0x00C00013U
+#define BENCHMARK_END_COLLECTION_NOP 0x00D00013U
 #define ERROR_TERMINATION_NOP 0x00F00013U
 #define SUCCESS_TERMINATION_NOP 0x00A00013U
 
@@ -47,13 +49,23 @@ static const char * const eventNames[] = {
     "alu_operand_stall",
     "ls_operand_stall",
     "div_operand_stall",
+    "alu_op",
+    "branch_or_jump_op",
+    "load_op",
+    "store_op",
+    "mul_op",
+    "div_op",
+    "misc_op",
     "branch_correct",
     "branch_misspredict",
+    "return_correct",
     "return_misspredict",
-    "wb_mux_contention",
     "rs1_forwarding_needed",
     "rs2_forwarding_needed",
-    "rs1_and_rs2_forwarding_needed"
+    "rs1_and_rs2_forwarding_needed",
+    "num_instructions_completing",
+    "num_instructions_in_flight",
+    "num_of_instructions_pending_writeback"
 };
 static const int numEvents = arraySize(eventNames);
 
@@ -86,6 +98,8 @@ private:
   uint64_t cycle_count = 0;
   uint64_t event_counters[numEvents];
 
+  bool collect_stats = false;
+
   void update_stats();
   void update_UART();
   void update_memory();