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Decode/Issue unit-interface signal refactoring
This commit is contained in:
Eric Matthews
parent
bf5c12af25
commit
227bbc1385
9 changed files with 94 additions and 135 deletions
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@ -26,8 +26,8 @@ import taiga_types::*;
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module alu_unit(
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input logic clk,
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input logic rst,
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func_unit_ex_interface.unit alu_ex,
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unit_writeback_interface.unit alu_wb,
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unit_issue_interface.unit issue,
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unit_writeback_interface.unit wb,
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input alu_inputs_t alu_inputs
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);
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@ -86,13 +86,13 @@ module alu_unit(
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////////////////////////////////////////////////////
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//Output bank
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always_ff @ (posedge clk) begin
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if (alu_ex.possible_issue)
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rd_bank[alu_ex.instruction_id] <= result;
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if (issue.possible_issue)
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rd_bank[issue.instruction_id] <= result;
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end
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assign alu_ex.ready = 1;
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assign alu_wb.rd = rd_bank[alu_wb.writeback_instruction_id];
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assign alu_wb.done_next_cycle = alu_ex.instruction_id_one_hot & {MAX_INFLIGHT_COUNT{alu_ex.new_request_dec}};
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assign issue.ready = 1;
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assign wb.rd = rd_bank[wb.writeback_instruction_id];
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assign wb.done_next_cycle = issue.instruction_id_one_hot & {MAX_INFLIGHT_COUNT{issue.new_request}};
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////////////////////////////////////////////////////
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//Assertions
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@ -27,12 +27,14 @@ module branch_unit(
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input logic clk,
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input logic rst,
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func_unit_ex_interface.unit branch_ex,
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unit_issue_interface.unit issue,
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input branch_inputs_t branch_inputs,
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output branch_results_t br_results,
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ras_interface.branch_unit ras,
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output branch_flush,
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input branch_issued,
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//Trace signals
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output logic tr_branch_misspredict,
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output logic tr_return_misspredict
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@ -82,7 +84,7 @@ module branch_unit(
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instruction_id_t id;
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//implementation
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////////////////////////////////////////////////////
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assign branch_ex.ready = 1;
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assign issue.ready = 1;
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branch_comparator bc (
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.use_signed(branch_inputs.use_signed),
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@ -92,7 +94,7 @@ module branch_unit(
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.result(result)
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);
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assign branch_taken = branch_ex.new_request & ((~jump_ex & (result_ex ^ fn3_ex[0])) | jump_ex);
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assign branch_taken = branch_issued & ((~jump_ex & (result_ex ^ fn3_ex[0])) | jump_ex);
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assign jal_imm = {branch_inputs.instruction[31], branch_inputs.instruction[19:12], branch_inputs.instruction[20], branch_inputs.instruction[30:21]};
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@ -118,7 +120,7 @@ module branch_unit(
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assign jump_pc_dec = jump_base + pc_offset;
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always_ff @(posedge clk) begin
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if (branch_ex.new_request_dec) begin
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if (issue.new_request) begin
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fn3_ex <= branch_inputs.fn3;
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result_ex <= result;
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jump_ex <= (branch_inputs.jal | branch_inputs.jalr);
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@ -128,7 +130,7 @@ module branch_unit(
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//Predictor support
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////////////////////////////////////////////////////
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always_ff @(posedge clk) begin
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if (branch_ex.new_request_dec) begin
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if (issue.new_request) begin
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pc_ex <= branch_inputs.dec_pc;
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jump_pc <= {jump_pc_dec[31:1], 1'b0};
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njump_pc <= branch_inputs.dec_pc + 4;
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@ -144,7 +146,7 @@ module branch_unit(
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assign br_results.branch_ex_metadata = branch_metadata;
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assign br_results.branch_taken = branch_taken;
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assign br_results.branch_ex = branch_ex.new_request & branch_inputs.dec_pc_valid;
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assign br_results.branch_ex = branch_issued & branch_inputs.dec_pc_valid;
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assign br_results.is_return_ex = is_return;
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assign br_results.branch_prediction_used = branch_prediction_used;
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assign br_results.bp_update_way = bp_update_way;
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@ -152,16 +154,16 @@ module branch_unit(
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assign branch_correctly_taken = {br_results.branch_taken, branch_inputs.dec_pc[31:1]} == {1'b1, br_results.jump_pc[31:1]};
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assign branch_correclty_not_taken = {br_results.branch_taken, branch_inputs.dec_pc[31:1]} == {1'b0, br_results.njump_pc[31:1]};
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assign miss_predict = branch_ex.new_request && branch_inputs.dec_pc_valid && ~(branch_correctly_taken || branch_correclty_not_taken);
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assign miss_predict = branch_issued && branch_inputs.dec_pc_valid && ~(branch_correctly_taken || branch_correclty_not_taken);
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assign branch_flush = USE_BRANCH_PREDICTOR ? miss_predict : branch_ex.new_request & branch_taken & branch_inputs.dec_pc_valid;
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assign branch_flush = USE_BRANCH_PREDICTOR ? miss_predict : branch_issued & branch_taken & branch_inputs.dec_pc_valid;
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//RAS support
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////////////////////////////////////////////////////
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generate if (USE_BRANCH_PREDICTOR) begin
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always_ff @(posedge clk) begin
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is_call <= branch_ex.new_request_dec & branch_inputs.is_call;
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is_return <= branch_ex.new_request_dec & branch_inputs.is_return;
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is_call <= issue.new_request & branch_inputs.is_call;
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is_return <= issue.new_request & branch_inputs.is_return;
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end
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assign ras.push = is_call;
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106
core/decode.sv
106
core/decode.sv
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@ -41,17 +41,13 @@ module decode(
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output mul_inputs_t mul_inputs,
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output div_inputs_t div_inputs,
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func_unit_ex_interface.decode alu_ex,
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func_unit_ex_interface.decode ls_ex,
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func_unit_ex_interface.decode branch_ex,
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func_unit_ex_interface.decode gc_ex,
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func_unit_ex_interface.decode mul_ex,
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func_unit_ex_interface.decode div_ex,
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unit_issue_interface.decode unit_issue [NUM_UNITS-1:0],
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input logic gc_issue_hold,
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input logic gc_fetch_flush,
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input logic gc_issue_flush,
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output logic gc_flush_required,
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output logic branch_issued,
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output logic load_store_issue,
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@ -94,7 +90,7 @@ module decode(
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logic issue_valid;
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logic load_store_operands_ready;
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logic operands_ready;
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logic [NUM_UNITS-1:0] unit_operands_ready;
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logic mult_div_op;
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logic [NUM_WB_UNITS-1:0] new_request_for_id_gen;
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@ -108,7 +104,7 @@ module decode(
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logic valid_opcode;
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instruction_id_t last_id;
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genvar i;
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////////////////////////////////////////////////////
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//Implementation
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@ -176,17 +172,11 @@ module decode(
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////////////////////////////////////////////////////
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//Unit ready
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assign issue_ready[BRANCH_UNIT_ID] = new_request[BRANCH_UNIT_ID] & branch_ex.ready;
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assign issue_ready[ALU_UNIT_WB_ID] = new_request[ALU_UNIT_WB_ID] & alu_ex.ready;
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assign issue_ready[LS_UNIT_WB_ID] = new_request[LS_UNIT_WB_ID] & ls_ex.ready;
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assign issue_ready[GC_UNIT_ID] = new_request[GC_UNIT_ID] & gc_ex.ready;
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generate if (USE_MUL)
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assign issue_ready[MUL_UNIT_WB_ID] = new_request[MUL_UNIT_WB_ID] & mul_ex.ready;
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generate
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for (i=0; i<NUM_UNITS; i++) begin
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assign issue_ready[i] = new_request[i] & unit_issue[i].ready;
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end
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endgenerate
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generate if (USE_DIV)
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assign issue_ready[DIV_UNIT_WB_ID] = new_request[DIV_UNIT_WB_ID] & div_ex.ready;
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endgenerate
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////////////////////////////////////////////////////
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//Issue Determination
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@ -195,16 +185,13 @@ module decode(
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assign operands_ready = ~rf_decode.rs1_conflict & ~rf_decode.rs2_conflict;
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assign load_store_operands_ready = ~rf_decode.rs1_conflict & (~rf_decode.rs2_conflict | (rf_decode.rs2_conflict & load_store_forward_possible));
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assign issue[BRANCH_UNIT_ID] = issue_valid & operands_ready & issue_ready[BRANCH_UNIT_ID];
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assign issue[ALU_UNIT_WB_ID] = issue_valid & operands_ready & issue_ready[ALU_UNIT_WB_ID];
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assign issue[LS_UNIT_WB_ID] = issue_valid & load_store_operands_ready & issue_ready[LS_UNIT_WB_ID];
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assign issue[GC_UNIT_ID] = issue_valid & operands_ready & issue_ready[GC_UNIT_ID];
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generate if (USE_MUL)
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assign issue[MUL_UNIT_WB_ID] = issue_valid & operands_ready & issue_ready[MUL_UNIT_WB_ID];
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endgenerate
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generate if (USE_DIV)
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assign issue[DIV_UNIT_WB_ID] = issue_valid & operands_ready & issue_ready[DIV_UNIT_WB_ID];
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endgenerate
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//All units share the same operand ready logic except load-store which has an internal forwarding path
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always_comb begin
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unit_operands_ready = {NUM_UNITS{operands_ready}};
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unit_operands_ready[LS_UNIT_WB_ID] = load_store_operands_ready;
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end
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assign issue = {NUM_UNITS{issue_valid}} & unit_operands_ready & issue_ready;
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assign instruction_issued =
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((LS_INPUT_BUFFER_DEPTH >= MAX_INFLIGHT_COUNT) &&
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@ -321,6 +308,7 @@ module decode(
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assign branch_inputs.branch_metadata = fb.branch_metadata;
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assign branch_inputs.branch_prediction_used = fb.branch_prediction_used;
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assign branch_inputs.bp_update_way = fb.bp_update_way;
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////////////////////////////////////////////////////
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//Global Control unit inputs
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logic sfence;
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@ -409,59 +397,29 @@ module decode(
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////////////////////////////////////////////////////
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//Unit EX signals
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assign alu_ex.new_request_dec = issue[ALU_UNIT_WB_ID];
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assign ls_ex.new_request_dec = issue[LS_UNIT_WB_ID];
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assign branch_ex.new_request_dec = issue[BRANCH_UNIT_ID];
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assign gc_ex.new_request_dec = issue[GC_UNIT_ID];
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generate
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for(i = 0; i < NUM_UNITS; i++) begin
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assign unit_issue[i].possible_issue = new_request[i] & ti.id_available;
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assign unit_issue[i].new_request = issue[i];
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assign unit_issue[i].instruction_id = ti.issue_id;
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assign unit_issue[i].instruction_id_one_hot = ti.issue_id_one_hot;
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always_ff @(posedge clk) begin
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unit_issue[i].new_request_r = issue[i];
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end
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end
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endgenerate
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always_ff @(posedge clk) begin
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alu_ex.new_request <= issue[ALU_UNIT_WB_ID];
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ls_ex.new_request <= issue[LS_UNIT_WB_ID];
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gc_ex.new_request <= issue[GC_UNIT_ID];
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end
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//Branch new request is held if
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//Special case for branch unit:
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//Branch new request is held if the following instruction hasn't arrived at decode/issue yet
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always_ff @(posedge clk) begin
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if (rst)
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branch_ex.new_request <= 0;
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branch_issued <= 0;
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else if (issue[BRANCH_UNIT_ID])
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branch_ex.new_request <= 1;
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branch_issued <= 1;
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else if (fb_valid)
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branch_ex.new_request <= 0;
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branch_issued <= 0;
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end
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assign branch_ex.instruction_id_one_hot = ti.issue_id_one_hot;
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assign branch_ex.instruction_id = ti.issue_id;
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assign alu_ex.instruction_id_one_hot = ti.issue_id_one_hot;
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assign alu_ex.instruction_id = ti.issue_id;
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//Load Store unit stores ID in input FIFO
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assign gc_ex.instruction_id_one_hot = ti.issue_id_one_hot;
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assign gc_ex.instruction_id = ti.issue_id;
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generate if (USE_MUL)
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always_ff @(posedge clk) begin
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mul_ex.new_request <= issue[MUL_UNIT_WB_ID];
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end
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assign mul_ex.new_request_dec = issue[MUL_UNIT_WB_ID];
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assign mul_ex.instruction_id_one_hot = ti.issue_id_one_hot;
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assign mul_ex.instruction_id = ti.issue_id;
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assign mul_ex.possible_issue = new_request[MUL_UNIT_WB_ID] & ti.id_available;
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endgenerate
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generate if (USE_DIV)
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always_ff @(posedge clk) begin
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div_ex.new_request <= issue[DIV_UNIT_WB_ID];
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end
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//DIV unit stores ID in input FIFO
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assign div_ex.new_request_dec = issue[DIV_UNIT_WB_ID];
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assign div_ex.possible_issue = new_request[DIV_UNIT_WB_ID] & ti.id_available;
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endgenerate
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assign branch_ex.possible_issue = new_request[BRANCH_UNIT_ID] & ti.id_available;
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assign alu_ex.possible_issue = new_request[ALU_UNIT_WB_ID] & ti.id_available;
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assign ls_ex.possible_issue = new_request[LS_UNIT_WB_ID] & ti.id_available;
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assign gc_ex.possible_issue = new_request[GC_UNIT_ID] & ti.id_available;
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////////////////////////////////////////////////////
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//Illegal Opcode check
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always_comb begin
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@ -27,9 +27,10 @@ module div_unit
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(
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input logic clk,
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input logic rst,
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func_unit_ex_interface.unit div_ex,
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input div_inputs_t div_inputs,
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unit_writeback_interface.unit div_wb
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unit_issue_interface.unit issue,
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unit_writeback_interface.unit wb
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);
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logic computation_complete;
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@ -72,8 +73,8 @@ module div_unit
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) div_input_fifo (.fifo(input_fifo), .*);
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assign input_fifo.data_in = div_inputs;
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assign input_fifo.push = div_ex.new_request_dec;
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assign div_ex.ready = (DIV_INPUT_BUFFER_DEPTH >= MAX_INFLIGHT_COUNT) ? 1 : ~input_fifo.full;
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assign input_fifo.push = issue.new_request;
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assign issue.ready = (DIV_INPUT_BUFFER_DEPTH >= MAX_INFLIGHT_COUNT) ? 1 : ~input_fifo.full;
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assign input_fifo.pop = div_done;
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assign stage1 = input_fifo.data_out;
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@ -124,8 +125,8 @@ module div_unit
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rd_bank[stage1.instruction_id] <= wb_div_result;
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end
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assign div_wb.done_next_cycle = stage1.instruction_id_one_hot & {MAX_INFLIGHT_COUNT{div_done}};
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assign div_wb.rd = rd_bank[div_wb.writeback_instruction_id];
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assign wb.done_next_cycle = stage1.instruction_id_one_hot & {MAX_INFLIGHT_COUNT{div_done}};
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assign wb.rd = rd_bank[wb.writeback_instruction_id];
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////////////////////////////////////////////////////
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@ -30,7 +30,7 @@ module gc_unit(
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//Decode
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func_unit_ex_interface.unit gc_ex,
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unit_issue_interface.unit issue,
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input gc_inputs_t gc_inputs,
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input logic instruction_issued_no_rd,
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input logic gc_flush_required,
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@ -178,12 +178,12 @@ module gc_unit(
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////////////////////////////////////////////////////
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//GC Operation
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assign is_csr = gc_ex.new_request & gc_inputs.is_csr;
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assign is_csr = issue.new_request_r & gc_inputs.is_csr;
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assign gc_fetch_flush = branch_flush | gc_fetch_pc_override;
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always_ff @ (posedge clk) begin
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gc_issue_hold <= gc_ex.new_request_dec || is_csr || processing_csr || (next_state inside {PRE_CLEAR_STATE, CLEAR_STATE, TLB_CLEAR_STATE, IQ_DRAIN, IQ_DISCARD});
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gc_issue_hold <= issue.new_request || is_csr || processing_csr || (next_state inside {PRE_CLEAR_STATE, CLEAR_STATE, TLB_CLEAR_STATE, IQ_DRAIN, IQ_DISCARD});
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inuse_clear <= (next_state == CLEAR_STATE);
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inorder <= 0;//(next_state inside {LS_EXCEPTION_POSSIBLE, IQ_DRAIN});
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end
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@ -295,7 +295,7 @@ module gc_unit(
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//CSR reads are passed through the Load-Store unit
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//A CSR write is only committed once it is the oldest instruction in the pipeline
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//while processing a csr operation, gc_issue_hold prevents further instructions from being issued
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assign gc_ex.ready = 1;
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assign issue.ready = 1;
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always_ff @(posedge clk) begin
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if (rst)
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@ -311,9 +311,9 @@ module gc_unit(
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csr_ready_to_complete_r <= csr_ready_to_complete;
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csr_id_done <= id & {MAX_INFLIGHT_COUNT{csr_ready_to_complete}};
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csr_id <= instruction_id;
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if (gc_ex.new_request_dec) begin
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id <= gc_ex.instruction_id_one_hot;
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instruction_id <= gc_ex.instruction_id;
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if (issue.new_request) begin
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id <= issue.instruction_id_one_hot;
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instruction_id <= issue.instruction_id;
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end
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end
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@ -50,16 +50,17 @@ interface branch_predictor_interface;
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endinterface
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interface func_unit_ex_interface;
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logic new_request_dec;
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interface unit_issue_interface;
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logic possible_issue;
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logic new_request;
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logic ready;
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logic new_request_r;
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instruction_id_t instruction_id;
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instruction_id_one_hot_t instruction_id_one_hot;
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modport decode (input ready, output possible_issue, new_request_dec, new_request, instruction_id, instruction_id_one_hot);
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modport unit (output ready, input possible_issue, new_request_dec, new_request, instruction_id, instruction_id_one_hot);
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logic ready;
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modport decode (input ready, output possible_issue, new_request, new_request_r, instruction_id, instruction_id_one_hot);
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modport unit (output ready, input possible_issue, new_request, new_request_r, instruction_id, instruction_id_one_hot);
|
||||
endinterface
|
||||
|
||||
interface ras_interface;
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@ module load_store_unit (
|
|||
input logic clk,
|
||||
input logic rst,
|
||||
input load_store_inputs_t ls_inputs,
|
||||
func_unit_ex_interface.unit ls_ex,
|
||||
unit_issue_interface.unit issue,
|
||||
|
||||
input logic dcache_on,
|
||||
input logic clear_reservation,
|
||||
|
|
@ -58,7 +58,7 @@ module load_store_unit (
|
|||
output exception_packet_t ls_exception,
|
||||
output logic ls_exception_valid,
|
||||
|
||||
unit_writeback_interface.unit ls_wb
|
||||
unit_writeback_interface.unit wb
|
||||
);
|
||||
|
||||
localparam NUM_SUB_UNITS = USE_D_SCRATCH_MEM+USE_BUS+USE_DCACHE;
|
||||
|
|
@ -126,10 +126,10 @@ module load_store_unit (
|
|||
) ls_input_fifo (.fifo(input_fifo), .*);
|
||||
|
||||
assign input_fifo.data_in = ls_inputs;
|
||||
assign input_fifo.push = ls_ex.new_request_dec;
|
||||
assign ls_ex.ready = (LS_INPUT_BUFFER_DEPTH >= MAX_INFLIGHT_COUNT) ? 1 : ~input_fifo.full;
|
||||
assign input_fifo.push = issue.new_request;
|
||||
assign issue.ready = (LS_INPUT_BUFFER_DEPTH >= MAX_INFLIGHT_COUNT) ? 1 : ~input_fifo.full;
|
||||
assign input_fifo.pop = issue_request | gc_issue_flush;
|
||||
assign load_store_FIFO_emptying = input_fifo.almost_empty & issue_request & ~ls_ex.new_request_dec;
|
||||
assign load_store_FIFO_emptying = input_fifo.almost_empty & issue_request & ~issue.new_request;
|
||||
assign stage1 = input_fifo.data_out;
|
||||
|
||||
////////////////////////////////////////////////////
|
||||
|
|
@ -342,7 +342,7 @@ module load_store_unit (
|
|||
previous_load <= final_load_data;
|
||||
end
|
||||
|
||||
assign ls_wb.rd = rd_bank[ls_wb.writeback_instruction_id];
|
||||
assign wb.rd = rd_bank[wb.writeback_instruction_id];
|
||||
|
||||
logic exception_complete;
|
||||
logic ls_done;
|
||||
|
|
@ -351,7 +351,7 @@ module load_store_unit (
|
|||
end
|
||||
assign ls_done = load_complete | exception_complete;
|
||||
|
||||
assign ls_wb.done_next_cycle = csr_id_done | (stage2_attr.instruction_id_one_hot & {MAX_INFLIGHT_COUNT{ls_done}});
|
||||
assign wb.done_next_cycle = csr_id_done | (stage2_attr.instruction_id_one_hot & {MAX_INFLIGHT_COUNT{ls_done}});
|
||||
////////////////////////////////////////////////////
|
||||
//End of Implementation
|
||||
////////////////////////////////////////////////////
|
||||
|
|
|
|||
|
|
@ -26,9 +26,10 @@ import taiga_types::*;
|
|||
module mul_unit(
|
||||
input logic clk,
|
||||
input logic rst,
|
||||
func_unit_ex_interface.unit mul_ex,
|
||||
|
||||
input mul_inputs_t mul_inputs,
|
||||
unit_writeback_interface.unit mul_wb
|
||||
unit_issue_interface.unit issue,
|
||||
unit_writeback_interface.unit wb
|
||||
);
|
||||
|
||||
logic signed [65:0] result;
|
||||
|
|
@ -61,10 +62,10 @@ module mul_unit(
|
|||
mulh[0] <= (mul_inputs.op[1:0] != MUL_fn3[1:0]);
|
||||
mulh[1] <= mulh[0];
|
||||
|
||||
id[0] <= mul_ex.instruction_id;
|
||||
id[0] <= issue.instruction_id;
|
||||
id[1] <= id[0];
|
||||
|
||||
id_one_hot_done[0] <= mul_ex.instruction_id_one_hot & {MAX_INFLIGHT_COUNT{mul_ex.new_request_dec}};
|
||||
id_one_hot_done[0] <= issue.instruction_id_one_hot & {MAX_INFLIGHT_COUNT{issue.new_request}};
|
||||
id_one_hot_done[1] <= id_one_hot_done[0];
|
||||
end
|
||||
|
||||
|
|
@ -77,9 +78,9 @@ module mul_unit(
|
|||
|
||||
//Issue/write-back handshaking
|
||||
////////////////////////////////////////////////////
|
||||
assign mul_ex.ready = 1;
|
||||
assign mul_wb.rd = rd_bank[mul_wb.writeback_instruction_id];
|
||||
assign mul_wb.done_next_cycle = id_one_hot_done[1];
|
||||
assign issue.ready = 1;
|
||||
assign wb.rd = rd_bank[wb.writeback_instruction_id];
|
||||
assign wb.done_next_cycle = id_one_hot_done[1];
|
||||
|
||||
////////////////////////////////////////////////////
|
||||
//End of Implementation
|
||||
|
|
|
|||
|
|
@ -61,12 +61,7 @@ module taiga (
|
|||
div_inputs_t div_inputs;
|
||||
gc_inputs_t gc_inputs;
|
||||
|
||||
func_unit_ex_interface branch_ex();
|
||||
func_unit_ex_interface alu_ex();
|
||||
func_unit_ex_interface ls_ex();
|
||||
func_unit_ex_interface gc_ex();
|
||||
func_unit_ex_interface mul_ex();
|
||||
func_unit_ex_interface div_ex();
|
||||
unit_issue_interface unit_issue [NUM_UNITS-1:0]();
|
||||
|
||||
exception_packet_t ls_exception;
|
||||
logic ls_exception_valid;
|
||||
|
|
@ -134,6 +129,7 @@ module taiga (
|
|||
logic instruction_complete;
|
||||
logic instruction_issued;
|
||||
logic gc_flush_required;
|
||||
logic branch_issued;
|
||||
|
||||
//Trace Interface Signals
|
||||
logic tr_operand_stall;
|
||||
|
|
@ -182,9 +178,9 @@ module taiga (
|
|||
|
||||
////////////////////////////////////////////////////
|
||||
//Execution Units
|
||||
branch_unit branch_unit_block (.*);
|
||||
alu_unit alu_unit_block (.*, .alu_wb(unit_wb[ALU_UNIT_WB_ID]));
|
||||
load_store_unit load_store_unit_block (.*, .dcache_on(1'b1), .clear_reservation(1'b0), .tlb(dtlb), .ls_wb(unit_wb[LS_UNIT_WB_ID]), .l1_request(l1_request[L1_DCACHE_ID]), .l1_response(l1_response[L1_DCACHE_ID]));
|
||||
branch_unit branch_unit_block (.*, .issue(unit_issue[BRANCH_UNIT_ID]));
|
||||
alu_unit alu_unit_block (.*, .issue(unit_issue[ALU_UNIT_WB_ID]), .wb(unit_wb[ALU_UNIT_WB_ID]));
|
||||
load_store_unit load_store_unit_block (.*, .dcache_on(1'b1), .clear_reservation(1'b0), .tlb(dtlb), .issue(unit_issue[LS_UNIT_WB_ID]), .wb(unit_wb[LS_UNIT_WB_ID]), .l1_request(l1_request[L1_DCACHE_ID]), .l1_response(l1_response[L1_DCACHE_ID]));
|
||||
generate if (ENABLE_S_MODE) begin
|
||||
tlb_lut_ram #(DTLB_WAYS, DTLB_DEPTH) d_tlb (.*, .tlb(dtlb), .mmu(dmmu));
|
||||
mmu d_mmu (.*, .mmu(dmmu), .l1_request(l1_request[L1_DMMU_ID]), .l1_response(l1_response[L1_DMMU_ID]), .mmu_exception());
|
||||
|
|
@ -194,13 +190,13 @@ module taiga (
|
|||
assign dtlb.physical_address = dtlb.virtual_address;
|
||||
end
|
||||
endgenerate
|
||||
gc_unit gc_unit_block (.*);
|
||||
gc_unit gc_unit_block (.*, .issue(unit_issue[GC_UNIT_ID]));
|
||||
|
||||
generate if (USE_MUL)
|
||||
mul_unit mul_unit_block (.*, .mul_wb(unit_wb[MUL_UNIT_WB_ID]));
|
||||
mul_unit mul_unit_block (.*, .issue(unit_issue[MUL_UNIT_WB_ID]), .wb(unit_wb[MUL_UNIT_WB_ID]));
|
||||
endgenerate
|
||||
generate if (USE_DIV)
|
||||
div_unit div_unit_block (.*, .div_wb(unit_wb[DIV_UNIT_WB_ID]));
|
||||
div_unit div_unit_block (.*, .issue(unit_issue[DIV_UNIT_WB_ID]), .wb(unit_wb[DIV_UNIT_WB_ID]));
|
||||
endgenerate
|
||||
|
||||
////////////////////////////////////////////////////
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue