lsq interface split

core/interfaces.sv

@@ -208,14 +208,13 @@ interface load_store_queue_interface;
     logic new_issue;
     logic ready;
 
-    id_t id_needed_by_store;
     data_access_shared_inputs_t transaction_out;
     logic transaction_ready;
     logic empty;
     logic accepted;
 
-    modport queue (input addr, load, store, be, fn3, data_in, id, forwarded_store, data_id, possible_issue, new_issue, accepted, output ready, id_needed_by_store, transaction_out, transaction_ready, empty);
-    modport ls  (output addr, load, store, be, fn3, data_in, id, forwarded_store, data_id, possible_issue, new_issue, accepted, input ready, id_needed_by_store, transaction_out, transaction_ready, empty);
+    modport queue (input addr, load, store, be, fn3, data_in, id, forwarded_store, data_id, possible_issue, new_issue, accepted, output ready, transaction_out, transaction_ready, empty);
+    modport ls  (output addr, load, store, be, fn3, data_in, id, forwarded_store, data_id, possible_issue, new_issue, accepted, input ready, transaction_out, transaction_ready, empty);
 endinterface
 
 interface writeback_store_interface;

core/load_queue.sv

@@ -33,7 +33,7 @@ module load_queue
         input logic clk,
         input logic rst,
 
-        load_store_queue_interface.queue lsq,
+        input lsq_entry_t lsq,
         output lq_entry_t lq_entry,
         input logic [SQ_DEPTH-1:0] potential_store_conflicts,
         input load_ack,

core/load_store_queue.sv

@@ -45,6 +45,8 @@ module load_store_queue //ID-based input buffer for Load/Store Unit
     localparam SQ_DEPTH = 4;
     addr_hash_t addr_hash;
 
+    lsq_entry_t lsq_entry;
+
     lq_entry_t lq_entry;
     logic [SQ_DEPTH-1:0] potential_store_conflicts;
     logic load_ack;
@@ -73,10 +75,22 @@ module load_store_queue //ID-based input buffer for Load/Store Unit
         .addr_hash (addr_hash)
     );
 
+    assign lsq_entry.addr = lsq.addr;
+    assign lsq_entry.load = lsq.load;
+    assign lsq_entry.store = lsq.store;
+    assign lsq_entry.be = lsq.be;
+    assign lsq_entry.fn3 = lsq.fn3;
+    assign lsq_entry.data_in = lsq.data_in;
+    assign lsq_entry.id = lsq.id;
+    assign lsq_entry.forwarded_store = lsq.forwarded_store;
+    assign lsq_entry.data_id = lsq.data_id;
+    assign lsq_entry.possible_issue = lsq.possible_issue;
+    assign lsq_entry.new_issue = lsq.new_issue;
+
     load_queue #(.SQ_DEPTH(SQ_DEPTH)) lq_block (
         .clk (clk),
         .rst (rst | gc_issue_flush),
-        .lsq (lsq),
+        .lsq (lsq_entry),
         .lq_entry (lq_entry),
         .potential_store_conflicts (potential_store_conflicts),
         .load_ack (load_ack),
@@ -87,7 +101,7 @@ module load_store_queue //ID-based input buffer for Load/Store Unit
     store_queue #(.DEPTH(SQ_DEPTH)) sq_block (
         .clk (clk),
         .rst (rst | gc_issue_flush),
-        .lsq (lsq),
+        .lsq (lsq_entry),
         .sq_empty (sq_empty),
         .sq_full (sq_full),
         .addr_hash (addr_hash),

core/store_queue.sv

@@ -38,7 +38,7 @@ module store_queue
         output logic sq_full,
 
         //Request interface
-        load_store_queue_interface.queue lsq,
+        input lsq_entry_t lsq,
 
         //Address hash (shared by loads and stores)
         input addr_hash_t addr_hash,

core/taiga_types.sv

@@ -223,6 +223,21 @@ package taiga_types;
         logic con;
     } to_l1_arbiter_packet;
 
+    typedef struct packed {
+        logic [31:0] addr;
+        logic load;
+        logic store;
+        logic [3:0] be;
+        logic [2:0] fn3;
+        logic [31:0] data_in;
+        id_t id;
+        logic forwarded_store;
+        id_t data_id;
+
+        logic possible_issue;
+        logic new_issue;
+    } lsq_entry_t;
+
     typedef struct packed {
         logic [31:0] addr;
         logic [2:0] fn3;