resource savings

core/csr_regs.sv

@@ -31,6 +31,7 @@ module csr_regs (
         //GC unit
         input csr_inputs_t csr_inputs,
         input new_request,
+        input read_regs,
         input commit,
         input exception_packet_t gc_exception,
         output exception_packet_t csr_exception,
@@ -530,7 +531,10 @@ endgenerate
     end
 
     always_ff @(posedge clk) begin
-        selected_csr_r <= selected_csr;
+        if (read_regs)
+            selected_csr_r <= selected_csr;
+        else
+            selected_csr_r <= 0;
     end
 
     assign wb_csr = selected_csr_r;

core/gc_unit.sv

@@ -264,7 +264,7 @@ module gc_unit(
     assign csr_inputs.rs1_is_zero = (rs1_addr == 0);
     assign csr_inputs.rd_is_zero = gc_inputs.rd_is_zero;
 
-    csr_regs csr_registers (.*, .new_request(is_csr), .commit(csr_ready_to_complete_r));
+    csr_regs csr_registers (.*, .new_request(is_csr), .read_regs(csr_ready_to_complete), .commit(csr_ready_to_complete_r));
 
     ////////////////////////////////////////////////////
     //Decode / Write-back Handshaking

core/load_store_unit.sv

@@ -315,7 +315,7 @@ module load_store_unit (
 
     ////////////////////////////////////////////////////
     //Output bank
-    assign wb.rd = csr_done ? csr_rd : final_load_data;//rd_bank[wb.writeback_instruction_id];
+    assign wb.rd = csr_rd | final_load_data;
 
     logic exception_complete;
     logic ls_done;

core/write_back.sv

@@ -150,10 +150,7 @@ module write_back(
     end
 
     //Read table for unit ID (acks, and rd_addr for register file)
-    always_ff @(posedge clk) begin
-        retired_instruction_packet <= instruction_queue_empty ? ti.inflight_packet : packet_table[retired_id];
-    end
-
+    assign retired_instruction_packet = packet_table[retired_id_r];
     assign instruction_complete = retired_r & ~retired_instruction_packet.is_store;
 
     //Register file interaction