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CSR/GC restructuring
This commit is contained in:
Eric Matthews
parent
e56790a442
commit
2b547bc0d5
6 changed files with 92 additions and 66 deletions
117
core/csr_regs.sv
117
core/csr_regs.sv
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@ -35,11 +35,15 @@ module csr_regs
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input logic clk,
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input logic rst,
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//GC unit
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//Unit Interfaces
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input csr_inputs_t csr_inputs,
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input new_request,
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input read_regs,
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input commit,
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input logic new_request,
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input id_t id,
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unit_writeback_interface.unit wb,
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input logic gc_issue_hold,
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input logic commit,
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input exception_packet_t gc_exception,
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output exception_packet_t csr_exception,
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output logic [1:0] current_privilege,
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@ -74,7 +78,8 @@ module csr_regs
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(* ramstyle = "MLAB, no_rw_check" *) logic[XLEN-1:0] scratch_regs [31:0];//Only 0x1 and 0x3 used by supervisor and machine mode respectively
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logic[XLEN-1:0] scratch_out;
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csr_inputs_t csr_inputs_r;
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privilege_t privilege_level;
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privilege_t next_privilege_level;
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@ -116,32 +121,43 @@ module csr_regs
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logic done;
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logic [255:0] swrite_decoder;
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logic [255:0] swrite_en;
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logic [255:0] mwrite_decoder;
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logic [255:0] mwrite_en;
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////////////////////////////////////////////////////
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//Implementation
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always_ff @(posedge clk) begin
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if (new_request) begin
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csr_inputs_r <= csr_inputs;
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end
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end
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assign supervisor_write = commit && (csr_inputs_r.addr.rw_bits != CSR_READ_ONLY && csr_inputs_r.addr.privilege == SUPERVISOR_PRIVILEGE);
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assign machine_write = commit && (csr_inputs_r.addr.rw_bits != CSR_READ_ONLY && csr_inputs_r.addr.privilege == MACHINE_PRIVILEGE);
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always_comb begin
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swrite_decoder = 0;
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swrite_decoder[csr_inputs.addr.sub_addr] = supervisor_write ;
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swrite_decoder[csr_inputs_r.addr.sub_addr] = supervisor_write ;
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mwrite_decoder = 0;
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mwrite_decoder[csr_inputs.addr.sub_addr] = machine_write ;
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mwrite_decoder[csr_inputs_r.addr.sub_addr] = machine_write ;
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end
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//convert addr into packed struct form
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assign supervisor_write = commit && (csr_inputs.addr.rw_bits != CSR_READ_ONLY && csr_inputs.addr.privilege == SUPERVISOR_PRIVILEGE);
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assign machine_write = commit && (csr_inputs.addr.rw_bits != CSR_READ_ONLY && csr_inputs.addr.privilege == MACHINE_PRIVILEGE);
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always_ff @(posedge clk) begin
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swrite_en <= swrite_decoder;
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mwrite_en <= mwrite_decoder;
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end
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////////////////////////////////////////////////////
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//Exception Check
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assign privilege_exception = new_request & (csr_inputs.addr.privilege > privilege_level);
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assign csr_exception.valid = new_request & (invalid_addr | privilege_exception);
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assign privilege_exception = csr_inputs_r.addr.privilege > privilege_level;
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assign csr_exception.valid = commit & (invalid_addr | privilege_exception);
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always_comb begin
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case (csr_inputs.op)
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CSR_RW : updated_csr = csr_inputs.data;
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CSR_RS : updated_csr = selected_csr_r | csr_inputs.data;
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CSR_RC : updated_csr = selected_csr_r & ~csr_inputs.data;
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default : updated_csr = csr_inputs.data;
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case (csr_inputs_r.op)
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CSR_RW : updated_csr = csr_inputs_r.data;
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CSR_RS : updated_csr = selected_csr_r | csr_inputs_r.data;
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CSR_RC : updated_csr = selected_csr_r & ~csr_inputs_r.data;
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default : updated_csr = csr_inputs_r.data;
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endcase
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end
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@ -274,10 +290,10 @@ generate if (CONFIG.INCLUDE_M_MODE) begin
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end
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mstatus_t mstatus_write_mask;
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assign mstatus_write_mask = machine_write ? mstatus_mask : sstatus_mask;
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assign mstatus_write_mask = mwrite_en[MSTATUS[7:0]] ? mstatus_mask : sstatus_mask;
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always_comb begin
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if (mwrite_decoder[MSTATUS[7:0]] | swrite_decoder[SSTATUS[7:0]])
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if (mwrite_en[MSTATUS[7:0]] | swrite_en[SSTATUS[7:0]])
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mstatus_new = (mstatus & ~mstatus_write_mask) | (updated_csr & mstatus_write_mask);
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else if (interrupt | gc_exception.valid)
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mstatus_new = mstatus_exception;
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@ -299,7 +315,7 @@ generate if (CONFIG.INCLUDE_M_MODE) begin
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//No vectored mode, mode hard-coded to zero
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always_ff @(posedge clk) begin
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mtvec[1:0] <= '0;
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if (mwrite_decoder[MTVEC[7:0]])
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if (mwrite_en[MTVEC[7:0]])
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mtvec[XLEN-1:2] <= updated_csr[XLEN-1:2];
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end
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assign trap_pc = mtvec;
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@ -328,7 +344,7 @@ generate if (CONFIG.INCLUDE_M_MODE) begin
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always_ff @(posedge clk) begin
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if (rst)
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medeleg <= '0;
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else if (mwrite_decoder[MEDELEG[7:0]])
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else if (mwrite_en[MEDELEG[7:0]])
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medeleg <= (updated_csr & medeleg_mask);
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end
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@ -346,7 +362,7 @@ generate if (CONFIG.INCLUDE_M_MODE) begin
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always_ff @(posedge clk) begin
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if (rst)
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mideleg <= '0;
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else if (mwrite_decoder[MIDELEG[7:0]])
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else if (mwrite_en[MIDELEG[7:0]])
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mideleg <= (updated_csr & mideleg_mask);
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end
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@ -356,7 +372,7 @@ generate if (CONFIG.INCLUDE_M_MODE) begin
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always_ff @(posedge clk) begin
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if (rst)
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mip <= 0;
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else if (mwrite_decoder[MIP[7:0]])
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else if (mwrite_en[MIP[7:0]])
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mip <= (updated_csr & mip_mask);
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end
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@ -368,9 +384,9 @@ generate if (CONFIG.INCLUDE_M_MODE) begin
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always_ff @(posedge clk) begin
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if (rst)
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mie_reg <= '0;
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else if (mwrite_decoder[MIE[7:0]])
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else if (mwrite_en[MIE[7:0]])
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mie_reg <= (updated_csr & mie_mask);
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else if (swrite_decoder[SIE[7:0]])
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else if (swrite_en[SIE[7:0]])
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mie_reg <= (updated_csr & sie_mask);
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end
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@ -380,7 +396,7 @@ generate if (CONFIG.INCLUDE_M_MODE) begin
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//exception causing PC. Lower two bits tied to zero.
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always_ff @(posedge clk) begin
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mepc[1:0] <= '0;
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if (mwrite_decoder[MEPC[7:0]] | gc_exception.valid)
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if (mwrite_en[MEPC[7:0]] | gc_exception.valid)
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mepc[XLEN-1:2] <= gc_exception.valid ? exception_pc[XLEN-1:2] : updated_csr[XLEN-1:2];
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end
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assign csr_mepc = mepc;
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@ -429,7 +445,7 @@ generate if (CONFIG.INCLUDE_M_MODE) begin
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always_ff @(posedge clk) begin
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mcause.zeroes <= '0;
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if ((mcause_write_valid & mwrite_decoder[MCAUSE[7:0]]) | gc_exception.valid) begin
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if ((mcause_write_valid & mwrite_en[MCAUSE[7:0]]) | gc_exception.valid) begin
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mcause.interrupt <= gc_exception.valid ? 1'b0 : updated_csr[XLEN-1];
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mcause.code <= gc_exception.valid ? gc_exception.code : updated_csr[ECODE_W-1:0];
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end
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@ -438,7 +454,7 @@ generate if (CONFIG.INCLUDE_M_MODE) begin
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////////////////////////////////////////////////////
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//MTVAL
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always_ff @(posedge clk) begin
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if (mwrite_decoder[MTVAL[7:0]] | gc_exception.valid)
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if (mwrite_en[MTVAL[7:0]] | gc_exception.valid)
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mtval <= gc_exception.valid ? gc_exception.tval : updated_csr;
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end
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@ -446,13 +462,13 @@ generate if (CONFIG.INCLUDE_M_MODE) begin
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//Scratch regs
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//For efficient LUT-RAM packing, all scratch regs are stored together
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logic scratch_reg_write;
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assign scratch_reg_write = mwrite_decoder[MSCRATCH[7:0]] | swrite_decoder[SSCRATCH[7:0]];
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assign scratch_reg_write = mwrite_en[MSCRATCH[7:0]] | swrite_en[SSCRATCH[7:0]];
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always_ff @(posedge clk) begin
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if (scratch_reg_write)
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scratch_regs[{csr_inputs.addr.privilege, csr_inputs.addr.sub_addr[2:0]}] <= updated_csr;
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scratch_regs[{csr_inputs_r.addr.privilege, csr_inputs_r.addr.sub_addr[2:0]}] <= updated_csr;
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end
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assign scratch_out = scratch_regs[{csr_inputs.addr.privilege, csr_inputs.addr.sub_addr[2:0]}];
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assign scratch_out = scratch_regs[{csr_inputs_r.addr.privilege, csr_inputs_r.addr.sub_addr[2:0]}];
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end
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endgenerate
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@ -501,7 +517,7 @@ generate if (CONFIG.INCLUDE_S_MODE) begin
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always_ff @(posedge clk) begin
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if (rst)
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stvec <= {CONFIG.CSRS.RESET_VEC[XLEN-1:2], 2'b00};
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else if (swrite_decoder[STVEC[7:0]])
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else if (swrite_en[STVEC[7:0]])
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stvec <= (updated_csr & stvec_mask);
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end
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@ -512,7 +528,7 @@ generate if (CONFIG.INCLUDE_S_MODE) begin
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always_ff @(posedge clk) begin
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if (rst)
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satp <= 0;
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else if (swrite_decoder[SATP[7:0]])
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else if (swrite_en[SATP[7:0]])
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satp <= (updated_csr & satp_mask);
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end
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@ -531,10 +547,10 @@ endgenerate
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logic[CONFIG.CSRS.COUNTER_W-1:0] mcycle_input_next;
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logic mcycle_inc;
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assign mcycle_input_next[31:0] = mwrite_decoder[MCYCLE[7:0]] ? updated_csr : mcycle[31:0];
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assign mcycle_input_next[CONFIG.CSRS.COUNTER_W-1:32] = mwrite_decoder[MCYCLEH[7:0]] ? updated_csr[CONFIG.CSRS.COUNTER_W-33:0] : mcycle[CONFIG.CSRS.COUNTER_W-1:32];
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assign mcycle_input_next[31:0] = mwrite_en[MCYCLE[7:0]] ? updated_csr : mcycle[31:0];
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assign mcycle_input_next[CONFIG.CSRS.COUNTER_W-1:32] = mwrite_en[MCYCLEH[7:0]] ? updated_csr[CONFIG.CSRS.COUNTER_W-33:0] : mcycle[CONFIG.CSRS.COUNTER_W-1:32];
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assign mcycle_inc = ~(mwrite_decoder[MCYCLE[7:0]] | mwrite_decoder[MCYCLEH[7:0]]);
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assign mcycle_inc = ~(mwrite_en[MCYCLE[7:0]] | mwrite_en[MCYCLEH[7:0]]);
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always_ff @(posedge clk) begin
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if (rst)
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@ -545,10 +561,10 @@ endgenerate
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logic[CONFIG.CSRS.COUNTER_W-1:0] minst_ret_input_next;
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logic[LOG2_RETIRE_PORTS:0] minst_ret_inc;
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assign minst_ret_input_next[31:0] = mwrite_decoder[MINSTRET[7:0]] ? updated_csr : minst_ret[31:0];
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assign minst_ret_input_next[CONFIG.CSRS.COUNTER_W-1:32] = mwrite_decoder[MINSTRETH[7:0]] ? updated_csr[CONFIG.CSRS.COUNTER_W-33:0] : minst_ret[CONFIG.CSRS.COUNTER_W-1:32];
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assign minst_ret_input_next[31:0] = mwrite_en[MINSTRET[7:0]] ? updated_csr : minst_ret[31:0];
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assign minst_ret_input_next[CONFIG.CSRS.COUNTER_W-1:32] = mwrite_en[MINSTRETH[7:0]] ? updated_csr[CONFIG.CSRS.COUNTER_W-33:0] : minst_ret[CONFIG.CSRS.COUNTER_W-1:32];
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assign minst_ret_inc = {(LOG2_RETIRE_PORTS+1){~(mwrite_decoder[MINSTRET[7:0]] | mwrite_decoder[MINSTRETH[7:0]])}} & retire.count;
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assign minst_ret_inc = {(LOG2_RETIRE_PORTS+1){~(mwrite_en[MINSTRET[7:0]] | mwrite_en[MINSTRETH[7:0]])}} & retire.count;
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always_ff @(posedge clk) begin
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if (rst)
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@ -557,9 +573,12 @@ endgenerate
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minst_ret <= minst_ret_input_next + CONFIG.CSRS.COUNTER_W'(minst_ret_inc);
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end
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////////////////////////////////////////////////////
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//CSR mux
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always_comb begin
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invalid_addr = 0;
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case (csr_inputs.addr) inside
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case (csr_inputs_r.addr) inside
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//Machine info
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MISA : selected_csr = CONFIG.INCLUDE_M_MODE ? misa : 0;
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MVENDORID : selected_csr = CONFIG.INCLUDE_M_MODE ? mvendorid : 0;
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@ -626,10 +645,24 @@ endgenerate
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endcase
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end
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always_ff @(posedge clk) begin
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if (read_regs)
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if (commit)
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selected_csr_r <= selected_csr;
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end
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assign wb_csr = selected_csr_r;
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////////////////////////////////////////////////////
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//Output
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always_ff @(posedge clk) begin
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if (new_request)
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wb.id <= id;
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end
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always_ff @(posedge clk) begin
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if (rst)
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wb.done <= 0;
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else
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wb.done <= commit;
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end
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assign wb.rd = selected_csr_r;
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endmodule
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@ -58,6 +58,7 @@ module decode_and_issue
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output load_store_inputs_t ls_inputs,
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output branch_inputs_t branch_inputs,
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output gc_inputs_t gc_inputs,
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output csr_inputs_t csr_inputs,
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output mul_inputs_t mul_inputs,
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output div_inputs_t div_inputs,
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@ -498,11 +499,11 @@ module decode_and_issue
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assign gc_inputs.is_i_fence = CONFIG.INCLUDE_M_MODE & issue_to[UNIT_IDS.CSR] & is_ifence_r;
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//CSR support
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assign gc_inputs.csr_inputs.addr = issue.instruction[31:20];
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assign gc_inputs.csr_inputs.op = issue.fn3[1:0];
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assign gc_inputs.csr_inputs.data = issue.fn3[2] ? {27'b0, issue.rs_addr[RS1]} : rf.data[RS1];
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assign gc_inputs.csr_inputs.reads = ~((issue.fn3[1:0] == CSR_RW) && (issue.rd_addr == 0));
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assign gc_inputs.csr_inputs.writes = ~((issue.fn3[1:0] == CSR_RC) && (issue.rs_addr[RS1] == 0));
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assign csr_inputs.addr = issue.instruction[31:20];
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assign csr_inputs.op = issue.fn3[1:0];
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assign csr_inputs.data = issue.fn3[2] ? {27'b0, issue.rs_addr[RS1]} : rf.data[RS1];
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assign csr_inputs.reads = ~((issue.fn3[1:0] == CSR_RW) && (issue.rd_addr == 0));
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assign csr_inputs.writes = ~((issue.fn3[1:0] == CSR_RC) && (issue.rs_addr[RS1] == 0));
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assign gc_flush_required = CONFIG.INCLUDE_M_MODE && issue_to[UNIT_IDS.CSR] && potential_flush;
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@ -39,6 +39,7 @@ module gc_unit
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//Decode
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unit_issue_interface.unit issue,
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input gc_inputs_t gc_inputs,
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input csr_inputs_t csr_inputs,
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input logic gc_flush_required,
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//Branch miss predict
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input logic branch_flush,
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@ -310,10 +311,12 @@ module gc_unit
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csr_regs # (.CONFIG(CONFIG))
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csr_registers (
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.clk(clk), .rst(rst),
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.csr_inputs(stage1.csr_inputs),
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.new_request(stage1.is_csr),
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.read_regs(csr_ready_to_complete),
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.commit(csr_ready_to_complete_r),
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.csr_inputs(csr_inputs),
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.new_request(issue.possible_issue & gc_inputs.is_csr & ~gc_issue_hold),
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.id(issue.id),
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.wb(wb),
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.gc_issue_hold(gc_issue_hold),
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.commit(csr_ready_to_complete),
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.gc_exception(gc_exception_r),
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.csr_exception(csr_exception),
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.current_privilege(current_privilege),
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@ -355,19 +358,6 @@ module gc_unit
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csr_ready_to_complete_r <= csr_ready_to_complete;
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end
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always_ff @(posedge clk) begin
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csr_id <= instruction_id;
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if (issue.new_request) begin
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instruction_id <= issue.id;
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end
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end
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////////////////////////////////////////////////////
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//Output
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assign wb.rd = wb_csr;
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assign wb.done = csr_ready_to_complete_r;
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assign wb.id = csr_id;
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////////////////////////////////////////////////////
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//End of Implementation
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////////////////////////////////////////////////////
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@ -111,6 +111,7 @@ module taiga
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mul_inputs_t mul_inputs;
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div_inputs_t div_inputs;
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gc_inputs_t gc_inputs;
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csr_inputs_t csr_inputs;
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unit_issue_interface unit_issue [NUM_UNITS-1:0]();
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@ -391,6 +392,7 @@ module taiga
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.ls_inputs (ls_inputs),
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.branch_inputs (branch_inputs),
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.gc_inputs (gc_inputs),
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.csr_inputs (csr_inputs),
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.mul_inputs (mul_inputs),
|
||||
.div_inputs (div_inputs),
|
||||
.unit_issue (unit_issue),
|
||||
|
|
@ -524,6 +526,7 @@ module taiga
|
|||
.rst (rst),
|
||||
.issue (unit_issue[UNIT_IDS.CSR]),
|
||||
.gc_inputs (gc_inputs),
|
||||
.csr_inputs (csr_inputs),
|
||||
.gc_flush_required (gc_flush_required),
|
||||
.branch_flush (branch_flush),
|
||||
.potential_branch_exception (potential_branch_exception),
|
||||
|
|
|
|||
|
|
@ -183,7 +183,6 @@ package taiga_types;
|
|||
typedef struct packed{
|
||||
logic [31:0] pc;
|
||||
logic [31:0] instruction;
|
||||
csr_inputs_t csr_inputs;
|
||||
logic is_csr;
|
||||
logic is_fence;
|
||||
logic is_i_fence;
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
core/taiga_config.sv
|
||||
core/riscv_types.sv
|
||||
core/csr_types.sv
|
||||
core/taiga_types.sv
|
||||
l2_arbiter/l2_config_and_types.sv
|
||||
l2_arbiter/l2_interfaces.sv
|
||||
|
|
@ -10,7 +11,6 @@ local_memory/local_mem.sv
|
|||
core/interfaces.sv
|
||||
core/external_interfaces.sv
|
||||
|
||||
core/csr_types.sv
|
||||
core/csr_regs.sv
|
||||
core/gc_unit.sv
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue