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2nd cycle forwarding removal

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This commit is contained in:
Eric Matthews 2019-08-20 10:58:22 -07:00
parent ba64f8dcae
commit 306a868d1d
2 changed files with 8 additions and 36 deletions
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28
core/dcache.sv
View file

@ -37,11 +37,6 @@ module dcache(
output logic[31:0] data_out,
input amo_details_t amo,
input logic use_forwarded_data,
output logic dcache_forward_data,
output logic [2:0] dcache_stage2_fn3,
ls_sub_unit_interface.sub_unit ls
);
@ -69,12 +64,8 @@ module dcache(
logic stage2_store;
logic [3:0] stage2_be;
logic [2:0] stage2_fn3;
logic [31:0] stage2_data_in;
logic [31:0] stage2_data;
logic stage2_use_forwarded_data;
logic [31:0] stage2_forwarded_data;
amo_details_t stage2_amo;
logic [31:0] dbank_data_out;
@ -109,15 +100,6 @@ module dcache(
/*************************************
* 2nd cycle signals
*************************************/
always_ff @ (posedge clk) begin
if(rst)
stage2_use_forwarded_data <= 0;
else if (ls.new_request)
stage2_use_forwarded_data <= use_forwarded_data;
else if (store_complete)
stage2_use_forwarded_data <= 0;
end
always_ff @ (posedge clk) begin
if (ls.new_request) begin
stage2_addr <= ls_inputs.addr;
@ -125,14 +107,11 @@ module dcache(
stage2_load <= ls_inputs.load;
stage2_store <= ls_inputs.store;
stage2_fn3 <= ls_inputs.fn3;
stage2_data_in <= ls_inputs.data_in;
stage2_data <= ls_inputs.data_in;
stage2_amo <= amo;
end
end
assign dcache_stage2_fn3 = stage2_fn3;
assign dcache_forward_data = stage2_use_forwarded_data;
/*************************************
* General Control Logic
*************************************/
@ -248,7 +227,7 @@ module dcache(
//AMO op processing on incoming data
always_ff @ (posedge clk) begin
amo_rs2 <= stage2_data_in; //Only forwarding on STORE opcode
amo_rs2 <= stage2_data;
end
assign amo_alu_inputs.rs1_load = l1_response.data;
@ -263,7 +242,7 @@ module dcache(
if (stage2_amo.is_amo & is_target_word)
new_line_data = amo_result;
else if (stage2_amo.is_sc)
new_line_data = stage2_data_in;//Only forwarding on STORE opcode
new_line_data = stage2_data;
else
new_line_data = l1_response.data;
end
@ -272,7 +251,6 @@ module dcache(
assign sc_write_index = stage2_addr[DCACHE_SUB_LINE_ADDR_W+1:2];
assign update_word_index = stage2_amo.is_sc ? sc_write_index : word_count;
////////////////////////////////////////////////////////
assign stage2_data = stage2_use_forwarded_data ? ls_inputs.data_in : stage2_data_in;
//Data Bank(s)
ddata_bank #(DCACHE_LINES*DCACHE_LINE_W*DCACHE_WAYS) data_bank (

16
core/load_store_unit.sv
View file

@ -97,8 +97,6 @@ module load_store_unit (
logic unaligned_addr;
logic [NUM_SUB_UNITS-1:0] sub_unit_address_match;
logic dcache_forward_data;
logic [2:0] dcache_stage2_fn3;
logic unit_stall;
typedef struct packed{
@ -221,20 +219,16 @@ module load_store_unit (
assign shared_inputs.be = be;
assign shared_inputs.fn3 = stage1.fn3;
logic forward_data;
assign forward_data = stage1.load_store_forward | dcache_forward_data;
assign stage1_raw_data = forward_data ? previous_load : stage1.rs2;
assign stage1_raw_data = stage1.load_store_forward ? previous_load : stage1.rs2;
//Input: ABCD
//Assuming aligned requests,
//Possible byte selections: (A/C/D, B/D, C/D, D)
logic [1:0] data_in_mux;
always_comb begin
data_in_mux = dcache_forward_data ? dcache_stage2_fn3[1:0] : virtual_address[1:0];
shared_inputs.data_in[7:0] = stage1_raw_data[7:0];
shared_inputs.data_in[15:8] = (data_in_mux == 2'b01) ? stage1_raw_data[7:0] : stage1_raw_data[15:8];
shared_inputs.data_in[23:16] = (data_in_mux == 2'b10) ? stage1_raw_data[7:0] : stage1_raw_data[23:16];
case(data_in_mux)
shared_inputs.data_in[15:8] = (virtual_address[1:0] == 2'b01) ? stage1_raw_data[7:0] : stage1_raw_data[15:8];
shared_inputs.data_in[23:16] = (virtual_address[1:0] == 2'b10) ? stage1_raw_data[7:0] : stage1_raw_data[23:16];
case(virtual_address[1:0])
2'b10 : shared_inputs.data_in[31:24] = stage1_raw_data[15:8];
2'b11 : shared_inputs.data_in[31:24] = stage1_raw_data[7:0];
default : shared_inputs.data_in[31:24] = stage1_raw_data[31:24];
@ -294,7 +288,7 @@ module load_store_unit (
assign unit_ready[DCACHE_ID] = cache.ready;
assign unit_data_valid[DCACHE_ID] = cache.data_valid;
dcache data_cache (.*, .ls_inputs(shared_inputs), .ls(cache), .amo(stage1.amo), .use_forwarded_data(stage1.load_store_forward), .data_out(unit_data_array[DCACHE_ID]));
dcache data_cache (.*, .ls_inputs(shared_inputs), .ls(cache), .amo(stage1.amo), .data_out(unit_data_array[DCACHE_ID]));
end
endgenerate