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Fix sim for verilator

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This commit is contained in:
Chris Keilbart 2024-09-05 12:19:51 -07:00
parent a9c351ba22
commit 33a2546033
3 changed files with 6 additions and 4 deletions
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4
test_benches/verilator/CVA5Tracer.cc
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@ -152,13 +152,15 @@ void CVA5Tracer::start_tracer(const char *trace_file) {
}
uint64_t CVA5Tracer::cycle_count = 0;
uint64_t CVA5Tracer::get_cycle_count() {
return cycle_count;
}
CVA5Tracer::CVA5Tracer(std::ifstream& programFile) {
cycle_count = 0;
#ifdef TRACE_ON
Verilated::traceEverOn(true);
#endif

4
test_benches/verilator/CVA5Tracer.h
View file

@ -54,7 +54,7 @@ public:
void set_log_file(std::ofstream* logFile);
void set_pc_file(std::ofstream* pcFile);
void start_tracer(const char *trace_file);
uint64_t get_cycle_count();
static uint64_t get_cycle_count();
//DDR Simulation
Vcva5_sim *tb;
@ -71,7 +71,7 @@ private:
int reset_length = 64;
int stall_limit = 2000;
int stall_count = 0;
uint64_t cycle_count = 0;
static uint64_t cycle_count;
bool program_complete = false;

2
test_benches/verilator/cva5_sim.cc
View file

@ -12,7 +12,7 @@ CVA5Tracer *cva5Tracer;
char* csv_log_name;
//For time index on assertions
double sc_time_stamp () {
return cva5Tracer->get_cycle_count();
return CVA5Tracer::get_cycle_count();
}
const char* cva5_csv_log_file_name () {