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fixing dcache ways bug
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msa417
parent
c60027995d
commit
3bd08f7802
2 changed files with 108 additions and 45 deletions
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@ -112,53 +112,68 @@ module multicore_arbiter
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assign mems[i].write_outstanding = wcounts[i][$clog2(FIFO_DEPTH)] | write_outstanding[i];
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end endgenerate
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logic [4:0] rmw_len;
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logic [31:2] rmw_addr;
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logic [1:0] rmw_index;
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// logic [4:0] rmw_len;
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// logic [31:2] rmw_addr;
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logic [(NUM_CORES == 1 ? 1 : $clog2(NUM_CORES))-1:0] rmw_index;
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always_ff @(posedge clk or posedge rst) begin
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if (rst) begin
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rmw_len <= '0;
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rmw_addr <= '0;
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// rmw_len <= '0;
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// rmw_addr <= '0;
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rmw_index <= '0;
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end
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else if (in_req.rmw & in_req.rnw & request_push) begin
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rmw_addr <= in_req.addr;
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rmw_len <= in_req.rlen;
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else if (in_req.rmw & request_push) begin
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// rmw_addr <= in_req.addr;
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// rmw_len <= in_req.rlen;
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rmw_index <= chosen_port;
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end
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end
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logic[1:0] rmw_in_fifo;
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// logic[1:0] rmw_in_fifo;
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// always_ff @(posedge clk or posedge rst) begin
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// if (rst)
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// rmw_in_fifo <= 0;
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// else if (rmw_in_fifo == 2)begin
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// if(rmw_counter == rmw_len+1)
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// rmw_in_fifo <= 0;
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// else
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// rmw_in_fifo <= 2;
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// end else if (in_req.rmw & in_req.rnw & request_push)
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// rmw_in_fifo <= 1;
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// else if (out_req.rmw & out_req.rnw & request_pop)
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// rmw_in_fifo <= 2;
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// end
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// logic [4:0] rmw_counter;
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// always_ff @(posedge clk) begin
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// if(rst)begin
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// rmw_counter <= '0;
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// end else if(rmw_in_fifo==2) begin
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// if(rvalids[rmw_index])
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// rmw_counter <= rmw_counter + 1;
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// else
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// rmw_counter <= rmw_counter;
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// end else begin
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// rmw_counter <= '0;
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// end
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// end
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logic rmw_is_on;
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always_ff @(posedge clk or posedge rst) begin
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if (rst)
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rmw_in_fifo <= 0;
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else if (rmw_in_fifo == 2)begin
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if(rmw_counter == rmw_len+1)
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rmw_in_fifo <= 0;
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else
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rmw_in_fifo <= 2;
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end else if (in_req.rmw & in_req.rnw & request_push)
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rmw_in_fifo <= 1;
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else if (out_req.rmw & out_req.rnw & request_pop)
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rmw_in_fifo <= 2;
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end
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logic [4:0] rmw_counter;
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always_ff @(posedge clk) begin
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if(rst)begin
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rmw_counter <= '0;
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end else if(rmw_in_fifo==2) begin
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if(rvalids[rmw_index])
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rmw_counter <= rmw_counter + 1;
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else
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rmw_counter <= rmw_counter;
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end else begin
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rmw_counter <= '0;
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if (rst) begin
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rmw_is_on <= 1'b0;
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end else if(in_req.rmw & request_push) begin
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rmw_is_on <= 1'b1;
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end else if(in_req.rmw==0) begin
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rmw_is_on <= 1'b0;
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end
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end
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logic[NUM_CORES-1:0] accept_request_from_rmw_core;
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assign request_push = ~request_fifo.full & |requests & ((rmw_in_fifo==0) | in_req.rnw | rmw_addr[31:6] != in_req.addr[31:6]);
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logic rmw_hit;
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assign rmw_hit = |(requests & accept_request_from_rmw_core);
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assign accept_request_from_rmw_core = (rmw_is_on ? (1'b1 << rmw_index) : {NUM_CORES{1'b1}});
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assign request_push = ~request_fifo.full & |requests & (~rmw_is_on | rmw_hit);//((rmw_in_fifo==0) | in_req.rnw | rmw_addr[31:6] != in_req.addr[31:6]);
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assign request_fifo.data_in = in_req;
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assign out_req = request_fifo.data_out;
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assign request_valid = request_fifo.valid;
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@ -176,7 +191,7 @@ module multicore_arbiter
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//Arbitration
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round_robin #(.NUM_PORTS(NUM_CORES)) rr (
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.requests(requests),
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.requests(requests & accept_request_from_rmw_core),
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.grant(request_push),
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.grantee(chosen_port),
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.*);
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@ -185,8 +185,19 @@ module dcache_inv
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logic stage1_tb_wval_r;
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logic[CONFIG.DCACHE.WAYS-1:0] hit_ohot_r;
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assign a_en = snoop_write | (stage1_tb_write_r & ~inv_matches_stage1) | ls.new_request;
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assign a_wbe = ({CONFIG.DCACHE.WAYS{snoop_write}} & snoop_hit) | ({CONFIG.DCACHE.WAYS{stage1_tb_write_r}} & (stage1_type == CBO ? hit_ohot_r : replacement_way));
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assign a_en = snoop_write | stage1_tb_write_r | ls.new_request ;// & ~inv_matches_stage1 )
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assign a_wbe = ({CONFIG.DCACHE.WAYS{snoop_write}} & snoop_hit) | ({CONFIG.DCACHE.WAYS{stage1_tb_write_r}} & (stage1_type == CBO ? hit_ohot_r : (coming_to_read_after_snoop_reg == 1'b1 ? hit_ohot_r : replacement_way)));
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logic[CONFIG.DCACHE.WAYS-1:0] rmw_refill_way;
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always_ff @(posedge clk) begin
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if (rst)
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rmw_refill_way <= 0;
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else if (current_state==RMW_FILLING & a_wbe!=0)
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rmw_refill_way <= a_wbe;
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else if (current_state!=RMW_FILLING)
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rmw_refill_way <= 0;
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end
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always_comb begin
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if (snoop_write)
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@ -248,10 +259,15 @@ module dcache_inv
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logic hit_r;
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logic[CONFIG.DCACHE.WAYS-1:0] hit_ohot;
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logic hit_state = 0;
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always_comb begin
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hit_ohot = '0;
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for (int i = 0; i < CONFIG.DCACHE.WAYS; i++)
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hit_ohot[i] = a_rdata[i].valid & (a_rdata[i].tag == stage1.addr[2+SCONFIG.SUB_LINE_ADDR_W+SCONFIG.LINE_ADDR_W+:SCONFIG.TAG_W]);
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// if(hit_state==2'd2)begin
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// hit_ohot = hit_ohot_r;
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// end else begin
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for (int i = 0; i < CONFIG.DCACHE.WAYS; i++)
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hit_ohot[i] = a_rdata[i].valid & (a_rdata[i].tag == stage1.addr[2+SCONFIG.SUB_LINE_ADDR_W+SCONFIG.LINE_ADDR_W+:SCONFIG.TAG_W]);
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// end
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end
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assign hit = |hit_ohot;
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@ -259,9 +275,26 @@ module dcache_inv
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if (stage0_advance_r) begin
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hit_r <= hit;
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hit_ohot_r <= hit_ohot;
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end
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end
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// else if(hit_state==2'd1 && (stage1_tb_write_r & ~inv_matches_stage1))begin
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// hit_r <= 0;
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// hit_ohot_r <= a_wbe;
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// end
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// end else if((rmw_stage1_tb_write))begin
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// hit_r <= 0;
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// end
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end
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// always_ff @(posedge clk)begin
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// if(rst)begin
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// hit_state<=2'd0;
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// end else if(stage0_advance_r) begin
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// hit_state<=2'd0;
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// end else if(rmw_retry)begin
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// hit_state<=2'd1;
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// end
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// end
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////////////////////////////////////////////////////
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//Atomic read/modify/write state machine
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//Separate from other logic because atomic requests will need to be retried on a snoop invalidation
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@ -292,9 +325,19 @@ module dcache_inv
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current_state <= next_state;
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end
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logic coming_to_read_after_snoop;
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logic coming_to_read_after_snoop_reg;
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always_ff @(posedge clk) begin
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if (rst)
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coming_to_read_after_snoop_reg <= 0;
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else
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coming_to_read_after_snoop_reg <= coming_to_read_after_snoop;
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end
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always_comb begin
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unique case (current_state)
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RMW_READ : begin
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coming_to_read_after_snoop = coming_to_read_after_snoop_reg;
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rmw_mem_request = 1;
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rmw_mem_rnw = 1;
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rmw_stage1_tb_write = mem.ack & ~stage1.uncacheable;
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@ -305,6 +348,7 @@ module dcache_inv
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next_state = mem.ack ? RMW_FILLING : RMW_READ;
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end
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RMW_WRITE : begin
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coming_to_read_after_snoop = 0;
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rmw_mem_request = ~rmw_retry;
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rmw_mem_rnw = 0;
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rmw_stage1_tb_write = 0;
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@ -314,12 +358,14 @@ module dcache_inv
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rmw_stage1_done = mem.ack;
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if (mem.ack)
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next_state = RMW_IDLE;
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else if (rmw_retry)
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else if (rmw_retry)begin
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next_state = RMW_READ;
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else
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coming_to_read_after_snoop = 1;
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end else
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next_state = RMW_WRITE;
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end
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RMW_FILLING : begin
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coming_to_read_after_snoop = 0;
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rmw_mem_request = 0;
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rmw_mem_rnw = 'x;
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rmw_stage1_tb_write = 0;
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@ -327,12 +373,14 @@ module dcache_inv
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rmw_db_wdata = mem.rdata;
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rmw_ls_data_valid = 0;
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rmw_stage1_done = 0;
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if (return_done)
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if (return_done)begin
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next_state = rmw_retry ? RMW_READ : RMW_WRITE;
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else
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coming_to_read_after_snoop = rmw_retry;
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end else
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next_state = RMW_FILLING;
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end
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RMW_IDLE : begin
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coming_to_read_after_snoop = 0;
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rmw_mem_request = 0;
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rmw_mem_rnw = 'x;
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rmw_stage1_tb_write = 0;
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