github-mirrors/cva5
1
0
Fork 0
mirror of https://github.com/openhwgroup/cva5.git synced 2025-04-24 14:08:57 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

paramaterized read ports on basic LUTRAM block

Browse source
This commit is contained in:
Eric Matthews 2020-06-01 10:46:25 -07:00
parent a0f4368f85
commit 421385747c
2 changed files with 17 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

13
core/lut_ram.sv
View file

@ -22,17 +22,18 @@
module lut_ram #(
parameter WIDTH = 32,
parameter DEPTH = 32
parameter DEPTH = 32,
parameter READ_PORTS = 2
)
(
input logic clk,
input logic[$clog2(DEPTH)-1:0] waddr,
input logic[$clog2(DEPTH)-1:0] raddr,
input logic[$clog2(DEPTH)-1:0] raddr [READ_PORTS],
input logic ram_write,
input logic[WIDTH-1:0] new_ram_data,
output logic[WIDTH-1:0] ram_data_out
output logic[WIDTH-1:0] ram_data_out [READ_PORTS]
);
@ -44,6 +45,10 @@ module lut_ram #(
ram[waddr] <= new_ram_data;
end
assign ram_data_out = ram[raddr];
always_comb begin
for (int i = 0; i < READ_PORTS; i++) begin
ram_data_out[i] = ram[raddr[i]];
end
end
endmodule

13
core/tlb_lut_ram.sv
View file

@ -56,7 +56,8 @@ module tlb_lut_ram #(
logic [WAYS-1:0] tag_hit;
logic [WAYS-1:0] replacement_way;
tlb_entry_t ram_data [WAYS-1:0];
logic [$bits(tlb_entry_t)-1:0] ram_data [WAYS-1:0][1];
tlb_entry_t ram_entry [WAYS-1:0];
tlb_entry_t new_entry;
logic flush_in_progress;
@ -79,9 +80,11 @@ module tlb_lut_ram #(
genvar i;
generate
for (i=0; i<WAYS; i=i+1) begin : lut_rams
lut_ram #(.WIDTH($bits(tlb_entry_t)), .DEPTH(DEPTH)) ram_block (.clk(clk),
lut_ram #(.WIDTH($bits(tlb_entry_t)), .DEPTH(DEPTH), .READ_PORTS(1))
ram_block (.clk(clk),
.waddr(tlb_write_addr), .ram_write(tlb_write[i]), .new_ram_data(new_entry),
.raddr(tlb_read_addr), .ram_data_out(ram_data[i]));
.raddr({tlb_read_addr}), .ram_data_out(ram_data[i]));
assign ram_entry[i] = ram_data[i][0];
end
endgenerate
@ -114,7 +117,7 @@ module tlb_lut_ram #(
always_comb begin
for (int i=0; i<WAYS; i=i+1) begin
tag_hit[i] = {ram_data[i].valid, ram_data[i].tag} == {1'b1, virtual_tag};
tag_hit[i] = {ram_entry[i].valid, ram_entry[i].tag} == {1'b1, virtual_tag};
end
end
@ -138,7 +141,7 @@ module tlb_lut_ram #(
tlb.physical_address[11:0] = tlb.virtual_address[11:0];
tlb.physical_address[31:12] = tlb.virtual_address[31:12];
for (int i=0; i<WAYS; i=i+1) begin
if(tag_hit[i] & tlb_on) tlb.physical_address[31:12] = ram_data[i].phys_addr;
if(tag_hit[i] & tlb_on) tlb.physical_address[31:12] = ram_entry[i].phys_addr;
end
end