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Simulation tracing improvements

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Signed-off-by: Eric Matthews <ematthew@sfu.ca>
This commit is contained in:
Eric Matthews 2022-11-14 12:03:35 -05:00
parent 7de7e1a5c0
commit 4d42d3445d
6 changed files with 37 additions and 26 deletions
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42
test_benches/verilator/AXI_DDR_simulation/axi_ddr_sim.cc
View file

@ -36,7 +36,7 @@ axi_ddr_sim::axi_ddr_sim(string filepath, uint32_t starting_memory_location, int
//Parse the uniform pages
uint32_t page_index = starting_memory_location/PAGE_SIZE;
for (; page_index < max_pages; page_index++){
ddr_page page;
ddr_page page {};
for(int data_index = 0; data_index < PAGE_SIZE/4; data_index++){
getline(input_memory_file, line);
//Read 32-bit number represented through hexidecimals
@ -63,7 +63,7 @@ axi_ddr_sim::axi_ddr_sim(ifstream & input_memory_file, Vcva5_sim * tb){
bool not_finished = true;
uint32_t page_index = starting_location/PAGE_SIZE;
for (; page_index < max_pages; page_index++){
ddr_page page;
ddr_page page {};
for(int data_index = 0; data_index < PAGE_SIZE/4; data_index++){
not_finished = (bool)getline(input_memory_file, line);
@ -90,23 +90,24 @@ axi_ddr_sim::axi_ddr_sim(ifstream & input_memory_file, Vcva5_sim * tb){
int axi_ddr_sim::get_data(uint32_t data_address){
uint32_t starting_address = (data_address / PAGE_SIZE) * PAGE_SIZE;
if(ddr_pages.count(starting_address)){ //If page exists
return ddr_pages[starting_address].return_data(data_address%PAGE_SIZE/4);
}
else{//If it doesn't, instantiate a new page
ddr_page page;
if(!ddr_pages.count(starting_address)){ //If page does not exist
ddr_page page {};
ddr_pages.insert(pair<uint32_t,ddr_page>(starting_address, page));
assert(ddr_pages.count(starting_address)); //Check if it was intialized
return ddr_pages[starting_address].return_data(data_address%PAGE_SIZE/4);
assert(ddr_pages.count(starting_address));
}
return ddr_pages[starting_address].return_data(data_address%PAGE_SIZE/4);
}
void axi_ddr_sim::set_data(uint32_t data_address, uint32_t set_data, uint32_t byte_enable){
uint32_t data = get_data(data_address);
uint32_t starting_address = (data_address / PAGE_SIZE) * PAGE_SIZE;
if(!ddr_pages.count(starting_address)){ //If page does not exist
ddr_page page {};
ddr_pages.insert(pair<uint32_t,ddr_page>(starting_address, page));
assert(ddr_pages.count(starting_address)); //Check if it was intialized
}
data = (data & ~byte_enable) | (set_data & byte_enable);
ddr_pages[starting_address].write_data(data_address%PAGE_SIZE/4, data);
};
@ -119,6 +120,7 @@ void axi_ddr_sim::parse_input_signals(){
if(tb->ddr_axi_awvalid && wr_ad_channel_queue.size() < MAX_INFLIGHT_WR_REQ){
AXI_write_address_channel_signals elem{tb->ddr_axi_awaddr, tb->ddr_axi_awlen, tb->ddr_axi_awsize, tb->ddr_axi_awburst,tb->ddr_axi_awcache,tb->ddr_axi_awid};
wr_ad_channel_queue.push(elem);
order_queue.push(1);
}
//If the master has write data
if(tb->ddr_axi_wvalid){
@ -129,6 +131,7 @@ void axi_ddr_sim::parse_input_signals(){
if(tb->ddr_axi_arvalid && rd_ad_channel_queue.size() < MAX_INFLIGHT_RD_REQ){
AXI_read_address_channel_signals elem{tb->ddr_axi_araddr, tb->ddr_axi_arlen, tb->ddr_axi_arsize, tb->ddr_axi_arburst, tb->ddr_axi_arcache, tb->ddr_axi_arid};
rd_ad_channel_queue.push(elem);
order_queue.push(0);
}
}
@ -152,7 +155,7 @@ void axi_ddr_sim::parse_output_signals(){
tb->ddr_axi_wready = 1;
//Write Req
if(wr_ad_channel_queue.size() < MAX_INFLIGHT_WR_REQ)
if((wr_ad_channel_queue.size() < MAX_INFLIGHT_WR_REQ))
tb->ddr_axi_awready = 1;
else
tb->ddr_axi_awready = 0;
@ -207,7 +210,7 @@ void axi_ddr_sim::parse_output_signals(){
}
void axi_ddr_sim::handle_read_req(){
if(rd_ad_channel_queue.size() > 0 ){
if(rd_ad_channel_queue.size() > 0 && (order_queue.front() == 0)){
if(current_read_parameters.delay_cycles_left == 0){
AXI_read_data_channel_signals elem;
elem.rid = rd_ad_channel_queue.front().arid;
@ -233,9 +236,15 @@ void axi_ddr_sim::handle_read_req(){
if(current_read_parameters.number_of_bursts_left == 0){
elem.rlast = 1;
rd_ad_channel_queue.pop();
order_queue.pop();
}
else
elem.rlast = 0;
if ((current_read_parameters.address >> 24) == 0x88) {
elem.rdata = 0xFFFFFF21;
}
r_data_channel_queue.push(elem);
}
else{
@ -248,8 +257,8 @@ void axi_ddr_sim::handle_read_req(){
void axi_ddr_sim::handle_write_req(){
//cout << "w_data_channel_queue size: " << w_data_channel_queue.size() << endl;
//cout << "current_write_parameters.number_of_bursts_left: " << current_write_parameters.number_of_bursts_left << endl;
if(w_data_channel_queue.size() > 0 && current_write_parameters.number_of_bursts_left > 0){
if(current_write_parameters.delay_cycles_left == 0){
if(w_data_channel_queue.size() > 0 && current_write_parameters.number_of_bursts_left > 0 && (order_queue.front() == 1)){
if(current_write_parameters.delay_cycles_left == 0){
AXI_write_data_channel_signals elem = w_data_channel_queue.front();
w_data_channel_queue.pop();
//Calculate Byte Enable
@ -293,6 +302,7 @@ void axi_ddr_sim::handle_write_req(){
resp_elem.bid = elem.wid;
resp_elem.bresp = 0;
wr_ad_channel_queue.pop();
order_queue.pop();
w_res_channel_queue.push(resp_elem);
}
}
@ -305,7 +315,7 @@ void axi_ddr_sim::handle_write_req(){
void axi_ddr_sim::update_current_read_parameters(){
//If I can serve a new read request
if(rd_ad_channel_queue.size() > 0 && current_read_parameters.number_of_bursts_left == 0){
if(rd_ad_channel_queue.size() > 0 && current_read_parameters.number_of_bursts_left == 0 && (order_queue.front() == 0)){
current_read_parameters.address = rd_ad_channel_queue.front().araddr;
current_read_parameters.number_of_bursts_left = rd_ad_channel_queue.front().arlen +1;
current_read_parameters.delay_cycles_left = read_distribution(generator);
@ -328,7 +338,7 @@ void axi_ddr_sim::update_current_read_parameters(){
void axi_ddr_sim::update_current_write_parameters(){
//If I can serve a new read request
if(wr_ad_channel_queue.size() > 0 && current_write_parameters.number_of_bursts_left == 0){
if(wr_ad_channel_queue.size() > 0 && current_write_parameters.number_of_bursts_left == 0 && (order_queue.front() == 1)){
current_write_parameters.address = wr_ad_channel_queue.front().awaddr;
current_write_parameters.number_of_bursts_left = wr_ad_channel_queue.front().awlen +1;
current_write_parameters.delay_cycles_left = write_distribution(generator);

3
test_benches/verilator/AXI_DDR_simulation/axi_ddr_sim.h
View file

@ -105,7 +105,8 @@ struct addr_calculation_parameters{
queue<AXI_write_data_channel_signals> w_data_channel_queue;
//Write Response Queue
queue<AXI_write_response_channel_signals> w_res_channel_queue;
//Order Queue
queue<int> order_queue;
unsigned starting_location = 0x80000000;
};

4
test_benches/verilator/CVA5Tracer.cc
View file

@ -132,7 +132,7 @@ void CVA5Tracer::tick() {
update_UART();
update_memory();
#ifdef TRACE_ON
#ifdef PC_TRACE_ON
for (int i =0; i < tb->NUM_RETIRE_PORTS; i++) {
if (logPC && tb->retire_ports_valid[i]) {
*pcFile << std::hex << tb->retire_ports_pc[i] << std::endl;
@ -145,7 +145,7 @@ void CVA5Tracer::tick() {
void CVA5Tracer::start_tracer(const char *trace_file) {
#ifdef TRACE_ON
verilatorWaveformTracer = new VerilatedVcdC;
verilatorWaveformTracer = new VerilatedFstC;
tb->trace(verilatorWaveformTracer, 99);
verilatorWaveformTracer->open(trace_file);
#endif

4
test_benches/verilator/CVA5Tracer.h
View file

@ -26,7 +26,7 @@
#include <iostream>
#include <iterator>
#include "verilated.h"
#include "verilated_vcd_c.h"
#include "verilated_fst_c.h"
#include "Vcva5_sim.h"
#include "SimMem.h"
#include "AXI_DDR_simulation/axi_ddr_sim.h"
@ -62,7 +62,7 @@ private:
axi_ddr_sim * axi_ddr;
SimMem *mem;
#ifdef TRACE_ON
VerilatedVcdC *verilatorWaveformTracer;
VerilatedFstC *verilatorWaveformTracer;
#endif
std::ofstream* logFile;
std::ofstream* pcFile;

2
test_benches/verilator/cva5_sim.cc
View file

@ -2,7 +2,7 @@
#include <iostream>
#include <fstream>
#include "verilated.h"
#include "verilated_vcd_c.h"
#include "verilated_fst_c.h"
#include "svdpi.h"
#include "Vcva5_sim__Dpi.h"
#include "Vcva5_sim.h"

8
tools/cva5.mak
View file

@ -26,8 +26,8 @@ DDR_SIZE_GB = 4
PAGE_SIZE_KB = 2
MAX_READ_REQ = 8
MAX_WRITE_REQ = $(MAX_READ_REQ)
MIN_RD_DELAY = 1
MAX_RD_DELAY = 1
MIN_RD_DELAY = 15
MAX_RD_DELAY = 30
MIN_WR_DELAY = 1
MAX_WR_DELAY = 1
DELAY_SEED = 867583
@ -55,7 +55,7 @@ CFLAGS = -g0 -O3 -std=c++14 -march=native -D$(ddr_size_def) -D$(page_size_def) -
################################################################################
VERILATOR_LINT_IGNORE= -Wno-LITENDIAN -Wno-SYMRSVDWORD
ifeq ($(TRACE_ENABLE), True)
VERILATOR_CFLAGS = --trace --trace-structs --CFLAGS "$(CFLAGS) -D TRACE_ON"
VERILATOR_CFLAGS = --trace-fst --trace-structs --CFLAGS "$(CFLAGS) -D TRACE_ON"
else
VERILATOR_CFLAGS = --CFLAGS "$(CFLAGS)"
endif
@ -93,7 +93,7 @@ $(CVA5_SIM): $(CVA5_HW_SRCS) $(CVA5_SIM_SRCS)
-o cva5-sim \
$(VERILATOR_LINT_IGNORE) $(VERILATOR_CFLAGS) \
$(CVA5_SIM_SRCS) \
$(CVA5_HW_SRCS) $(CVA5_DIR)/test_benches/sim_stats.sv $(VERILATOR_DIR)/cva5_sim.sv --top-module cva5_sim
$(CVA5_HW_SRCS) $(CVA5_DIR)/test_benches/sim_stats.sv $(CVA5_DIR)/test_benches/verilator/cva5_sim.sv --top-module cva5_sim
$(MAKE) -C $(CVA5_SIM_DIR) -f Vcva5_sim.mk
.PHONY: clean-cva5-sim