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Added support for additional CSRs

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This commit is contained in:
Eric Matthews 2020-08-13 16:44:27 -07:00
parent eeeb0cc1c0
commit 525918e6b6
2 changed files with 18 additions and 3 deletions
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17
core/csr_regs.sv
View file

@ -497,9 +497,9 @@ endgenerate
end
end
always_comb begin
always_comb begin
invalid_addr = 0;
case(csr_addr)
case (csr_addr) inside
//Machine info
MISA : selected_csr = ENABLE_M_MODE ? misa : 0;
MVENDORID : selected_csr = ENABLE_M_MODE ? mvendorid : 0;
@ -512,17 +512,24 @@ endgenerate
MIDELEG : selected_csr = ENABLE_M_MODE ? mideleg : 0;
MIE : selected_csr = ENABLE_M_MODE ? mie_reg : 0;
MTVEC : selected_csr = ENABLE_M_MODE ? mtvec : 0;
MCOUNTEREN : selected_csr = 0;
//Machine trap handling
MSCRATCH : selected_csr = ENABLE_M_MODE ? scratch_out : 0;
MEPC : selected_csr = ENABLE_M_MODE ? mepc : 0;
MCAUSE : selected_csr = ENABLE_M_MODE ? mcause : 0;
MTVAL : selected_csr = ENABLE_M_MODE ? mtval : 0;
MIP : selected_csr = ENABLE_M_MODE ? mip : 0;
//Machine Memory Protection
[12'h3EF : 12'h3A0] : selected_csr = 0;
//Machine Timers and Counters
MCYCLE : selected_csr = ENABLE_M_MODE ? mcycle[XLEN-1:0] : 0;
MINSTRET : selected_csr = ENABLE_M_MODE ? minst_ret[XLEN-1:0] : 0;
[12'hB03 : 12'hB1F] : selected_csr = 0;
MCYCLEH : selected_csr = ENABLE_M_MODE ? 32'(mcycle[COUNTER_W-1:XLEN]) : 0;
MINSTRETH : selected_csr = ENABLE_M_MODE ? 32'(minst_ret[COUNTER_W-1:XLEN]) : 0;
[12'hB83 : 12'hB9F] : selected_csr = 0;
//Machine Counter Setup
[12'h320 : 12'h33F] : selected_csr = 0;
//Supervisor Trap Setup
SSTATUS : selected_csr = ENABLE_S_MODE ? (mstatus & sstatus_mask) : '0;
@ -530,6 +537,7 @@ endgenerate
SIDELEG : selected_csr = 0;
SIE : selected_csr = ENABLE_S_MODE ? (mie_reg & sie_mask) : '0;
STVEC : selected_csr = ENABLE_S_MODE ? stvec : '0;
SCOUNTEREN : selected_csr = 0;
//Supervisor trap handling
SSCRATCH : selected_csr = ENABLE_S_MODE ? scratch_out : '0;
SEPC : selected_csr = ENABLE_S_MODE ? scratch_out : '0;
@ -541,13 +549,18 @@ endgenerate
//User status
//Floating point
FFLAGS : selected_csr = 0;
FRM : selected_csr = 0;
FCSR : selected_csr = 0;
//User Counter Timers
CYCLE : selected_csr = mcycle[XLEN-1:0];
TIME : selected_csr = mcycle[XLEN-1:0];
INSTRET : selected_csr = minst_ret[XLEN-1:0];
[12'hC03 : 12'hC1F] : selected_csr = 0;
CYCLEH : selected_csr = 32'(mcycle[COUNTER_W-1:XLEN]);
TIMEH : selected_csr = 32'(mcycle[COUNTER_W-1:XLEN]);
INSTRETH : selected_csr = 32'(minst_ret[COUNTER_W-1:XLEN]);
[12'hC83 : 12'hC9F] : selected_csr = 0;
default : begin selected_csr = 0; invalid_addr = 1; end
endcase

4
core/riscv_types.sv
View file

@ -128,6 +128,7 @@ package riscv_types;
MIDELEG = 12'h303,
MIE = 12'h304,
MTVEC = 12'h305,
MCOUNTEREN = 12'h306,
//Machine trap handling
MSCRATCH = 12'h340,
MEPC = 12'h341,
@ -135,6 +136,7 @@ package riscv_types;
MTVAL = 12'h343,
MIP = 12'h344,
//Machine Counters
MCYCLE = 12'hB00,
MINSTRET = 12'hB02,
@ -148,7 +150,7 @@ package riscv_types;
SIDELEG = 12'h103,
SIE = 12'h104,
STVEC = 12'h105,
SCOUNTEREN = 12'h106,
//Supervisor trap handling
SSCRATCH = 12'h140,
SEPC = 12'h141,