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Instruction and Data Cache reorganization and cleanup
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
This commit is contained in:
Eric Matthews
parent
6aeac17b9d
commit
562a9c2ff6
4 changed files with 135 additions and 138 deletions
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@ -100,12 +100,11 @@ module dcache
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logic hit_allowed;
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logic read_hit_allowed;
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logic read_hit_data_valid;
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logic read_hit;
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logic address_range_valid;
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logic idle;
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logic busy;
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logic read_miss_complete;
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logic store_complete;
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@ -136,7 +135,6 @@ module dcache
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//Signal is valid for a single cycle, RAM enables are used to hold outputs in case of pipeline stalls
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always_ff @ (posedge clk) begin
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read_hit_allowed <= ls.new_request & ls.re & dcache_on & ~(amo.is_lr | amo.is_amo) & ~uncacheable;
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read_hit_data_valid <= read_hit_allowed;
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second_cycle <= ls.new_request;
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tag_update <= second_cycle & dcache_on & stage2.load & ~tag_hit & ~stage2.uncacheable;//Cache enabled, read miss
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end
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@ -144,14 +142,11 @@ module dcache
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assign read_hit = tag_hit & read_hit_allowed;
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//LR reservation, cleared on exceptions
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always_ff @ (posedge clk) begin
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if (rst)
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reservation <= 0;
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else if (second_cycle)
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reservation <= stage2.amo.is_lr;
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else if (sc_complete | clear_reservation)
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reservation <= 0;
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else
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reservation <= (reservation & ~(sc_complete | clear_reservation)) | (second_cycle & stage2.amo.is_lr);
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end
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////////////////////////////////////////////////////
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@ -165,10 +160,10 @@ module dcache
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assign l1_request.amo = stage2.amo.op;
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always_ff @ (posedge clk) begin
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if (rst | line_complete)
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if (ls.new_request)
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word_count <= 0;
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else if (l1_response.data_valid)
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word_count <= word_count + 1;
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else
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word_count <= word_count + SCONFIG.SUB_LINE_ADDR_W'(l1_response.data_valid);
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end
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assign is_target_word = (stage2.addr[SCONFIG.SUB_LINE_ADDR_W-1:0] == word_count) | stage2.uncacheable;
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@ -176,32 +171,30 @@ module dcache
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always_ff @ (posedge clk) begin
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if (rst)
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arb_request_r <= 0;
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else if (second_cycle & ~l1_request.ack)
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arb_request_r <= new_arb_request;
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else if (l1_request.ack)
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arb_request_r <= 0;
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else
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arb_request_r <= (arb_request_r | new_arb_request) & ~l1_request.ack;
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end
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assign l1_request.request = new_arb_request | arb_request_r;
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////////////////////////////////////////////////////
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//Replacement policy (free runing one-hot cycler, i.e. pseudo random)
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cycler #(CONFIG.DCACHE.WAYS) replacement_policy (
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.clk (clk),
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.rst (rst),
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.en (1'b1),
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.one_hot (replacement_way)
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.clk (clk),
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.rst (rst),
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.en (1'b1),
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.one_hot (replacement_way)
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);
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//One-hot tag hit / update logic to binary int
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one_hot_to_integer #(CONFIG.DCACHE.WAYS)
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hit_way_conv (
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.one_hot(tag_hit_way),
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.int_out(tag_hit_way_int)
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.one_hot (tag_hit_way),
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.int_out (tag_hit_way_int)
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);
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one_hot_to_integer #(CONFIG.DCACHE.WAYS)
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update_way_conv (
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.one_hot (replacement_way),
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.int_out (replacement_way_int)
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.one_hot (replacement_way),
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.int_out (replacement_way_int)
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);
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@ -252,9 +245,9 @@ module dcache
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endgenerate
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always_comb begin
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if (stage2.amo.is_amo & is_target_word)
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if (CONFIG.INCLUDE_AMO & stage2.amo.is_amo & is_target_word)
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new_line_data = amo_result;
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else if (stage2.amo.is_sc)
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else if (CONFIG.INCLUDE_AMO & stage2.amo.is_sc)
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new_line_data = stage2.data;
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else
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new_line_data = l1_response.data;
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@ -278,28 +271,27 @@ module dcache
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assign data_bank_addr_b = {tag_update_way_int, stage2.addr[SCONFIG.LINE_ADDR_W+SCONFIG.SUB_LINE_ADDR_W-1:SCONFIG.SUB_LINE_ADDR_W], update_word_index};
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end endgenerate
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ddata_bank #(.LINES(DCACHE_SIZE_IN_WORDS)) data_bank (
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.clk(clk),
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.addr_a(data_bank_addr_a),
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.addr_b(data_bank_addr_b),
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.en_a(second_cycle),
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.en_b((l1_response.data_valid & ~stage2.uncacheable) | (sc_complete & sc_success)),
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.be_a(write_hit_be),
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.data_in_a(stage2.data),
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.data_in_b(new_line_data),
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.data_out_a(dbank_data_out)
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);
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ddata_bank #(.LINES(DCACHE_SIZE_IN_WORDS))
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data_bank (
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.clk(clk),
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.addr_a(data_bank_addr_a),
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.addr_b(data_bank_addr_b),
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.en_a(second_cycle),
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.en_b((l1_response.data_valid & ~stage2.uncacheable) | (sc_complete & sc_success)),
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.be_a(write_hit_be),
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.data_in_a(stage2.data),
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.data_in_b(new_line_data),
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.data_out_a(dbank_data_out)
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);
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////////////////////////////////////////////////////
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//Output
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logic l1_data_valid_r;
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always_ff @ (posedge clk) begin
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if (l1_response.data_valid & is_target_word)
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miss_data <= l1_response.data;
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else if (sc_complete)
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miss_data <= {31'b0, sc_success};
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l1_data_valid_r <= l1_response.data_valid;
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miss_data <= sc_complete ? {31'b0, sc_success} : l1_response.data;
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end
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assign ls.data_out = read_hit_data_valid ? dbank_data_out : miss_data;
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assign ls.data_out = l1_data_valid_r ? miss_data : dbank_data_out;
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////////////////////////////////////////////////////
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//Pipeline Advancement
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@ -321,15 +313,13 @@ module dcache
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ls.data_valid <= (l1_response.data_valid & is_target_word) | read_hit | sc_complete;
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end
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assign ls.ready = read_hit | store_complete | read_miss_complete | idle;
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assign ls.ready = read_hit | store_complete | read_miss_complete | ~busy;
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always_ff @ (posedge clk) begin
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if (rst)
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idle <= 1;
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else if (ls.new_request)
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idle <= 0;
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else if (ls.ready)
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idle <= 1;
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busy <= 0;
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else
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busy <= (busy & ~ls.ready) | ls.new_request;
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end
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////////////////////////////////////////////////////
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144
core/icache.sv
144
core/icache.sv
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@ -42,6 +42,7 @@ module icache
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);
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localparam derived_cache_config_t SCONFIG = get_derived_cache_params(CONFIG, CONFIG.ICACHE, CONFIG.ICACHE_ADDR);
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localparam bit [SCONFIG.SUB_LINE_ADDR_W-1:0] END_OF_LINE_COUNT = SCONFIG.SUB_LINE_ADDR_W'(CONFIG.ICACHE.LINE_W-1);
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logic tag_hit;
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logic [CONFIG.ICACHE.WAYS-1:0] tag_hit_way;
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@ -51,20 +52,24 @@ module icache
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logic [CONFIG.ICACHE.WAYS-1:0] tag_update_way;
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logic [SCONFIG.SUB_LINE_ADDR_W-1:0] word_count;
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logic [SCONFIG.SUB_LINE_ADDR_W-1:0] target_word;
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logic is_target_word;
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logic line_complete;
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logic [31:0] data_out [CONFIG.ICACHE.WAYS-1:0];
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logic [31:0] miss_data;
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logic miss_in_progress;
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logic linefill_in_progress;
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logic request_in_progress;
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logic miss_data_valid;
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logic second_cycle;
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logic [31:0] second_cycle_addr;
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logic idle;
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logic memory_complete;
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fifo_interface #(.DATA_WIDTH(32)) input_fifo();
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logic new_request;
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logic [31:0] new_request_addr;
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////////////////////////////////////////////////////
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//Implementation
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@ -72,18 +77,44 @@ module icache
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//On the second cycle of a request hit/miss determination is performed
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//On a miss, the memory request starts on the third cycle
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assign new_request = (fetch_sub.new_request | input_fifo.valid) & ((~request_in_progress | tag_hit) & ~linefill_in_progress);
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assign input_fifo.push = fetch_sub.new_request & (~new_request | input_fifo.valid);
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assign input_fifo.potential_push = input_fifo.push;
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assign input_fifo.pop = new_request & input_fifo.valid;
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assign input_fifo.data_in = fetch_sub.addr;
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assign new_request_addr = input_fifo.valid ? input_fifo.data_out : fetch_sub.addr;
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cva5_fifo #(.DATA_WIDTH(32), .FIFO_DEPTH(2))
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cache_input_fifo (
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.clk (clk),
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.rst (rst),
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.fifo (input_fifo)
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);
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////////////////////////////////////////////////////
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//Ready determination
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always_ff @ (posedge clk) begin
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if (rst)
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request_in_progress <= 0;
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else
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request_in_progress <= (request_in_progress & ~fetch_sub.data_valid) | new_request;
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end
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assign fetch_sub.ready = ~input_fifo.full;
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////////////////////////////////////////////////////
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//General Control Logic
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always_ff @ (posedge clk) begin
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if (rst)
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second_cycle <= 0;
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else
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second_cycle <= fetch_sub.new_request;
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second_cycle <= new_request;
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end
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always_ff @(posedge clk) begin
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if (fetch_sub.new_request)
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second_cycle_addr <= fetch_sub.addr;
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if (new_request)
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second_cycle_addr <= new_request_addr;
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end
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//As request can be aborted on any cycle, only update tags if memory request is in progress
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@ -96,13 +127,13 @@ module icache
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//Replacement policy is psuedo random
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cycler #(CONFIG.ICACHE.WAYS) replacement_policy (
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.clk (clk),
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.rst (rst),
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.en (1'b1),
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.one_hot (replacement_way)
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.clk (clk),
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.rst (rst),
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.en (1'b1),
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.one_hot (replacement_way)
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);
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always_ff @ (posedge clk) begin
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if (second_cycle)
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if (second_cycle & ~linefill_in_progress)
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tag_update_way <= replacement_way;
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end
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@ -132,24 +163,24 @@ module icache
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//Miss state tracking
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always_ff @ (posedge clk) begin
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if (rst)
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miss_in_progress <= 0;
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linefill_in_progress <= 0;
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else
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miss_in_progress <= l1_request.ack | (miss_in_progress & ~line_complete);
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linefill_in_progress <= (linefill_in_progress & ~line_complete) | l1_request.ack;
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end
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////////////////////////////////////////////////////
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//Tag banks
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itag_banks #(.CONFIG(CONFIG), .SCONFIG(SCONFIG))
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icache_tag_banks (
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.clk(clk),
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.rst(rst), //clears the read_hit_allowed flag
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.stage1_addr(fetch_sub.addr),
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.stage2_addr(second_cycle_addr),
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.update_way(tag_update_way),
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.update(tag_update),
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.stage1_adv(fetch_sub.new_request & icache_on),
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.tag_hit(tag_hit),
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.tag_hit_way(tag_hit_way)
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.clk(clk),
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.rst(rst), //clears the read_hit_allowed flag
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.stage1_addr(new_request_addr),
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.stage2_addr(second_cycle_addr),
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.update_way(tag_update_way),
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.update(tag_update),
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.stage1_adv(new_request & icache_on),
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.tag_hit(tag_hit),
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.tag_hit_way(tag_hit_way)
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);
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////////////////////////////////////////////////////
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@ -158,9 +189,9 @@ module icache
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generate for (i=0; i < CONFIG.ICACHE.WAYS; i++) begin : idata_bank_gen
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byte_en_BRAM #(CONFIG.ICACHE.LINES*CONFIG.ICACHE.LINE_W) idata_bank (
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.clk(clk),
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.addr_a(fetch_sub.addr[2 +: SCONFIG.LINE_ADDR_W+SCONFIG.SUB_LINE_ADDR_W]),
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.addr_a(new_request_addr[2 +: SCONFIG.LINE_ADDR_W+SCONFIG.SUB_LINE_ADDR_W]),
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.addr_b({second_cycle_addr[(2+SCONFIG.SUB_LINE_ADDR_W) +: SCONFIG.LINE_ADDR_W], word_count}),
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.en_a(fetch_sub.new_request),
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.en_a(new_request),
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.en_b(tag_update_way[i] & l1_response.data_valid),
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.be_a('0),
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.be_b('1),
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@ -173,61 +204,42 @@ module icache
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////////////////////////////////////////////////////
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//Miss data path
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assign target_word = second_cycle_addr[2 +: SCONFIG.SUB_LINE_ADDR_W];
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assign is_target_word = (target_word == word_count);
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always_ff @ (posedge clk) begin
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if (rst)
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word_count <= 0;
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else if (l1_response.data_valid)
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word_count <= word_count + 1;
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end
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assign is_target_word = (second_cycle_addr[2 +: SCONFIG.SUB_LINE_ADDR_W] == word_count);
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always_ff @ (posedge clk) begin
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if (l1_response.data_valid & is_target_word)
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miss_data <= l1_response.data;
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else
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miss_data <= 0;
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word_count <= word_count + SCONFIG.SUB_LINE_ADDR_W'(l1_response.data_valid);
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end
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always_ff @ (posedge clk) begin
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if (rst)
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miss_data_valid <= 0;
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else
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miss_data_valid <= miss_in_progress & l1_response.data_valid & is_target_word;
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end
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assign line_complete = (l1_response.data_valid && (word_count == SCONFIG.SUB_LINE_ADDR_W'(CONFIG.ICACHE.LINE_W-1)));
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always_ff @ (posedge clk) begin
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if (rst)
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memory_complete <= 0;
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else
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memory_complete <= line_complete;
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end
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assign miss_data_valid = request_in_progress & l1_response.data_valid & is_target_word;
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assign line_complete = l1_response.data_valid & (word_count == END_OF_LINE_COUNT);
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////////////////////////////////////////////////////
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//Output muxing
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localparam OMUX_W = CONFIG.ICACHE.WAYS+1;
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logic [OMUX_W-1:0] priority_vector;
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logic [$clog2(OMUX_W)-1:0] output_sel;
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logic [31:0] output_array [OMUX_W];
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always_comb begin
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fetch_sub.data_out = miss_data;//zero if not a miss
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priority_vector[0] = miss_data_valid;
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output_array[0] = l1_response.data;
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for (int i = 0; i < CONFIG.ICACHE.WAYS; i++) begin
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fetch_sub.data_out = fetch_sub.data_out | (data_out[i] & {32{tag_hit_way[i]}});
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priority_vector[i+1] = tag_hit_way[i];
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output_array[i+1] = data_out[i];
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end
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end
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priority_encoder #(.WIDTH(OMUX_W))
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arb_encoder
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(
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.priority_vector (priority_vector),
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.encoded_result (output_sel)
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);
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assign fetch_sub.data_out = output_array[output_sel];
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assign fetch_sub.data_valid = miss_data_valid | tag_hit;
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////////////////////////////////////////////////////
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//Ready determination
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always_ff @ (posedge clk) begin
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if (rst)
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idle <= 1;
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else if (fetch_sub.new_request)
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idle <= 0;
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else if (memory_complete | tag_hit) //read miss OR write through complete
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idle <= 1;
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end
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assign fetch_sub.ready = tag_hit | memory_complete | idle;
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////////////////////////////////////////////////////
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//End of Implementation
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////////////////////////////////////////////////////
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@ -239,7 +251,7 @@ module icache
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else $error("Spurious icache ack received from arbiter!");
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icache_l1_arb_data_valid_assertion:
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assert property (@(posedge clk) disable iff (rst) l1_response.data_valid |-> miss_in_progress)
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assert property (@(posedge clk) disable iff (rst) l1_response.data_valid |-> linefill_in_progress)
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else $error("Spurious icache data received from arbiter!");
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endmodule
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@ -198,12 +198,12 @@ interface load_store_queue_interface;
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lsq_entry_t data_in;
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logic potential_push;
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logic push;
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logic full;
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logic pop;
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//LSQ outputs
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data_access_shared_inputs_t data_out;
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logic valid;
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logic pop;
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logic full;
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//LSQ status
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||||
logic sq_empty;
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@ -228,12 +228,11 @@ interface store_queue_interface;
|
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//Issue inputs
|
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lsq_entry_t data_in;
|
||||
logic push;
|
||||
logic full;
|
||||
logic pop;
|
||||
|
||||
sq_entry_t data_out;
|
||||
|
||||
logic valid;
|
||||
logic pop;
|
||||
logic full;
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||||
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||||
//SQ status
|
||||
logic empty;
|
||||
|
|
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|||
|
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@ -50,7 +50,7 @@ module l1_arbiter
|
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logic [L1_CONNECTIONS-1:0] acks;
|
||||
logic [((L1_CONNECTIONS == 1) ? 0 : ($clog2(L1_CONNECTIONS)-1)) : 0] arb_sel;
|
||||
|
||||
logic push_ready;
|
||||
logic fifos_full;
|
||||
logic request_exists;
|
||||
////////////////////////////////////////////////////
|
||||
//Implementation
|
||||
|
|
@ -69,14 +69,14 @@ module l1_arbiter
|
|||
assign sc_success = CONFIG.INCLUDE_AMO & l2.con_result;
|
||||
|
||||
//Arbiter can pop address FIFO at a different rate than the data FIFO, so check that both have space.
|
||||
assign push_ready = ~(l2.request_full | l2.data_full);
|
||||
assign fifos_full = l2.request_full | l2.data_full;
|
||||
assign request_exists = |requests;
|
||||
|
||||
assign l2.request_push = push_ready & request_exists;
|
||||
assign l2.request_push = request_exists & ~fifos_full;
|
||||
|
||||
////////////////////////////////////////////////////
|
||||
//Dcache Specific
|
||||
assign l2.wr_data_push = CONFIG.INCLUDE_DCACHE & (push_ready & l1_request[L1_DCACHE_ID].request & ~l1_request[L1_DCACHE_ID].rnw); //Assumes data cache has highest priority
|
||||
assign l2.wr_data_push = CONFIG.INCLUDE_DCACHE & (l1_request[L1_DCACHE_ID].request & ~l1_request[L1_DCACHE_ID].rnw & ~fifos_full); //Assumes data cache has highest priority
|
||||
assign l2.wr_data = l1_request[L1_DCACHE_ID].data;
|
||||
|
||||
assign l2.inv_ack = CONFIG.DCACHE.USE_EXTERNAL_INVALIDATIONS ? l1_response[L1_DCACHE_ID].inv_ack : l2.inv_valid;
|
||||
|
|
@ -86,30 +86,26 @@ module l1_arbiter
|
|||
////////////////////////////////////////////////////
|
||||
//Interface mapping
|
||||
generate for (genvar i = 0; i < L1_CONNECTIONS; i++) begin : gen_l2_requests
|
||||
always_comb begin
|
||||
l2_requests[i].addr = l1_request[i].addr[31:2];
|
||||
l2_requests[i].rnw = l1_request[i].rnw;
|
||||
l2_requests[i].be = l1_request[i].be;
|
||||
l2_requests[i].is_amo = l1_request[i].is_amo;
|
||||
l2_requests[i].amo_type_or_burst_size = l1_request[i].size;
|
||||
l2_requests[i].sub_id = L2_SUB_ID_W'(i);
|
||||
end
|
||||
assign l2_requests[i] = '{
|
||||
addr : l1_request[i].addr[31:2],
|
||||
rnw : l1_request[i].rnw,
|
||||
be : l1_request[i].be,
|
||||
is_amo : l1_request[i].is_amo,
|
||||
amo_type_or_burst_size : l1_request[i].size,
|
||||
sub_id : L2_SUB_ID_W'(i)
|
||||
};
|
||||
end endgenerate
|
||||
|
||||
////////////////////////////////////////////////////
|
||||
//Arbitration
|
||||
priority_encoder
|
||||
#(.WIDTH(L1_CONNECTIONS))
|
||||
priority_encoder #(.WIDTH(L1_CONNECTIONS))
|
||||
arb_encoder
|
||||
(
|
||||
.priority_vector (requests),
|
||||
.encoded_result (arb_sel)
|
||||
);
|
||||
|
||||
always_comb begin
|
||||
acks = '0;
|
||||
acks[arb_sel] = l2.request_push;
|
||||
end
|
||||
assign acks = L1_CONNECTIONS'(l2.request_push) << arb_sel;
|
||||
|
||||
assign l2.addr = l2_requests[arb_sel].addr;
|
||||
assign l2.rnw = l2_requests[arb_sel].rnw;
|
||||
|
|
@ -120,7 +116,7 @@ module l1_arbiter
|
|||
|
||||
generate for (genvar i = 0; i < L1_CONNECTIONS; i++) begin : gen_l1_responses
|
||||
assign l1_response[i].data = l2.rd_data;
|
||||
assign l1_response[i].data_valid = l2.rd_data_valid && (l2.rd_sub_id == i);
|
||||
assign l1_response[i].data_valid = l2.rd_data_valid & (l2.rd_sub_id == i);
|
||||
end endgenerate
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue