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unit wb renaming
This commit is contained in:
Eric Matthews
parent
184aad14c8
commit
5f2dfd21db
7 changed files with 64 additions and 68 deletions
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@ -84,7 +84,7 @@ module alu_unit(
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//Output
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assign issue.ready = 1;
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assign wb.rd = result;
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assign wb.done_next_cycle = issue.new_request;
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assign wb.done = issue.new_request;
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assign wb.id = issue.instruction_id;
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////////////////////////////////////////////////////
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@ -118,7 +118,7 @@ module div_unit
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////////////////////////////////////////////////////
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//Output
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assign wb.rd = wb_div_result;
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assign wb.done_next_cycle = div_done;
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assign wb.done = div_done;
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assign wb.id = stage1.instruction_id;
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////////////////////////////////////////////////////
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//Assertions
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@ -327,7 +327,7 @@ module load_store_unit (
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end
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assign ls_done = load_complete | exception_complete | store_complete;
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assign wb.done_next_cycle = csr_done | ls_done;
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assign wb.done = csr_done | ls_done;
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assign wb.id = csr_done ? csr_id : stage2_attr.instruction_id;
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////////////////////////////////////////////////////
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//End of Implementation
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@ -34,7 +34,7 @@ module mul_unit(
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logic signed [65:0] result;
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logic [1:0] mulh;
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logic [1:0] done_next_cycle;
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logic [1:0] done;
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instruction_id_t id [1:0];
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logic rs1_signed, rs2_signed;
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@ -63,15 +63,15 @@ module mul_unit(
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id[0] <= issue.instruction_id;
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id[1] <= id[0];
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done_next_cycle[0] <= issue.new_request;
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done_next_cycle[1] <= done_next_cycle[0];
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done[0] <= issue.new_request;
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done[1] <= done[0];
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end
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//Issue/write-back handshaking
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////////////////////////////////////////////////////
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assign issue.ready = 1;
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assign wb.rd = mulh[1] ? result[63:32] : result[31:0];
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assign wb.done_next_cycle = done_next_cycle[1];
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assign wb.done = done[1];
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assign wb.id = id[1];
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////////////////////////////////////////////////////
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//End of Implementation
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@ -28,7 +28,6 @@ package taiga_types;
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parameter ECODE_W = 5;
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typedef logic[$clog2(MAX_INFLIGHT_COUNT)-1:0] instruction_id_t;
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typedef logic[MAX_INFLIGHT_COUNT-1:0] instruction_id_one_hot_t;
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typedef logic[$clog2(NUM_WB_UNITS)-1:0] unit_id_t;
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typedef logic[1:0] branch_predictor_metadata_t;
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@ -297,7 +296,7 @@ package taiga_types;
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typedef struct packed{
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instruction_id_t id;
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logic done_next_cycle;
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logic done;
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logic [XLEN-1:0] rd;
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} unit_writeback_t;
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@ -376,7 +375,6 @@ package taiga_types;
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logic load;
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logic store;
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logic load_store_forward;
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instruction_id_one_hot_t instruction_id_one_hot;
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instruction_id_t instruction_id;
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//exception support
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logic [31:0] pc;
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@ -395,7 +393,6 @@ package taiga_types;
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logic [XLEN-1:0] rs2;
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logic [1:0] op;
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logic reuse_result;
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instruction_id_one_hot_t instruction_id_one_hot;
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instruction_id_t instruction_id;
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} div_inputs_t;
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@ -46,7 +46,7 @@ module write_back(
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//aliases for write-back-interface signals
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instruction_id_t unit_instruction_id [NUM_WB_UNITS-1:0];
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logic [NUM_WB_UNITS-1:0] unit_done_next_cycle;
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logic [NUM_WB_UNITS-1:0] unit_done;
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logic [XLEN-1:0] unit_rd [NUM_WB_UNITS-1:0];
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/////
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@ -70,7 +70,7 @@ module write_back(
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generate
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for (i=0; i< NUM_WB_UNITS; i++) begin : interface_to_array_g
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assign unit_instruction_id[i] = unit_wb[i].id;
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assign unit_done_next_cycle[i] = unit_wb[i].done_next_cycle;
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assign unit_done[i] = unit_wb[i].done;
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assign unit_rd[i] = unit_wb[i].rd;
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end
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endgenerate
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@ -80,7 +80,7 @@ module write_back(
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id_done_new[i] = 0;
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id_unit_select[i] = 0;
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for (int j=0; j< NUM_WB_UNITS; j++) begin
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if (unit_done_next_cycle[j] && (unit_instruction_id[j] == i[$clog2(MAX_INFLIGHT_COUNT)-1:0])) begin
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if (unit_done[j] && (unit_instruction_id[j] == i[$clog2(MAX_INFLIGHT_COUNT)-1:0])) begin
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id_unit_select[i] = j[$clog2(NUM_WB_UNITS)-1:0];
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id_done_new[i] |= 1;
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end
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@ -17,14 +17,14 @@
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</db_ref_list>
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<zoom_setting>
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<ZoomStartTime time="0fs"></ZoomStartTime>
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<ZoomEndTime time="656000000001fs"></ZoomEndTime>
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<Cursor1Time time="338000000000fs"></Cursor1Time>
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<ZoomEndTime time="25150000000001fs"></ZoomEndTime>
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<Cursor1Time time="6590859000000fs"></Cursor1Time>
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</zoom_setting>
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<column_width_setting>
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<NameColumnWidth column_width="259"></NameColumnWidth>
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<ValueColumnWidth column_width="93"></ValueColumnWidth>
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<ValueColumnWidth column_width="252"></ValueColumnWidth>
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</column_width_setting>
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<WVObjectSize size="171" />
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<WVObjectSize size="167" />
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<wvobject type="logic" fp_name="/taiga_full_simulation/clk">
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<obj_property name="ElementShortName">clk</obj_property>
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<obj_property name="ObjectShortName">clk</obj_property>
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@ -81,56 +81,6 @@
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<obj_property name="ElementShortName">mem_valid</obj_property>
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<obj_property name="ObjectShortName">mem_valid</obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/taiga_full_simulation/uut/bp_block/br_results">
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<obj_property name="ElementShortName">br_results</obj_property>
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<obj_property name="ObjectShortName">br_results</obj_property>
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<obj_property name="isExpanded"></obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/taiga_full_simulation/uut/bp_block/if_entry">
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<obj_property name="ElementShortName">if_entry[1:0]</obj_property>
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<obj_property name="ObjectShortName">if_entry[1:0]</obj_property>
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<wvobject type="array" fp_name="/taiga_full_simulation/uut/bp_block/if_entry[1]">
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<obj_property name="ElementShortName">[1]</obj_property>
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<obj_property name="ObjectShortName">[1]</obj_property>
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<obj_property name="isExpanded"></obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/taiga_full_simulation/uut/bp_block/if_entry[0]">
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<obj_property name="ElementShortName">[0]</obj_property>
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<obj_property name="ObjectShortName">[0]</obj_property>
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</wvobject>
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</wvobject>
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<wvobject type="array" fp_name="/taiga_full_simulation/uut/bp_block/ex_entry">
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<obj_property name="ElementShortName">ex_entry</obj_property>
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<obj_property name="ObjectShortName">ex_entry</obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/taiga_full_simulation/uut/bp_block/new_jump_addr">
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<obj_property name="ElementShortName">new_jump_addr[31:0]</obj_property>
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<obj_property name="ObjectShortName">new_jump_addr[31:0]</obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/taiga_full_simulation/uut/bp_block/predicted_pc">
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<obj_property name="ElementShortName">predicted_pc[1:0][31:0]</obj_property>
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<obj_property name="ObjectShortName">predicted_pc[1:0][31:0]</obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/taiga_full_simulation/uut/bp_block/tag_matches">
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<obj_property name="ElementShortName">tag_matches[1:0]</obj_property>
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<obj_property name="ObjectShortName">tag_matches[1:0]</obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/taiga_full_simulation/uut/bp_block/replacement_way">
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<obj_property name="ElementShortName">replacement_way[1:0]</obj_property>
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<obj_property name="ObjectShortName">replacement_way[1:0]</obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/taiga_full_simulation/uut/bp_block/update_way">
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<obj_property name="ElementShortName">update_way[1:0]</obj_property>
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<obj_property name="ObjectShortName">update_way[1:0]</obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/taiga_full_simulation/uut/bp_block/hit_way">
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<obj_property name="ElementShortName">hit_way[0:0]</obj_property>
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<obj_property name="ObjectShortName">hit_way[0:0]</obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/taiga_full_simulation/uut/bp_block/tag_match">
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<obj_property name="ElementShortName">tag_match</obj_property>
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<obj_property name="ObjectShortName">tag_match</obj_property>
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</wvobject>
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<wvobject fp_name="divider7368" type="divider">
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<obj_property name="label">I Cache</obj_property>
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<obj_property name="DisplayName">label</obj_property>
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@ -354,6 +304,55 @@
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<wvobject type="array" fp_name="/taiga_full_simulation/uut/write_back_mux/retired_instruction_packet">
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<obj_property name="ElementShortName">retired_instruction_packet</obj_property>
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<obj_property name="ObjectShortName">retired_instruction_packet</obj_property>
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<wvobject type="array" fp_name="/taiga_full_simulation/uut/write_back_mux/retired_instruction_packet.rd_addr">
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<obj_property name="ElementShortName">.rd_addr[4:0]</obj_property>
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<obj_property name="ObjectShortName">.rd_addr[4:0]</obj_property>
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<obj_property name="isExpanded"></obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/taiga_full_simulation/uut/write_back_mux/retired_instruction_packet.rd_addr_nzero">
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<obj_property name="ElementShortName">.rd_addr_nzero</obj_property>
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<obj_property name="ObjectShortName">.rd_addr_nzero</obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/taiga_full_simulation/uut/write_back_mux/retired_instruction_packet.is_store">
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<obj_property name="ElementShortName">.is_store</obj_property>
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<obj_property name="ObjectShortName">.is_store</obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/taiga_full_simulation/uut/write_back_mux/retired_instruction_packet.rd_addr">
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<obj_property name="ElementShortName">.rd_addr[4:0]</obj_property>
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<obj_property name="ObjectShortName">.rd_addr[4:0]</obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/taiga_full_simulation/uut/write_back_mux/retired_instruction_packet.rd_addr_nzero">
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<obj_property name="ElementShortName">.rd_addr_nzero</obj_property>
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<obj_property name="ObjectShortName">.rd_addr_nzero</obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/taiga_full_simulation/uut/write_back_mux/retired_instruction_packet.is_store">
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<obj_property name="ElementShortName">.is_store</obj_property>
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<obj_property name="ObjectShortName">.is_store</obj_property>
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</wvobject>
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</wvobject>
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<wvobject fp_name="divider4416" type="divider">
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<obj_property name="label">Div Unit</obj_property>
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<obj_property name="DisplayName">label</obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/taiga_full_simulation/uut/\genblk5.div_unit_block /computation_complete">
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<obj_property name="ElementShortName">computation_complete</obj_property>
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<obj_property name="ObjectShortName">computation_complete</obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/taiga_full_simulation/uut/\genblk5.div_unit_block /div_done">
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<obj_property name="ElementShortName">div_done</obj_property>
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<obj_property name="ObjectShortName">div_done</obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/taiga_full_simulation/uut/\genblk5.div_unit_block /start_algorithm">
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<obj_property name="ElementShortName">start_algorithm</obj_property>
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<obj_property name="ObjectShortName">start_algorithm</obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/taiga_full_simulation/uut/\genblk5.div_unit_block /in_progress">
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<obj_property name="ElementShortName">in_progress</obj_property>
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<obj_property name="ObjectShortName">in_progress</obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/taiga_full_simulation/uut/\genblk5.div_unit_block /stage1.reuse_result">
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<obj_property name="ElementShortName">.reuse_result</obj_property>
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<obj_property name="ObjectShortName">.reuse_result</obj_property>
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</wvobject>
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<wvobject fp_name="divider3000" type="divider">
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<obj_property name="label">LS Unit</obj_property>
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