package import refactor

core/addr_hash.sv

@@ -20,11 +20,13 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import riscv_types::*;
-import taiga_types::*;
+module addr_hash 
 
-module addr_hash (
+    import taiga_config::*;
+    import riscv_types::*;
+    import taiga_types::*;
+
+    (
         input logic clk,
         input logic rst,
         input logic [31:0] addr,

core/alu_unit.sv

@@ -20,11 +20,13 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import riscv_types::*;
-import taiga_types::*;
+module alu_unit
 
-module alu_unit(
+    import taiga_config::*;
+    import riscv_types::*;
+    import taiga_types::*;
+
+    (
         input logic clk,
         input logic rst,
         unit_issue_interface.unit issue,

core/amo_alu.sv

@@ -20,14 +20,16 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import riscv_types::*;
-import taiga_types::*;
+module amo_alu
 
-module amo_alu(
+    import taiga_config::*;
+    import riscv_types::*;
+    import taiga_types::*;
+
+    (
         input amo_alu_inputs_t amo_alu_inputs,
         output logic[31:0] result
-        );
+    );
 
     logic rs1_smaller_than_rs2;
      logic signed [32:0] rs1_ext;

core/avalon_master.sv

@@ -20,12 +20,13 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import riscv_types::*;
-import taiga_types::*;
-
 module avalon_master
-        (
+
+    import taiga_config::*;
+    import riscv_types::*;
+    import taiga_types::*;
+
+    (
         input logic clk,
         input logic rst,
 
@@ -35,7 +36,7 @@ module avalon_master
         input data_access_shared_inputs_t ls_inputs,
         ls_sub_unit_interface.sub_unit ls
 
-        );
+    );
     //implementation
     ////////////////////////////////////////////////////
 

core/axi_master.sv

@@ -20,12 +20,13 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import riscv_types::*;
-import taiga_types::*;
-
 module axi_master
-        (
+
+    import taiga_config::*;
+    import riscv_types::*;
+    import taiga_types::*;
+
+    (
         input logic clk,
         input logic rst,
 
@@ -36,7 +37,7 @@ module axi_master
         input data_access_shared_inputs_t ls_inputs,
         ls_sub_unit_interface.sub_unit ls
 
-        );
+    );
     logic ready;
 
 

core/axi_to_arb.sv

@@ -20,14 +20,14 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import riscv_types::*;
-import taiga_types::*;
-import l2_config_and_types::*;
-
-
 module axi_to_arb
-        (
+
+    import taiga_config::*;
+    import riscv_types::*;
+    import taiga_types::*;
+    import l2_config_and_types::*;
+
+    (
         input logic clk,
         input logic rst,
 
@@ -73,12 +73,10 @@ module axi_to_arb
         input logic axi_bvalid,
         input logic [1:0] axi_bresp,
 
-
-
         //arb interface
         l2_memory_interface.slave l2
 
-        );
+    );
 
     logic pop_request;
 

core/barrel_shifter.sv

@@ -20,11 +20,13 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import riscv_types::*;
-import taiga_types::*;
+module barrel_shifter
 
-module barrel_shifter (
+    import taiga_config::*;
+    import riscv_types::*;
+    import taiga_types::*;
+    
+    (
         input logic[31:0] shifter_input,
         input logic[4:0] shift_amount,
         input logic arith,

core/binary_occupancy.sv

@@ -20,11 +20,13 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import taiga_types::*;
+module binary_occupancy
 
-module binary_occupancy #(parameter DEPTH = 4)
-        (
+    import taiga_config::*;
+    import taiga_types::*;
+    
+    #(parameter DEPTH = 4)
+    (
         input logic clk,
         input logic rst,
         input logic push,
@@ -34,7 +36,7 @@ module binary_occupancy #(parameter DEPTH = 4)
         output logic empty,
         output logic almost_empty,
         output logic valid
-        );
+    );
 
     logic[$clog2(DEPTH)-1:0] count;
 

core/branch_comparator.sv

@@ -20,18 +20,20 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import riscv_types::*;
-import taiga_types::*;
+module branch_comparator
 
-module branch_comparator(
-            input logic use_signed,
-            input logic less_than,
-            input logic [31:0] a,
-            input logic [31:0] b,
-            input logic xor_result,
-            output logic result
-        );
+    import taiga_config::*;
+    import riscv_types::*;
+    import taiga_types::*;
+
+    (
+        input logic use_signed,
+        input logic less_than,
+        input logic [31:0] a,
+        input logic [31:0] b,
+        input logic xor_result,
+        output logic result
+    );
 
     logic [32:0] sign_extended_a;
     logic [32:0] sign_extended_b;

core/branch_predictor.sv

@@ -20,18 +20,20 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import riscv_types::*;
-import taiga_types::*;
+module branch_predictor
 
-module branch_predictor (
+    import taiga_config::*;
+    import riscv_types::*;
+    import taiga_types::*;
+
+    (
         input logic clk,
         input logic rst,
         branch_predictor_interface.branch_predictor bp,
         output branch_metadata_t branch_metadata_if,
         input branch_metadata_t branch_metadata_ex,
         input branch_results_t br_results
-        );
+    );
 
     //BP tag width can be reduced, based on memory size, when virtual address
     //support is not enabled

core/branch_predictor_ram.sv

@@ -20,15 +20,16 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import taiga_types::*;
-
 module branch_predictor_ram
-        #(
+
+    import taiga_config::*;
+    import taiga_types::*;
+
+    #(
         parameter C_DATA_WIDTH = 20,
         parameter C_DEPTH = 512
-        )
-        (
+    )
+    (
         input logic clk,
         input logic rst,
         input logic [$clog2(C_DEPTH)-1:0] write_addr,
@@ -37,7 +38,7 @@ module branch_predictor_ram
         input logic read_en,
         input logic [C_DATA_WIDTH-1:0] write_data,
         output logic [C_DATA_WIDTH-1:0] read_data
-        );
+    );
     (* ram_style = "block" *)logic [C_DATA_WIDTH-1:0] branch_ram [C_DEPTH-1:0];
     //implementation
     ////////////////////////////////////////////////////

core/branch_unit.sv

@@ -20,11 +20,13 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import riscv_types::*;
-import taiga_types::*;
+module branch_unit
 
-module branch_unit(
+    import taiga_config::*;
+    import riscv_types::*;
+    import taiga_types::*;
+
+    (
         input logic clk,
         input logic rst,
 
@@ -46,7 +48,7 @@ module branch_unit(
         output logic tr_branch_misspredict,
         output logic tr_return_correct,
         output logic tr_return_misspredict
-        );
+    );
 
     logic branch_issued_r;
 

core/byte_en_BRAM.sv

@@ -22,16 +22,18 @@
 
 
 
-module byte_en_BRAM 
-import taiga_config::*;
-import taiga_types::*;
-import riscv_types::*;
+module byte_en_BRAM
+
+    import taiga_config::*;
+    import taiga_types::*;
+    import riscv_types::*;
+
 	#(
         parameter LINES = 4096,
         parameter preload_file = "",
         parameter USE_PRELOAD_FILE = 0
-        )
-        (
+    )
+    (
         input logic clk,
         input logic[$clog2(LINES)-1:0] addr_a,
         input logic en_a,
@@ -44,7 +46,7 @@ import riscv_types::*;
         input logic[XLEN/8-1:0] be_b,
         input logic[XLEN-1:0] data_in_b,
         output logic[XLEN-1:0] data_out_b
-        );
+    );
 
     generate
         if(FPGA_VENDOR == "xilinx")

core/dbram.sv

@@ -20,10 +20,12 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import taiga_types::*;
+module dbram
 
-module dbram(
+    import taiga_config::*;
+    import taiga_types::*;
+
+    (
         input logic clk,
         input logic rst,
 
@@ -32,7 +34,7 @@ module dbram(
         output logic[31:0] data_out,
 
         local_memory_interface.master data_bram
-        );
+    );
 
     assign ls.ready = 1;
 

core/dcache.sv

@@ -20,11 +20,13 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import riscv_types::*;
-import taiga_types::*;
+module dcache
 
-module dcache(
+    import taiga_config::*;
+    import riscv_types::*;
+    import taiga_types::*;
+    
+    (
         input logic clk,
         input logic rst,
         input logic dcache_on,
@@ -39,7 +41,7 @@ module dcache(
 
         input amo_details_t amo,
         ls_sub_unit_interface.sub_unit ls
-        );
+    );
 
     localparam DCACHE_SIZE_IN_WORDS = DCACHE_LINES*DCACHE_LINE_W*DCACHE_WAYS;
 

core/ddata_bank.sv

@@ -20,13 +20,15 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import taiga_types::*;
+module ddata_bank 
 
-module ddata_bank #(
+    import taiga_config::*;
+    import taiga_types::*;
+
+    #(
         parameter LINES = 2048
-        )
-        (
+    )
+    (
         input logic clk,
         input logic[$clog2(LINES)-1:0] addr_a,
         input logic en_a,
@@ -38,7 +40,7 @@ module ddata_bank #(
         input logic[$clog2(LINES)-1:0] addr_b,
         input logic en_b,
         input logic[31:0] data_in_b
-        );
+    );
 
     byte_en_BRAM #(LINES, "", 0) ram_block (.*, .be_b({4{en_b}}), .data_out_b());
 

core/decode_and_issue.sv

@@ -20,11 +20,13 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import riscv_types::*;
-import taiga_types::*;
+module decode_and_issue
 
-module decode_and_issue (
+    import taiga_config::*;
+    import riscv_types::*;
+    import taiga_types::*;
+    
+    (
         input logic clk,
         input logic rst,
 

core/div_unit.sv

@@ -20,11 +20,12 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import riscv_types::*;
-import taiga_types::*;
-
 module div_unit
+
+    import taiga_config::*;
+    import riscv_types::*;
+    import taiga_types::*;
+
     (
         input logic clk,
         input logic rst,

core/dtag_banks.sv

@@ -20,10 +20,12 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import taiga_types::*;
+module dtag_banks 
 
-module dtag_banks(
+    import taiga_config::*;
+    import taiga_types::*;
+
+    (
         input logic clk,
         input logic rst,
 

core/external_interfaces.sv

@@ -20,11 +20,8 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import taiga_types::*;
-import l2_config_and_types::*;
-
 interface axi_interface;
+    import taiga_config::*;
 
     logic arready;
     logic arvalid;
@@ -129,6 +126,8 @@ interface wishbone_interface;
 endinterface
 
 interface l1_arbiter_request_interface;
+    import l2_config_and_types::*;
+
     logic [31:0] addr;
     logic [31:0] data ;
     logic rnw ;

core/fetch.sv

@@ -20,11 +20,13 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import riscv_types::*;
-import taiga_types::*;
+module fetch
 
-module fetch(
+    import taiga_config::*;
+    import riscv_types::*;
+    import taiga_types::*;
+
+    (
         input logic clk,
         input logic rst,
 
@@ -59,7 +61,7 @@ module fetch(
 
         //Trace Interface
         output logic tr_early_branch_correction
-        );
+    );
 
     localparam NUM_SUB_UNITS = USE_I_SCRATCH_MEM + USE_ICACHE;
     localparam NUM_SUB_UNITS_W = (NUM_SUB_UNITS == 1) ? 1 : $clog2(NUM_SUB_UNITS);

core/gc_unit.sv

@@ -20,12 +20,14 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import riscv_types::*;
-import taiga_types::*;
-import csr_types::*;
+module gc_unit
 
-module gc_unit(
+    import taiga_config::*;
+    import riscv_types::*;
+    import taiga_types::*;
+    import csr_types::*;
+
+    (
         input logic clk,
         input logic rst,
 

core/ibram.sv

@@ -20,16 +20,18 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import taiga_types::*;
+module ibram
 
-module ibram(
+    import taiga_config::*;
+    import taiga_types::*;
+    
+    (
         input logic clk,
         input logic rst,
 
         fetch_sub_unit_interface.sub_unit fetch_sub,
         local_memory_interface.master instruction_bram
-        );
+    );
 
     assign fetch_sub.ready = 1;
 

core/icache.sv

@@ -20,10 +20,12 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-module icache 
+module icache
+
     import taiga_config::*;
     import riscv_types::*;
     import taiga_types::*;
+
     (
         input logic clk,
         input logic rst,

core/illegal_instruction_checker.sv

@@ -21,7 +21,9 @@
  */
 
 module  illegal_instruction_checker
+
     import taiga_config::*;
+    
     (
         input logic [31:0] instruction,
         output logic illegal_instruction

core/instruction_metadata_and_id_management.sv

@@ -23,6 +23,7 @@
 module instruction_metadata_and_id_management
 
     import taiga_config::*;
+    import riscv_types::*;
     import taiga_types::*;
 
     (

core/intel/intel_byte_enable_ram.sv

@@ -20,15 +20,20 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import taiga_types::*;
 
-module intel_byte_enable_ram #(
+
+module intel_byte_enable_ram 
+
+    import taiga_config::*;
+    import riscv_types::*;
+    import taiga_types::*;
+
+    #(
         parameter LINES = 8192,
         parameter preload_file = "",
         parameter USE_PRELOAD_FILE = 0
-        )
-        (
+    )
+    (
         input logic clk,
         input logic[$clog2(LINES)-1:0] addr_a,
         input logic en_a,
@@ -41,7 +46,7 @@ module intel_byte_enable_ram #(
         input logic[XLEN/8-1:0] be_b,
         input logic[XLEN-1:0] data_in_b,
         output logic[XLEN-1:0] data_out_b
-        );
+    );
 
     (* ramstyle = "no_rw_check" *) logic [3:0][7:0] ram [LINES-1:0];
 

core/interfaces.sv

@@ -20,12 +20,9 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import riscv_types::*;
-import taiga_types::*;
-import l2_config_and_types::*;
-
 interface branch_predictor_interface;
+    import taiga_types::*;
+
     //Fetch signals
     logic [31:0] if_pc;
     id_t if_id;
@@ -52,6 +49,8 @@ interface branch_predictor_interface;
 endinterface
 
 interface unit_issue_interface;
+    import taiga_types::*;
+
     logic possible_issue;
     logic new_request;
     logic new_request_r;
@@ -64,6 +63,9 @@ interface unit_issue_interface;
 endinterface
 
 interface unit_writeback_interface;
+    import riscv_types::*;
+    import taiga_types::*;
+
         logic ack;
 
         id_t id;
@@ -95,6 +97,8 @@ interface ras_interface;
 endinterface
 
 interface csr_exception_interface;
+    import riscv_types::*;
+
     logic valid;
     exception_code_t code;
     logic [31:0] pc;
@@ -109,6 +113,9 @@ interface csr_exception_interface;
 endinterface
 
 interface exception_interface;
+    import riscv_types::*;
+    import taiga_types::*;
+
     logic valid;
     logic ack;
     
@@ -184,6 +191,8 @@ interface tlb_interface;
 endinterface
 
 interface load_store_queue_interface;
+    import riscv_types::*;
+    import taiga_types::*;
 
     logic [31:0] addr;
     logic load;
@@ -210,6 +219,9 @@ interface load_store_queue_interface;
 endinterface
 
 interface writeback_store_interface;
+    import riscv_types::*;
+    import taiga_types::*;
+
         id_t id_needed;
         logic possibly_waiting;
         logic waiting;
@@ -274,6 +286,10 @@ interface unsigned_division_interface #(parameter DATA_WIDTH = 32);
 endinterface
 
 interface renamer_interface;
+    import taiga_config::*;
+    import riscv_types::*;
+    import taiga_types::*;
+
     rs_addr_t rd_addr;
     rs_addr_t [REGFILE_READ_PORTS-1:0] rs_addr;
     rs_wb_group_t rd_wb_group;
@@ -296,6 +312,10 @@ interface renamer_interface;
 endinterface
 
 interface register_file_issue_interface;
+    import taiga_config::*;
+    import riscv_types::*;
+    import taiga_types::*;
+
     //read interface
     phys_addr_t phys_rs_addr [REGFILE_READ_PORTS];
     logic [LOG2_COMMIT_PORTS-1:0] rs_wb_group [REGFILE_READ_PORTS];

core/itag_banks.sv

@@ -20,10 +20,12 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import taiga_types::*;
+module itag_banks
 
-module itag_banks(
+    import taiga_config::*;
+    import taiga_types::*;
+
+    (
         input logic clk,
         input logic rst,
 

core/l1_arbiter.sv

@@ -20,13 +20,14 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import riscv_types::*;
-import taiga_types::*;
-import l2_config_and_types::*;
-
 module l1_arbiter
-        (
+
+    import taiga_config::*;
+    import riscv_types::*;
+    import taiga_types::*;
+    import l2_config_and_types::*;
+
+    (
         input logic clk,
         input logic rst,
 
@@ -37,7 +38,7 @@ module l1_arbiter
 
         l1_arbiter_request_interface.slave l1_request[L1_CONNECTIONS-1:0],
         l1_arbiter_return_interface.slave l1_response[L1_CONNECTIONS-1:0]
-        );
+    );
 
     l2_request_t[L1_CONNECTIONS-1:0] l2_requests;
 

core/load_queue.sv

@@ -20,11 +20,13 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import riscv_types::*;
-import taiga_types::*;
+module load_queue
 
-module load_queue # (
+    import taiga_config::*;
+    import riscv_types::*;
+    import taiga_types::*;
+
+    # (
         parameter SQ_DEPTH = 4
     )
     ( 

core/load_store_unit.sv

@@ -20,11 +20,13 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import riscv_types::*;
-import taiga_types::*;
+module load_store_unit
 
-module load_store_unit (
+    import taiga_config::*;
+    import riscv_types::*;
+    import taiga_types::*;
+
+    (
         input logic clk,
         input logic rst,
         input load_store_inputs_t ls_inputs,
@@ -65,7 +67,7 @@ module load_store_unit (
         unit_writeback_interface.unit wb,
 
         output logic tr_load_conflict_delay
-        );
+    );
 
     localparam NUM_SUB_UNITS = USE_D_SCRATCH_MEM+USE_BUS+USE_DCACHE;
     localparam NUM_SUB_UNITS_W = (NUM_SUB_UNITS == 1) ? 1 : $clog2(NUM_SUB_UNITS);

core/mmu.sv

@@ -20,12 +20,13 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import riscv_types::*;
-import taiga_types::*;
-import csr_types::*;
-
 module mmu
+
+    import taiga_config::*;
+    import riscv_types::*;
+    import taiga_types::*;
+    import csr_types::*;
+
     (
         input logic clk,
         input logic rst,

core/mul_unit.sv

@@ -20,18 +20,20 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import riscv_types::*;
-import taiga_types::*;
+module mul_unit
 
-module mul_unit(
+    import taiga_config::*;
+    import riscv_types::*;
+    import taiga_types::*;
+
+    (
         input logic clk,
         input logic rst,
 
         input mul_inputs_t mul_inputs,
         unit_issue_interface.unit issue,
         unit_writeback_interface.unit wb
-        );
+    );
 
     logic signed [63:0] result;
     logic mulh [2];

core/one_hot_occupancy.sv

@@ -20,11 +20,9 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import taiga_types::*;
-
-module one_hot_occupancy #(parameter DEPTH = 4)
-        (
+module one_hot_occupancy 
+    #(parameter DEPTH = 4)
+    (
         input logic clk,
         input logic rst,
         input logic push,
@@ -34,7 +32,7 @@ module one_hot_occupancy #(parameter DEPTH = 4)
         output logic empty,
         output logic almost_empty,
         output logic valid
-        );
+    );
 
     logic [DEPTH:0] valid_chain;
 

core/one_hot_to_integer.sv

@@ -25,14 +25,14 @@
 module one_hot_to_integer
     #(
         parameter C_WIDTH = 40
-        )
-        (
+    )
+    (
         //clk and rst for assertion purposes
         input logic clk,
         input logic rst,
         input logic [C_WIDTH-1:0] one_hot,
         output logic [(C_WIDTH == 1) ? 0 : ($clog2(C_WIDTH)-1) : 0] int_out
-        );
+    );
     ////////////////////////////////////////////////////
     //Implementation
     localparam LOG2_WIDTH = $clog2(C_WIDTH);

core/ras.sv

@@ -20,17 +20,19 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
  
-import taiga_config::*;
-import riscv_types::*;
-import taiga_types::*;
+module ras
 
-module ras (
+    import taiga_config::*;
+    import riscv_types::*;
+    import taiga_types::*;
+
+    (
         input logic clk,
         input logic rst,
         input logic gc_fetch_flush,
         input logic early_branch_flush_ras_adjust,
         ras_interface.self ras
-        );
+    );
 
     (* ramstyle = "MLAB, no_rw_check" *) logic[31:0] lut_ram [RAS_DEPTH];
 

core/register_bank.sv

@@ -21,9 +21,11 @@
  */
 
 module register_bank
+
     import taiga_config::*;
     import riscv_types::*;
     import taiga_types::*;
+    
     #(
         parameter NUM_READ_PORTS = 2
     )

core/register_file.sv

@@ -21,9 +21,11 @@
  */
 
 module register_file
+
     import taiga_config::*;
     import riscv_types::*;
     import taiga_types::*;
+    
     (
         input logic clk,
         input logic rst,

core/register_free_list.sv

@@ -26,9 +26,11 @@
  *  For continuous operation when full, enqueing side must inspect pop signal
  */
 module register_free_list
+
     import taiga_config::*;
     import riscv_types::*;
     import taiga_types::*;
+    
     #(
         parameter DATA_WIDTH = 70, 
         parameter FIFO_DEPTH = 4

core/shift_counter.sv

@@ -20,15 +20,18 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import taiga_types::*;
+module shift_counter
 
-module shift_counter #(parameter DEPTH = 16) (
+    import taiga_config::*;
+    import taiga_types::*;
+
+    #(parameter DEPTH = 16)
+    (
         input logic clk,
         input logic rst,
         input logic start,
         output logic done
-        );
+    );
 
     logic [DEPTH-1:0] counter;
     ////////////////////////////////////////////////////

core/store_queue.sv

@@ -20,11 +20,13 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import riscv_types::*;
-import taiga_types::*;
+module store_queue
 
-module store_queue # (
+    import taiga_config::*;
+    import riscv_types::*;
+    import taiga_types::*;
+
+    # (
         parameter DEPTH = 4
     )
     ( 

core/taiga.sv

@@ -20,11 +20,16 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import riscv_types::*;
-import taiga_types::*;
 
-module taiga (
+
+module taiga
+
+    import taiga_config::*;
+    import l2_config_and_types::*;
+    import riscv_types::*;
+    import taiga_types::*;
+
+    (
         input logic clk,
         input logic rst,
 

core/taiga_fifo.sv

@@ -26,9 +26,11 @@
  *  For continuous operation when full, enqueing side must inspect pop signal
  */
 module taiga_fifo
+
     import taiga_config::*;
     import riscv_types::*;
     import taiga_types::*;
+    
     #(
         parameter DATA_WIDTH = 70, 
         parameter FIFO_DEPTH = 4

core/tlb_lut_ram.sv

@@ -20,14 +20,19 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import taiga_types::*;
 
-module tlb_lut_ram #(
+
+module tlb_lut_ram
+
+    import taiga_config::*;
+    import riscv_types::*;
+    import taiga_types::*;
+
+    #(
         parameter WAYS = 2,
         parameter DEPTH = 32
-        )
-        (
+    )
+    (
         input logic clk,
         input logic rst,
         input logic gc_tlb_flush,
@@ -35,7 +40,7 @@ module tlb_lut_ram #(
         input logic [ASIDLEN-1:0] asid,
         mmu_interface.tlb mmu,
         tlb_interface.tlb tlb
-        );
+    );
     //////////////////////////////////////////
     localparam TLB_TAG_W = 32-12-$clog2(DEPTH);
 

core/toggle_memory.sv

@@ -21,8 +21,10 @@
  */
 
 module toggle_memory
+
     import taiga_config::*;
     import taiga_types::*;
+    
     # (
         parameter DEPTH = 8
     )

core/toggle_memory_set.sv

@@ -21,8 +21,10 @@
  */
 
 module toggle_memory_set
+
     import taiga_config::*;
     import taiga_types::*;
+    
     # (
         parameter DEPTH = 64,
         parameter NUM_WRITE_PORTS = 3,

core/wishbone_master.sv

@@ -20,12 +20,13 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import riscv_types::*;
-import taiga_types::*;
-
 module wishbone_master
-        (
+
+    import taiga_config::*;
+    import riscv_types::*;
+    import taiga_types::*;
+
+    (
         input logic clk,
         input logic rst,
 
@@ -35,7 +36,7 @@ module wishbone_master
         input data_access_shared_inputs_t ls_inputs,
         ls_sub_unit_interface.sub_unit ls
 
-        );
+    );
     //implementation
     ////////////////////////////////////////////////////
 

core/writeback.sv

@@ -21,9 +21,11 @@
  */
 
 module writeback
+
     import taiga_config::*;
     import riscv_types::*;
     import taiga_types::*;
+    
     (
         input logic clk,
         input logic rst,

core/xilinx/taiga_wrapper_xilinx.sv

@@ -23,10 +23,12 @@
 
 
 module taiga_wrapper_xilinx
-import taiga_config::*;
-import taiga_types::*;
-import l2_config_and_types::*;
- (
+
+	import taiga_config::*;
+	import taiga_types::*;
+	import l2_config_and_types::*;
+
+	(
         input logic clk,
         input logic rst,
 

core/xilinx/xilinx_byte_enable_ram.sv

@@ -20,16 +20,18 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import taiga_types::*;
-import riscv_types::*;
+module xilinx_byte_enable_ram
 
-module xilinx_byte_enable_ram #(
+    import taiga_config::*;
+    import riscv_types::*;
+    import taiga_types::*;
+
+    #(
         parameter LINES = 4096,
         parameter preload_file = "",
         parameter USE_PRELOAD_FILE = 0
-        )
-        (
+    )
+    (
         input logic clk,
 
         input logic[$clog2(LINES)-1:0] addr_a,
@@ -43,7 +45,7 @@ module xilinx_byte_enable_ram #(
         input logic[XLEN/8-1:0] be_b,
         input logic[XLEN-1:0] data_in_b,
         output logic[XLEN-1:0] data_out_b
-        );
+    );
 
     logic [31:0] ram [LINES-1:0];
 

l2_arbiter/l2_arbiter.sv

@@ -20,16 +20,19 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import l2_config_and_types::*;
-import taiga_types::*;
+module l2_arbiter
 
-module l2_arbiter (
+    import l2_config_and_types::*;
+    import riscv_types::*;
+    import taiga_types::*;
+
+    (
         input logic clk,
         input logic rst,
 
         l2_requester_interface.slave request [L2_NUM_PORTS-1:0],
         l2_memory_interface.master mem
-        );
+    );
 
     l2_arbitration_interface arb();
 

l2_arbiter/l2_external_interfaces.sv

@@ -20,9 +20,9 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import l2_config_and_types::*;
-
 interface l2_requester_interface;
+    import l2_config_and_types::*;
+
     //l2_request_t request;
     logic [29:0] addr;
     logic [3:0] be;
@@ -75,6 +75,8 @@ endinterface
 
 
 interface l2_memory_interface #( parameter L2_ID_W = $clog2(L2_NUM_PORTS) + L2_SUB_ID_W);
+    import l2_config_and_types::*;
+
     logic [29:0] addr;
     logic [3:0] be;
     logic rnw;

l2_arbiter/l2_interfaces.sv

@@ -20,9 +20,9 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import l2_config_and_types::*;
-
 interface l2_arbitration_interface;
+    import l2_config_and_types::*;
+
     logic [L2_NUM_PORTS-1:0] requests;
     logic [$clog2(L2_NUM_PORTS)-1:0] grantee_i;
     logic [L2_NUM_PORTS-1:0] grantee_v;

l2_arbiter/l2_reservation_logic.sv

@@ -20,10 +20,12 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
  
-import l2_config_and_types::*;
 
 module l2_reservation_logic
-        (
+
+    import l2_config_and_types::*;
+
+    (
         input logic clk,
         input logic rst,
 
@@ -37,7 +39,7 @@ module l2_reservation_logic
 
         output logic abort
 
-        );
+    );
 
     logic [31:2] reservation_address [L2_NUM_PORTS-1:0];
     logic [L2_NUM_PORTS-1:0] reservation;

l2_arbiter/l2_round_robin.sv

@@ -20,14 +20,15 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import l2_config_and_types::*;
-
 module l2_round_robin
-        (
+
+    import l2_config_and_types::*;
+
+    (
         input logic clk,
         input logic rst,
         l2_arbitration_interface.slave arb
-        );
+    );
 
     logic [$clog2(L2_NUM_PORTS)-1:0] state;
     logic[$clog2(L2_NUM_PORTS)-1:0] muxes [L2_NUM_PORTS-1:0];

test_benches/taiga_tb.sv

@@ -22,15 +22,18 @@
 
 `timescale 1ns/1ns
 
-import tb_tools::*;
-import taiga_config::*;
-import taiga_types::*;
-import l2_config_and_types::*;
-
 `define  MEMORY_FILE  "/home/ematthew/Research/RISCV/software/riscv-tools/riscv-tests/benchmarks/dhrystone.riscv.sim_init"
 `define  UART_LOG  "/home/ematthew/uart.log"
 
-module taiga_tb ( );
+module taiga_tb 
+
+    import tb_tools::*;
+    import taiga_config::*;
+    import l2_config_and_types::*;
+    import riscv_types::*;
+    import taiga_types::*;
+
+  ( );
 
     logic simulator_clk;
     logic simulator_resetn;

test_benches/verilator/taiga_sim.sv

@@ -20,15 +20,17 @@
  *             Eric Matthews <ematthew@sfu.ca>
  */
 
-import taiga_config::*;
-import taiga_types::*;
-import l2_config_and_types::*;
+module taiga_sim 
 
+    import taiga_config::*;
+    import l2_config_and_types::*;
+    import riscv_types::*;
+    import taiga_types::*;
 
-module taiga_sim # (
+    # (
         parameter MEMORY_FILE = "/home/ematthew/Research/RISCV/software/riscv-tools/riscv-tests/benchmarks/dhrystone.riscv.hw_init" //change this to appropriate location "/home/ematthew/Downloads/dhrystone.riscv.sim_init"
-        )
-        (
+    )
+    (
         input logic clk,
         input logic rst,