switch spec_table to 1w_mr lutram

core/lutrams/lutram_1w_mr.sv

@@ -42,7 +42,7 @@ module lutram_1w_mr
 
 //For Xilinx with their wider selection of LUTRAMs, infer a multi-read port LUTRAM
 //For Intel, build the multi-read port ram from simple-dual-port LUTRAMs
-generate if (FPGA_VENDOR == XILINX) begin
+generate if (FPGA_VENDOR == XILINX) begin : xilinx_gen
     logic [WIDTH-1:0] ram [DEPTH-1:0];
 
     initial ram = '{default: 0};
@@ -58,7 +58,7 @@ generate if (FPGA_VENDOR == XILINX) begin
     end
 
 end
-else if (FPGA_VENDOR == INTEL) begin
+else if (FPGA_VENDOR == INTEL) begin : intel_gen
 
     for (genvar i = 0; i < NUM_READ_PORTS; i++) begin
         lutram_1w_1r #(.WIDTH(WIDTH), .DEPTH(DEPTH))

core/renamer.sv

@@ -92,12 +92,13 @@ module renamer
         phys_addr_t phys_addr;
         logic [$clog2(CONFIG.NUM_WB_GROUPS)-1:0] wb_group;
     } spec_table_t;
+    logic [4:0] spec_table_read_addr [REGFILE_READ_PORTS+1];
+    spec_table_t spec_table_read_data [REGFILE_READ_PORTS+1];
+
     spec_table_t spec_table_next;
     spec_table_t spec_table_old;
     spec_table_t spec_table_old_r;
 
-    (* ramstyle = "MLAB, no_rw_check" *) spec_table_t spec_table [32];
-
     logic spec_table_update;
     logic [4:0] spec_table_write_index;
 
@@ -121,10 +122,26 @@ module renamer
         end
     end
 
-    assign spec_table_old = spec_table[spec_table_write_index];
+    assign spec_table_read_addr[0] = spec_table_write_index;
+    assign spec_table_read_addr[1:REGFILE_READ_PORTS] = '{decode.rs_addr[RS1], decode.rs_addr[RS2]};
+
+    lutram_1w_mr #(
+        .WIDTH($bits(spec_table_t)),
+        .DEPTH(32),
+        .NUM_READ_PORTS(REGFILE_READ_PORTS+1)
+    )
+    spec_table_ram (
+        .clk(clk),
+        .waddr(spec_table_write_index),
+        .raddr(spec_table_read_addr),
+        .ram_write(spec_table_update),
+        .new_ram_data(spec_table_next),
+        .ram_data_out(spec_table_read_data)
+    );
+    assign spec_table_old = spec_table_read_data[0];
+
     always_ff @ (posedge clk) begin
         if (spec_table_update) begin
-            spec_table[spec_table_write_index] <= spec_table_next;
             spec_table_old_r <= spec_table_old;
         end
     end
@@ -140,7 +157,7 @@ module renamer
     //Renamed Outputs
     spec_table_t [REGFILE_READ_PORTS-1:0] spec_table_decode;
     generate for (genvar i = 0; i < REGFILE_READ_PORTS; i++) begin
-        assign spec_table_decode[i] = spec_table[decode.rs_addr[i]];
+        assign spec_table_decode[i] = spec_table_read_data[i+1];
         assign decode.phys_rs_addr[i] = spec_table_decode[i].phys_addr;
         assign decode.rs_wb_group[i] = spec_table_decode[i].wb_group;
     end endgenerate

test_benches/verilator/taiga_sim.sv

@@ -440,13 +440,19 @@ module taiga_sim
     logic [31:0][31:0] sim_registers_unamed;
 
     simulation_named_regfile sim_register;
+   typedef struct packed{
+        phys_addr_t phys_addr;
+        logic [$clog2(EXAMPLE_CONFIG.NUM_WB_GROUPS)-1:0] wb_group;
+    } spec_table_t;
+    spec_table_t translation [32];
     genvar i, j;
     generate  for (i = 0; i < 32; i++) begin
         for (j = 0; j < EXAMPLE_CONFIG.NUM_WB_GROUPS; j++) begin
+            assign translation[i] = cpu.renamer_block.spec_table_ram.xilinx_gen.ram[i];
             assign sim_registers_unamed_groups[j][i] = 
-            cpu.register_file_block.register_file_gen[j].reg_group.register_file_bank[cpu.renamer_block.spec_table[i].phys_addr];
+            cpu.register_file_block.register_file_gen[j].reg_group.register_file_bank[translation[i].phys_addr];
         end
-        assign sim_registers_unamed[31-i] = sim_registers_unamed_groups[cpu.renamer_block.spec_table[i].wb_group][i];
+        assign sim_registers_unamed[31-i] = sim_registers_unamed_groups[translation[i].wb_group][i];
     end
     endgenerate