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Remove phys_addr from issue/wb interface

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Signed-off-by: Eric Matthews <ematthew@sfu.ca>
This commit is contained in:
Eric Matthews 2023-02-03 16:31:23 -05:00
parent 2bac02308f
commit 79daaa9fd1
14 changed files with 33 additions and 44 deletions
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1
core/alu_unit.sv
View file

@ -177,7 +177,6 @@ module alu_unit
assign wb.rd = result;
assign wb.done = issue.possible_issue;
assign wb.id = issue.id;
assign wb.phys_addr = issue.phys_addr;
////////////////////////////////////////////////////
//Assertions

4
core/csr_unit.sv
View file

@ -176,10 +176,8 @@ module csr_unit
end
always_ff @(posedge clk) begin
if (issue.new_request) begin
if (issue.new_request)
wb.id <= issue.id;
wb.phys_addr <= issue.phys_addr;
end
end
assign wb.rd = selected_csr_r;

6
core/custom_unit.sv
View file

@ -47,7 +47,6 @@ module custom_unit
logic [31:0] result;
logic done;
id_t id;
phys_addr_t phys_addr;
////////////////////////////////////////////////////
//Implementation
//Simple 2-cycle adder that adds rs1 and rs2
@ -71,10 +70,8 @@ module custom_unit
assign issue.ready = ~wb.done;
always_ff @(posedge clk) begin
if (issue.new_request) begin
if (issue.new_request)
id <= issue.id;
phys_addr <= issue.phys_addr;
end
end
always_ff @(posedge clk) begin
@ -93,5 +90,4 @@ module custom_unit
wb.done <= (wb.done & ~wb.ack) | issue.new_request;
end
assign wb.id = id;
assign wb.phys_addr = phys_addr;
endmodule

5
core/cva5.sv
View file

@ -170,6 +170,7 @@ module cva5
logic retire_port_valid [RETIRE_PORTS];
//Writeback
wb_packet_t wb_packet [CONFIG.NUM_WB_GROUPS];
phys_addr_t wb_phys_addr [CONFIG.NUM_WB_GROUPS];
//Exception
logic [31:0] oldest_pc;
@ -249,6 +250,7 @@ module cva5
.instruction_issued (instruction_issued),
.instruction_issued_with_rd (instruction_issued_with_rd),
.wb_packet (wb_packet),
.wb_phys_addr (wb_phys_addr),
.retire (retire),
.store_retire (store_retire),
.retire_ids (retire_ids),
@ -402,7 +404,8 @@ module cva5
.decode_uses_rd (decode_uses_rd),
.decode_rd_addr (decode_rd_addr),
.rf_issue (rf_issue),
.commit (wb_packet)
.commit (wb_packet),
.wb_phys_addr (wb_phys_addr)
);
////////////////////////////////////////////////////

3
core/cva5_types.sv
View file

@ -111,7 +111,6 @@ package cva5_types;
logic [2:0] fn3;
logic [31:0] data;
id_t id;
phys_addr_t phys_addr;
logic forwarded_store;
id_t id_needed;
} lsq_entry_t;
@ -132,7 +131,6 @@ package cva5_types;
typedef struct packed{
id_t id;
phys_addr_t phys_addr;
logic valid;
logic [31:0] data;
} wb_packet_t;
@ -151,7 +149,6 @@ package cva5_types;
logic [2:0] fn3;
logic [31:0] data_in;
id_t id;
phys_addr_t phys_addr;
} data_access_shared_inputs_t;
typedef enum {

1
core/decode_and_issue.sv
View file

@ -232,7 +232,6 @@ module decode_and_issue
assign unit_issue[i].possible_issue = issue.stage_valid & unit_needed_issue_stage[i] & unit_issue[i].ready;
assign unit_issue[i].new_request = issue_to[i];
assign unit_issue[i].id = issue.id;
assign unit_issue[i].phys_addr = issue.phys_rd_addr;
end endgenerate
////////////////////////////////////////////////////

3
core/div_unit.sv
View file

@ -70,7 +70,6 @@ module div_unit
logic divisor_is_zero;
logic reuse_result;
id_t id;
phys_addr_t phys_addr;
} div_attributes_t;
typedef struct packed{
@ -170,7 +169,6 @@ module div_unit
assign issue_fifo_inputs.attr.divisor_is_zero = divisor_is_zero;
assign issue_fifo_inputs.attr.reuse_result = div_op_reuse;
assign issue_fifo_inputs.attr.id = issue.id;
assign issue_fifo_inputs.attr.phys_addr = issue.phys_addr;
////////////////////////////////////////////////////
//Input FIFO
@ -238,7 +236,6 @@ module div_unit
end
assign wb.id = wb_attr.id;
assign wb.phys_addr = wb_attr.phys_addr;
////////////////////////////////////////////////////
//Assertions

16
core/instruction_metadata_and_id_management.sv
View file

@ -64,6 +64,7 @@ module instruction_metadata_and_id_management
//WB
input wb_packet_t wb_packet [CONFIG.NUM_WB_GROUPS],
output phys_addr_t wb_phys_addr [CONFIG.NUM_WB_GROUPS],
//Retirer
output retire_packet_t retire,
@ -86,6 +87,8 @@ module instruction_metadata_and_id_management
(* ramstyle = "MLAB, no_rw_check" *) logic [0:0] uses_rd_table [MAX_IDS];
(* ramstyle = "MLAB, no_rw_check" *) logic [0:0] is_store_table [MAX_IDS];
(* ramstyle = "MLAB, no_rw_check" *) phys_addr_t id_to_phys_rd_table [MAX_IDS];
(* ramstyle = "MLAB, no_rw_check" *) logic [$bits(fetch_metadata_t)-1:0] fetch_metadata_table [MAX_IDS];
(* ramstyle = "MLAB, no_rw_check" *) logic [$bits(exception_sources_t)-1:0] exception_unit_table [MAX_IDS];
@ -150,6 +153,14 @@ module instruction_metadata_and_id_management
is_store_table[decode_id] <= decode_is_store;
end
////////////////////////////////////////////////////
//id_to_phys_rd_table
//Number of read ports = WB_GROUPS
always_ff @ (posedge clk) begin
if (decode_advance)
id_to_phys_rd_table[decode_id] <= decode_phys_rd_addr;
end
////////////////////////////////////////////////////
//Exception unit table
@ -270,6 +281,11 @@ module instruction_metadata_and_id_management
.in_use (id_waiting_for_writeback)
);
////////////////////////////////////////////////////
//WB phys_addr lookup
always_comb for (int i = 0; i < CONFIG.NUM_WB_GROUPS; i++)
wb_phys_addr[i] = id_to_phys_rd_table[wb_packet[i].id];
////////////////////////////////////////////////////
//Retirer
logic contiguous_retire;

10
core/internal_interfaces.sv
View file

@ -72,12 +72,11 @@ interface unit_issue_interface;
logic possible_issue;
logic new_request;
id_t id;
phys_addr_t phys_addr;
logic ready;
modport decode (input ready, output possible_issue, new_request, id, phys_addr);
modport unit (output ready, input possible_issue, new_request, id, phys_addr);
modport decode (input ready, output possible_issue, new_request, id);
modport unit (output ready, input possible_issue, new_request, id);
endinterface
interface unit_writeback_interface;
@ -87,17 +86,16 @@ interface unit_writeback_interface;
logic ack;
id_t id;
phys_addr_t phys_addr;
logic done;
logic [XLEN-1:0] rd;
modport unit (
input ack,
output id, done, rd, phys_addr
output id, done, rd
);
modport wb (
output ack,
input id, done, rd, phys_addr
input id, done, rd
);
endinterface

8
core/load_store_queue.sv
View file

@ -48,7 +48,6 @@ module load_store_queue //ID-based input buffer for Load/Store Unit
logic [31:0] addr;
logic [2:0] fn3;
id_t id;
phys_addr_t phys_addr;
logic store_collision;
logic [LOG2_SQ_DEPTH-1:0] sq_index;
} lq_entry_t;
@ -98,7 +97,6 @@ module load_store_queue //ID-based input buffer for Load/Store Unit
addr : lsq.data_in.addr,
fn3 : lsq.data_in.fn3,
id : lsq.data_in.id,
phys_addr : lsq.data_in.phys_addr,
store_collision : potential_store_conflict,
sq_index : sq_index
};
@ -142,8 +140,7 @@ module load_store_queue //ID-based input buffer for Load/Store Unit
be : '0,
fn3 : lq_data_out.fn3,
data_in : sq.data_out.data,
id : lq_data_out.id,
phys_addr : lq_data_out.phys_addr
id : lq_data_out.id
};
assign lsq.store_data_out = '{
@ -153,8 +150,7 @@ module load_store_queue //ID-based input buffer for Load/Store Unit
be : sq.data_out.be,
fn3 : sq.data_out.fn3,
data_in : sq.data_out.data,
id : lq_data_out.id,
phys_addr : lq_data_out.phys_addr
id : lq_data_out.id
};
assign lsq.sq_empty = sq.empty;

4
core/load_store_unit.sv
View file

@ -135,7 +135,6 @@ module load_store_unit
logic [1:0] sign_sel;
logic [1:0] final_mux_sel;
id_t id;
phys_addr_t phys_addr;
logic [NUM_SUB_UNITS_W-1:0] subunit_id;
} load_attributes_t;
load_attributes_t mem_attr, wb_attr;
@ -289,7 +288,6 @@ module load_store_unit
load : is_load_r,
store : is_store_r,
id : issue.id,
phys_addr : issue.phys_addr,
forwarded_store : CONFIG.INCLUDE_FORWARDING_TO_STORES & rs2_inuse,
id_needed : store_forward_id
};
@ -368,7 +366,6 @@ module load_store_unit
sign_sel : lsq.load_data_out.addr[1:0] | {1'b0, lsq.load_data_out.fn3[0]},//halfwrord
final_mux_sel : final_mux_sel,
id : lsq.load_data_out.id,
phys_addr : lsq.load_data_out.phys_addr,
subunit_id : subunit_id
};
@ -510,7 +507,6 @@ module load_store_unit
assign wb.rd = final_load_data;
assign wb.done = load_complete | load_exception_complete;
assign wb.id = load_exception_complete ? exception.id : wb_attr.id;
assign wb.phys_addr = wb_attr.phys_addr;
////////////////////////////////////////////////////
//End of Implementation

4
core/mul_unit.sv
View file

@ -49,7 +49,6 @@ module mul_unit
logic mulh [2];
logic valid [2];
id_t id [2];
phys_addr_t phys_addr [2];
logic rs1_is_signed, rs2_is_signed;
logic signed [32:0] rs1_ext, rs2_ext;
@ -99,12 +98,10 @@ module mul_unit
if (stage1_advance) begin
mulh[0] <= (issue_stage.fn3[1:0] != MUL_fn3[1:0]);
id[0] <= issue.id;
phys_addr[0] <= issue.phys_addr;
end
if (stage2_advance) begin
mulh[1] <= mulh[0];
id[1] <= id[0];
phys_addr[1] <= phys_addr[0];
end
end
@ -123,7 +120,6 @@ module mul_unit
assign wb.rd = mulh[1] ? result[63:32] : result[31:0];
assign wb.done = valid[1];
assign wb.id = id[1];
assign wb.phys_addr = phys_addr[1];
////////////////////////////////////////////////////
//End of Implementation

9
core/register_file.sv
View file

@ -47,7 +47,8 @@ module register_file
register_file_issue_interface.register_file rf_issue,
//Writeback
input wb_packet_t commit [CONFIG.NUM_WB_GROUPS]
input wb_packet_t commit [CONFIG.NUM_WB_GROUPS],
input phys_addr_t wb_phys_addr [CONFIG.NUM_WB_GROUPS]
);
typedef logic [31:0] rs_data_t [REGFILE_READ_PORTS];
rs_data_t regfile_rs_data [CONFIG.NUM_WB_GROUPS];
@ -81,8 +82,8 @@ module register_file
toggle[1] = rf_issue.single_cycle_or_flush;
toggle_addr[1] = rf_issue.phys_rd_addr;
for (int i = 1; i < CONFIG.NUM_WB_GROUPS; i++) begin
toggle[i+1] = commit[i].valid & |commit[i].phys_addr;
toggle_addr[i+1] = commit[i].phys_addr;
toggle[i+1] = commit[i].valid & |wb_phys_addr[i];
toggle_addr[i+1] = wb_phys_addr[i];
end
end
toggle_memory_set # (
@ -110,7 +111,7 @@ module register_file
lutram_1w_mr #(.WIDTH(32), .DEPTH(64), .NUM_READ_PORTS(REGFILE_READ_PORTS))
register_file_bank (
.clk,
.waddr(commit[i].phys_addr),
.waddr(wb_phys_addr[i]),
.raddr(decode_phys_rs_addr),
.ram_write(commit[i].valid & ~gc.writeback_supress),
.new_ram_data(commit[i].data),

3
core/writeback.sv
View file

@ -44,7 +44,6 @@ module writeback
logic [NUM_WB_UNITS-1:0] unit_ack;
//aliases for write-back-interface signals
id_t [NUM_WB_UNITS-1:0] unit_instruction_id;
phys_addr_t [NUM_WB_UNITS-1:0] unit_phys_addr;
logic [NUM_WB_UNITS-1:0] unit_done;
logic [XLEN-1:0] unit_rd [NUM_WB_UNITS];
@ -59,7 +58,6 @@ module writeback
//Re-assigning interface inputs to array types so that they can be dynamically indexed
generate for (i = 0; i < NUM_WB_UNITS; i++) begin : gen_wb_unit_unpacking
assign unit_instruction_id[i] = unit_wb[i].id;
assign unit_phys_addr[i] = unit_wb[i].phys_addr;
assign unit_done[i] = unit_wb[i].done;
assign unit_wb[i].ack = unit_ack[i];
assign unit_rd[i] = unit_wb[i].rd;
@ -78,7 +76,6 @@ module writeback
);
assign wb_packet.valid = |unit_done;
assign wb_packet.id = unit_instruction_id[unit_sel];
assign wb_packet.phys_addr = unit_phys_addr[unit_sel];
assign wb_packet.data = unit_rd[unit_sel];
assign unit_ack = NUM_WB_UNITS'(wb_packet.valid) << unit_sel;