initial pass at new forwarding network

core/alu_unit.sv

@@ -90,6 +90,8 @@ module alu_unit(
 
     assign issue.ready = 1;
     assign wb.rd = rd_bank[wb.writeback_instruction_id];
+    assign wb.rs1_data = rd_bank[wb.writeback_rs1_id];
+    assign wb.rs2_data = rd_bank[wb.writeback_rs2_id];
     assign wb.done_next_cycle = issue.instruction_id_one_hot & {MAX_INFLIGHT_COUNT{issue.new_request}};
 
     ////////////////////////////////////////////////////

core/div_unit.sv

@@ -125,7 +125,8 @@ module div_unit
 
     assign wb.done_next_cycle = stage1.instruction_id_one_hot & {MAX_INFLIGHT_COUNT{div_done}};
     assign wb.rd = rd_bank[wb.writeback_instruction_id];
-
+    assign wb.rs1_data = rd_bank[wb.writeback_rs1_id];
+    assign wb.rs2_data = rd_bank[wb.writeback_rs2_id];
 
     ////////////////////////////////////////////////////
     //Assertions

core/interfaces.sv

@@ -78,11 +78,15 @@ interface unit_writeback_interface;
     //unit output
     instruction_id_one_hot_t done_next_cycle;
     logic [XLEN-1:0] rd;
+    logic [XLEN-1:0] rs1_data;
+    logic [XLEN-1:0] rs2_data;
     //writeback output
     logic accepted;
     instruction_id_t writeback_instruction_id;
-    modport writeback (input done_next_cycle, rd, output accepted, writeback_instruction_id);
-    modport unit (output done_next_cycle, rd, input accepted, writeback_instruction_id);
+    instruction_id_t writeback_rs1_id;
+    instruction_id_t writeback_rs2_id;
+    modport writeback (input done_next_cycle, rd, rs1_data, rs2_data, output accepted, writeback_instruction_id, writeback_rs1_id, writeback_rs2_id);
+    modport unit (output done_next_cycle, rd, rs1_data, rs2_data, input accepted, writeback_instruction_id, writeback_rs1_id, writeback_rs2_id);
 endinterface
 
 //********************************
@@ -140,11 +144,15 @@ interface register_file_writeback_interface;
     logic[XLEN-1:0] rd_data;
     instruction_id_t id;
 
-    logic forward_rs1;
-    logic forward_rs2;
+    instruction_id_t rs1_id;
+    instruction_id_t rs2_id;
+    logic[XLEN-1:0] rs1_data;
+    logic[XLEN-1:0] rs2_data;
+    logic rs1_valid;
+    logic rs2_valid;
     
-    modport writeback (output rd_addr, commit, rd_nzero, rd_data, id, input forward_rs1, forward_rs2);
-    modport unit (input rd_addr, commit, rd_nzero, rd_data, id, output forward_rs1, forward_rs2);
+    modport writeback (output rd_addr, commit, rd_nzero, rd_data, id, rs1_data, rs2_data, rs1_valid, rs2_valid,  input rs1_id, rs2_id);
+    modport unit (input rd_addr, commit, rd_nzero, rd_data, id, rs1_data, rs2_data, rs1_valid, rs2_valid, output rs1_id, rs2_id);
 
 endinterface
 

core/load_store_unit.sv

@@ -341,6 +341,8 @@ module load_store_unit (
     end
 
     assign wb.rd = rd_bank[wb.writeback_instruction_id];
+    assign wb.rs1_data = rd_bank[wb.writeback_rs1_id];
+    assign wb.rs2_data = rd_bank[wb.writeback_rs2_id];
 
     logic exception_complete;
     logic ls_done;

core/mul_unit.sv

@@ -80,6 +80,8 @@ module mul_unit(
     ////////////////////////////////////////////////////
     assign issue.ready = 1;
     assign wb.rd = rd_bank[wb.writeback_instruction_id];
+    assign wb.rs1_data = rd_bank[wb.writeback_rs1_id];
+    assign wb.rs2_data = rd_bank[wb.writeback_rs2_id];
     assign wb.done_next_cycle = id_one_hot_done[1];
 
     ////////////////////////////////////////////////////

core/register_file.sv

@@ -44,6 +44,7 @@ module register_file(
 
     logic valid_write;
     logic in_use_match;
+
     instruction_id_t in_use_by_id;
     instruction_id_t rs1_id;
     instruction_id_t rs2_id;
@@ -81,17 +82,20 @@ module register_file(
     assign rs1_id =  in_use_by[rf_decode.rs1_addr];
     assign rs2_id =  in_use_by[rf_decode.rs2_addr];
     
+    assign rf_wb.rs1_id = rs1_id;
+    assign rf_wb.rs2_id = rs2_id;
+
     assign valid_write = rf_wb.rd_nzero && rf_wb.commit;
     assign in_use_match = (rf_wb.id == in_use_by_id);
 
-    assign rs1_feedforward = rs1_inuse && (rs1_id == rf_wb.id) && rf_wb.commit;
-    assign rs2_feedforward = rs2_inuse && (rs2_id == rf_wb.id) && rf_wb.commit;
+    assign rs1_feedforward = rs1_inuse;// && (rs1_id == rf_wb.id) && rf_wb.commit;
+    assign rs2_feedforward = rs2_inuse;// && (rs2_id == rf_wb.id) && rf_wb.commit;
 
-    assign rf_decode.rs1_data = rs1_feedforward ? rf_wb.rd_data : register[rf_decode.rs1_addr];
-    assign rf_decode.rs2_data = rs2_feedforward ? rf_wb.rd_data : register[rf_decode.rs2_addr];
+    assign rf_decode.rs1_data = rs1_feedforward ? rf_wb.rs1_data : register[rf_decode.rs1_addr];
+    assign rf_decode.rs2_data = rs2_feedforward ? rf_wb.rs2_data : register[rf_decode.rs2_addr];
 
-    assign rf_decode.rs1_conflict = rf_decode.uses_rs1 & rs1_inuse & ~rs1_feedforward;
-    assign rf_decode.rs2_conflict = rf_decode.uses_rs2 & rs2_inuse & ~rs2_feedforward;
+    assign rf_decode.rs1_conflict = rf_decode.uses_rs1 & rs1_inuse & ~rf_wb.rs1_valid;//rs1_inuse & ~rs1_feedforward;
+    assign rf_decode.rs2_conflict = rf_decode.uses_rs2 & rs2_inuse & ~rf_wb.rs2_valid;//rs2_inuse & ~rs2_feedforward;
 
     ////////////////////////////////////////////////////
     //Assertions

core/taiga_types.sv

@@ -29,6 +29,7 @@ package taiga_types;
 
     typedef logic[$clog2(MAX_INFLIGHT_COUNT)-1:0] instruction_id_t;
     typedef logic[MAX_INFLIGHT_COUNT-1:0] instruction_id_one_hot_t;
+    typedef logic[$clog2(NUM_WB_UNITS)-1:0] unit_id_t;
     typedef logic[1:0] branch_predictor_metadata_t;
 
     typedef enum bit [6:0] {
@@ -269,7 +270,7 @@ package taiga_types;
     } exception_packet_t;
 
     typedef struct packed{
-        logic [$clog2(NUM_WB_UNITS)-1:0] unit_id;
+        unit_id_t unit_id;
         logic [4:0] rd_addr;
         logic rd_addr_nzero;
     } inflight_instruction_packet;

core/write_back.sv

@@ -51,10 +51,14 @@ module write_back(
     //aliases for write-back-interface signals
     logic [MAX_INFLIGHT_COUNT-1:0] unit_done_next_cycle [NUM_WB_UNITS-1:0];
     logic [XLEN-1:0] unit_rd [NUM_WB_UNITS-1:0];
+    logic [XLEN-1:0] unit_rs1 [NUM_WB_UNITS-1:0];
+    logic [XLEN-1:0] unit_rs2 [NUM_WB_UNITS-1:0];
     /////
 
     instruction_id_t issue_id, retired_id, retired_id_r;
     inflight_instruction_packet retired_instruction_packet;
+    inflight_instruction_packet rs1_packet;
+    inflight_instruction_packet rs2_packet;
 
     instruction_id_t id_ordering [MAX_INFLIGHT_COUNT-1:0];
     instruction_id_t id_ordering_post_store [MAX_INFLIGHT_COUNT-1:0];
@@ -75,7 +79,11 @@ module write_back(
         for (i=0; i< NUM_WB_UNITS; i++) begin : interface_to_array_g
             assign unit_done_next_cycle[i] = unit_wb[i].done_next_cycle;
             assign unit_rd[i] = unit_wb[i].rd;
+            assign unit_rs1[i] = unit_wb[i].rs1_data;
+            assign unit_rs2[i] = unit_wb[i].rs2_data;
             assign unit_wb[i].writeback_instruction_id = retired_id_r;
+            assign unit_wb[i].writeback_rs1_id = rf_wb.rs1_id;
+            assign unit_wb[i].writeback_rs2_id = rf_wb.rs2_id;
         end
     endgenerate
 
@@ -174,6 +182,14 @@ module write_back(
     assign rf_wb.rd_nzero = retired_instruction_packet.rd_addr_nzero;
     assign rf_wb.rd_data = unit_rd[retired_instruction_packet.unit_id];
 
+    assign rf_wb.rs1_valid = id_done_r[rf_wb.rs1_id];
+    assign rf_wb.rs2_valid = id_done_r[rf_wb.rs2_id];
+
+    assign rs1_packet = packet_table[rf_wb.rs1_id];
+    assign rs2_packet = packet_table[rf_wb.rs2_id];
+
+    assign rf_wb.rs1_data = unit_rs1[rs1_packet.unit_id];
+    assign rf_wb.rs2_data = unit_rs2[rs2_packet.unit_id];
     ////////////////////////////////////////////////////
     //End of Implementation
     ////////////////////////////////////////////////////