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writeback to shared ID register file

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This commit is contained in:
Eric Matthews 2019-09-01 20:35:41 -07:00
parent f75f981f36
commit 89ae201b30
5 changed files with 51 additions and 62 deletions
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12
core/alu_unit.sv
View file

@ -40,7 +40,6 @@ module alu_unit(
logic[XLEN:0] adder_in2;
logic[XLEN-1:0] result;
logic [31:0] rd_bank [MAX_INFLIGHT_COUNT-1:0];
//implementation
////////////////////////////////////////////////////
@ -82,16 +81,9 @@ module alu_unit(
end
////////////////////////////////////////////////////
//Output bank
always_ff @ (posedge clk) begin
if (issue.possible_issue)
rd_bank[issue.instruction_id] <= result;
end
//Output
assign issue.ready = 1;
assign wb.rd = rd_bank[wb.writeback_instruction_id];
assign wb.rs1_data = rd_bank[wb.writeback_rs1_id];
assign wb.rs2_data = rd_bank[wb.writeback_rs2_id];
assign wb.rd = result;
assign wb.done_next_cycle = issue.new_request;
assign wb.id = issue.instruction_id;

12
core/div_unit.sv
View file

@ -56,7 +56,6 @@ module div_unit
logic divisor_zero;
logic [31:0] wb_div_result;
logic [31:0] rd_bank [MAX_INFLIGHT_COUNT-1:0];
div_inputs_t stage1;
@ -117,15 +116,8 @@ module div_unit
div_algorithm #(XLEN) div (.*, .start(start_algorithm), .A(complementerA), .B(complementerB), .Q(quotient), .R(remainder), .complete(computation_complete), .ack(computation_complete), .B_is_zero(divisor_zero));
////////////////////////////////////////////////////
//Output bank
always_ff @(posedge clk) begin
if (div_done)
rd_bank[stage1.instruction_id] <= wb_div_result;
end
assign wb.rd = rd_bank[wb.writeback_instruction_id];
assign wb.rs1_data = rd_bank[wb.writeback_rs1_id];
assign wb.rs2_data = rd_bank[wb.writeback_rs2_id];
//Output
assign wb.rd = wb_div_result;
assign wb.done_next_cycle = div_done;
assign wb.id = stage1.instruction_id;
////////////////////////////////////////////////////

14
core/load_store_unit.sv
View file

@ -82,7 +82,6 @@ module load_store_unit (
logic [31:0] aligned_load_data;
logic [31:0] final_load_data;
logic [31:0] rd_bank [MAX_INFLIGHT_COUNT-1:0];
logic [31:0] previous_load;
logic [31:0] stage1_raw_data;
@ -309,21 +308,14 @@ module load_store_unit (
endcase
end
////////////////////////////////////////////////////
//Output bank
always_ff @ (posedge clk) begin
if (load_complete | csr_done)
rd_bank[csr_done ? csr_id : stage2_attr.instruction_id] <= csr_done ? csr_rd : final_load_data;
end
always_ff @ (posedge clk) begin
if (load_complete)
previous_load <= final_load_data;
end
assign wb.rd = rd_bank[wb.writeback_instruction_id];
assign wb.rs1_data = rd_bank[wb.writeback_rs1_id];
assign wb.rs2_data = rd_bank[wb.writeback_rs2_id];
////////////////////////////////////////////////////
//Output bank
assign wb.rd = csr_done ? csr_rd : final_load_data;//rd_bank[wb.writeback_instruction_id];
logic exception_complete;
logic ls_done;

13
core/mul_unit.sv
View file

@ -40,8 +40,6 @@ module mul_unit(
logic rs1_signed, rs2_signed;
logic signed [32:0] rs1_ext, rs2_ext;
logic signed [32:0] rs1_r, rs2_r;
logic [31:0] rd_bank [MAX_INFLIGHT_COUNT-1:0];
////////////////////////////////////////////////////
//Implementation
@ -69,19 +67,10 @@ module mul_unit(
done_next_cycle[1] <= done_next_cycle[0];
end
////////////////////////////////////////////////////
//Output bank
always_ff @ (posedge clk) begin
if (done_next_cycle[1])
rd_bank[id[1]] <= mulh[1] ? result[63:32] : result[31:0];
end
//Issue/write-back handshaking
////////////////////////////////////////////////////
assign issue.ready = 1;
assign wb.rd = rd_bank[wb.writeback_instruction_id];
assign wb.rs1_data = rd_bank[wb.writeback_rs1_id];
assign wb.rs2_data = rd_bank[wb.writeback_rs2_id];
assign wb.rd = mulh[1] ? result[63:32] : result[31:0];
assign wb.done_next_cycle = done_next_cycle[1];
assign wb.id = id[1];
////////////////////////////////////////////////////

62
core/write_back.sv
View file

@ -52,15 +52,18 @@ module write_back(
logic [XLEN-1:0] unit_rs2 [NUM_WB_UNITS-1:0];
/////
logic [XLEN-1:0] rds_by_id [MAX_INFLIGHT_COUNT-1:0];
logic [XLEN-1:0] rds_by_id_next [MAX_INFLIGHT_COUNT-1:0];
logic [NUM_WB_UNITS-1:0][MAX_INFLIGHT_COUNT-1:0] write_reg;
logic [$clog2(NUM_WB_UNITS)-1:0] id_unit_select [MAX_INFLIGHT_COUNT-1:0];
instruction_id_t issue_id, retired_id, retired_id_r;
inflight_instruction_packet retired_instruction_packet;
inflight_instruction_packet rs1_packet;
inflight_instruction_packet rs2_packet;
instruction_id_t id_ordering [MAX_INFLIGHT_COUNT-1:0];
instruction_id_t id_ordering_post_store [MAX_INFLIGHT_COUNT-1:0];
logic [MAX_INFLIGHT_COUNT-1:0] id_done;
logic [MAX_INFLIGHT_COUNT-1:0] id_done_new;
logic [MAX_INFLIGHT_COUNT-1:0] id_done_r;
logic [MAX_INFLIGHT_COUNT-1:0] id_done_ordered;
@ -77,14 +80,34 @@ module write_back(
assign unit_instruction_id[i] = unit_wb[i].id;
assign unit_done_next_cycle[i] = unit_wb[i].done_next_cycle;
assign unit_rd[i] = unit_wb[i].rd;
assign unit_rs1[i] = unit_wb[i].rs1_data;
assign unit_rs2[i] = unit_wb[i].rs2_data;
assign unit_wb[i].writeback_instruction_id = retired_id_r;
assign unit_wb[i].writeback_rs1_id = rf_wb.rs1_id;
assign unit_wb[i].writeback_rs2_id = rf_wb.rs2_id;
end
endgenerate
always_comb begin
foreach(id_done_new[i]) begin
id_done_new[i] = 0;
id_unit_select[i] = 0;
for (int j=0; j< NUM_WB_UNITS; j++) begin
if (unit_done_next_cycle[j] && (unit_instruction_id[j] == i[$clog2(MAX_INFLIGHT_COUNT)-1:0])) begin
id_unit_select[i] = j[$clog2(NUM_WB_UNITS)-1:0];
id_done_new[i] |= 1;//unit_done_next_cycle[j] && (unit_instruction_id[j] == i[$clog2(MAX_INFLIGHT_COUNT)-1:0]);
end
end
end
end
always_comb begin
foreach(rds_by_id_next[i]) begin
rds_by_id_next[i] = unit_rd[id_unit_select[i]];
end
end
always_ff @ (posedge clk) begin
foreach(rds_by_id_next[i]) begin
if (id_done_new[i])
rds_by_id[i] <= rds_by_id_next[i];
end
end
//ID tracking
id_tracking id_fifos (.*, .issued(ti.issued), .retired(retired), .id_available(ti.id_available),
.oldest_id(oldest_id), .next_id(issue_id), .empty(instruction_queue_empty));
@ -118,14 +141,15 @@ module write_back(
end
//Or together all unit done signals for the same ID.
always_comb begin
id_done = (id_done_r & ~id_retired_last_cycle_r); //Still pending instructions
for (int i=0; i < MAX_INFLIGHT_COUNT; i++) begin
for (int j=0; j< NUM_WB_UNITS; j++) begin
id_done[i] |= unit_done_next_cycle[j] && (unit_instruction_id[j] == i[$clog2(MAX_INFLIGHT_COUNT)-1:0]);
end
end
end
// always_comb begin
// id_done_new = 0;
// for (int i=0; i < MAX_INFLIGHT_COUNT; i++) begin
// for (int j=0; j< NUM_WB_UNITS; j++) begin
// id_done_new[i] |= unit_done_next_cycle[j] && (unit_instruction_id[j] == i[$clog2(MAX_INFLIGHT_COUNT)-1:0]);
// end
// end
// end
assign id_done = (id_done_r & ~id_retired_last_cycle_r) | id_done_new; //Still pending instructions
always_ff @ (posedge clk) begin
if (rst)
@ -154,13 +178,13 @@ module write_back(
assign rf_wb.id = retired_id_r;
assign rf_wb.commit = retired_r & ~retired_instruction_packet.is_store;
assign rf_wb.rd_nzero = retired_instruction_packet.rd_addr_nzero;
assign rf_wb.rd_data = unit_rd[retired_instruction_packet.unit_id];
assign rf_wb.rd_data = rds_by_id[retired_id_r];//unit_rd[retired_instruction_packet.unit_id];
assign rf_wb.rs1_valid = id_done_r[rf_wb.rs1_id];
assign rf_wb.rs2_valid = id_done_r[rf_wb.rs2_id];
assign rf_wb.rs1_data = unit_rs1[rf_wb.rs1_unit_id];
assign rf_wb.rs2_data = unit_rs2[rf_wb.rs2_unit_id];
assign rf_wb.rs1_data = rds_by_id[rf_wb.rs1_id];
assign rf_wb.rs2_data = rds_by_id[rf_wb.rs2_id];
////////////////////////////////////////////////////
//End of Implementation
////////////////////////////////////////////////////