mirror of
https://github.com/openhwgroup/cva5.git
synced 2025-04-24 14:08:57 -04:00
Merge branch 'master' of gitlab.com:sfu-rcl/Taiga-dev
This commit is contained in:
Eric Matthews
commit
8aa593807d
7 changed files with 38599 additions and 4908 deletions
|
|
@ -2,6 +2,141 @@ Creating a Project for the Zedboard
|
|||
================
|
||||
|
||||
|
||||
1. Select the zedboard as your board in Vivado
|
||||
2. import the provided board constraints (.xdc file)
|
||||
|
||||
Building the core on the Zedboard
|
||||
-----
|
||||
Tested on Vivado 2018.3 on a Linux System
|
||||
### Building Taiga and Local Memory IP Cores
|
||||
In Vivado's TCL Console, change its directory to **within the cloned Taiga repository**:
|
||||
|
||||
cd <path to Taiga repo location>/Taiga
|
||||
|
||||
Build the Taiga IP Package by calling:
|
||||
|
||||
source scripts/xilinx/taiga_wrapper_IP.tcl
|
||||
|
||||
Build the Local Memory Package by calling:
|
||||
|
||||
source scripts/xilinx/local_memory_IP.tcl
|
||||
|
||||
These commands will create separate Vivado projects. Check if the packaging was successful, in the "Package IP" tab, navigate to the "Review and Package", a succesfully built IP core with have a Re-Package IP button at the bottom.
|
||||
|
||||
Both a Successful and failed build will create IP core folders(taiga_wrapper_IP and local_memory_IP) within the Taiga directory.
|
||||
|
||||
Note: If for some reason, it neccesary to run the scripts again, always delete the the IP core folder of the core that will be rebuilt, as Vivado is unable to overwrite these files otherwise.
|
||||
|
||||
|
||||
### Adding Taiga and Local Memory IP Cores to the project
|
||||
In either the existing Vivado project or a new Vivado project configured to run on a zedBoard. If starting a new project make sure to add the .xdc file provided as constraints and choose zedBoard as the project board.
|
||||
|
||||
Open the "IP Catalog" and add the IPs, by right-clicking on the Catalog Window, select "Add Repository..." and direct it to the Taiga Repository.
|
||||
|
||||
There should now be a User Repository that contains the cores:
|
||||
|
||||
local_mem_v1_0 and taiga_wrapper_xilinx_v1_0
|
||||
|
||||
|
||||
### Creating the Hardware Block Diagram and configuring IP Cores:
|
||||
Create a new Block Design by selecting "Create Block Design" in Vivado's Flow Navigator.
|
||||
Add the following IP cores:
|
||||
|
||||
1. taiga_wrapper_xilinx_v1_0
|
||||
2. local_mem_v1_0
|
||||
3. ZYNQ7 Processing System
|
||||
4. Processor System Reset
|
||||
5. AXI UART16550
|
||||
Note: There will be an AXI Interconnect added later on, but it has to be done after all other cores have been connected.
|
||||
|
||||
Configure the **Local Memory** to use a Preloaded File, by double-cliking on the core and setting "Use Preload File" to 1 and copy the file path to the .hw_init file provided.
|
||||
Leave "Ram Size" to 64.
|
||||
|
||||
|
||||
Configure the **ZYNQ7 Processing System** to output an FCLK_CLK of 100Mhz. This can be set in the IP's "Clock Configuration" under "PL Fabric Clocks:. Ensure there is at least 1 FCLK enabled and its Requested Frequency is 100Mhz.
|
||||
|
||||
### Connecting the IP Cores Together:
|
||||
Connect the **FCLK_CLK** output from the ZYNQ to all the cores' clk input, connect it as well to the ZYNQ's M_AXI_GP0_ACLK and the Processor System Reset's slowest_sync_clk. This is done by hovering your mouse over the port until it changes to a pencil symbol then click and drag to the clk ports.
|
||||
|
||||
Connect the **FCLK_RESET_N** output from the ZYNQ to the Processor System Reset's ext_reset_in.
|
||||
|
||||
Connect the **perpheral_aresetn** output from the Processor System Reset to the AXI Uart's aresetn pins.
|
||||
|
||||
Connect the **perpheral_areset** output from the Processor System Reset to the Local Memory and Taiga's reset pins.
|
||||
|
||||
Connect the **instruction_bram and data_bram** output from Taiga to the Local Memory's portA and portB inputs, respectively.
|
||||
|
||||
Set the UART's **sin and sout** pins to external. This is done by expanding the UART output by clicking on the "+" Symbol right beside it then rightclicking on the sin and sout pin and selecting the "Make External Option". Change the name of the external port to "sin" and "sout" instead of "sin_0" and "sout_0".
|
||||
|
||||
|
||||
### Autogenerate the HDL Wrapper for this Block Design:
|
||||
Under Sources, right click on the design_1.bd file, and select generate HDL Wrapper and let Vivado auto-generate one.
|
||||
|
||||
Set the newly generated as the Top file which is one of the options if you right click on the HDL Wrapper.
|
||||
|
||||
### Adding and Connecting the AXI Interconnect IP Cores:
|
||||
The Interconnect **must be added after everything else has been setup and the HDL wrapper has been generated** to help mitigate some errors that prevent the synthesis of the system.
|
||||
|
||||
Add the core AXI Interconnect (Not AXI Smartconnect).
|
||||
|
||||
Configure the AXI Interconnect to use **"Maximize Performance" as its "Optimization Strategy"**. This requires the interconnect to **not** be a 1-to-1 interconnect even if functionally it only connects the Taiga core to the UART. This can be done by setting either the Number of Slave or Master Interfaces to 2.
|
||||
|
||||
This was done because Vivado would optimized neccesarry signals away that would cause the interconnect to fail to transfer requests from the Taiga to the UART. This is the same reason as to why the AXI Smartconnect is not used.
|
||||
|
||||
Connect the **interconnect_aresetn** output from the Processor System Reset to the AXI Interconnect aresetn pins.
|
||||
|
||||
Connect the **m_axi** output from Taiga to the AXI Interconnect's S00_AXI input.
|
||||
|
||||
Connect the **M00_AXI** output from the AXI Interconnect to the UART's S_AXI input.
|
||||
|
||||
Set the UART's **slave address** to 0x6000_0000. This is done by Navigating to the Address Editor, finding "S_AXI" under taiga_wrapper_xilinx_0 -> m_axi -> Unmapped Slaves, righting clicking and "Assign Address". Then changing "Offset Address" to 0x6000_0000. Range can stay at 64K.
|
||||
|
||||
This is an approximation of what the connections should look like:
|
||||
|
||||
|
||||
### Sythesize Design:
|
||||
From the Flow Navigator, run Generate Bitstream.
|
||||
|
||||
### Bringing the Zedboard out of reset:
|
||||
This must be done each time to board is turned on or if the processor clocks were changed. If the zedBoard will be programmed through Xilinx SDK and not Vivado, this is not needed.
|
||||
|
||||
It must be done **after the synthesis** phase as the required file will be updated then.
|
||||
|
||||
Find the path to processing system IP core within the Vivado project directory. You are trying to look for ps7_init.tcl It will often look something like:
|
||||
|
||||
<path to Vivado project>/Taiga.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init.tcl
|
||||
|
||||
in the terminal you sourced and launched vivado, open xsdb. Input the follow commands:
|
||||
|
||||
connect
|
||||
target 1
|
||||
rst
|
||||
source <path to Vivado project>/Taiga.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_1/ps7_init.tcl
|
||||
ps7_init
|
||||
ps7_post_config
|
||||
|
||||
### Connected the UART through a PMOD:
|
||||
This project is set to use a serial PMOD connected to JA ports on the zedBoard. Connect the UART PMOD to your PC. Use your software of choice to listen on the apporpriate port with a 115200 Baud Rate.
|
||||
|
||||
A simple one to use is "screen" which can be installed on most systems.
|
||||
|
||||
Use the command:
|
||||
screen /dev/ttyUSB0 115200
|
||||
|
||||
Note: **ttyUSB0 might be different** on your setup depending on how you choice to connect the UART. You also might have to run it as root.
|
||||
|
||||
This is where the UART output can be seen.
|
||||
|
||||
### Program the ZedBoard:
|
||||
Program the ZedBoard with the generated bitstream. This can be done from the Flow Navigator, select Hardware Manager. Press the "Auto Connect button".
|
||||
|
||||
rightclick on the xc7z020_1 and select "Program Device". Confirm that it is the correct bitstream file, then click program. This will begin running the binnaries loaded onto the local memory. By default, it will be running the Dhrystone benchmarks.
|
||||
|
||||
|
||||
[OLD]Creating a Project for the Zedboard
|
||||
================
|
||||
|
||||
|
||||
1. Select the zedboard as your board in Vivado and import standard board constraints
|
||||
2. Add Taiga core and l2 arbiter sources to the project
|
||||
3. Add the taiga_wrapper.sv from the zedboard directory
|
||||
|
|
@ -84,15 +219,3 @@ Here is an example set of inputs for the script:
|
|||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
20910
examples/zedboard/dhrystone.riscv.hw_init
Executable file → Normal file
20910
examples/zedboard/dhrystone.riscv.hw_init
Executable file → Normal file
File diff suppressed because it is too large
Load diff
21650
examples/zedboard/dhrystone.riscv.sim_init
Executable file → Normal file
21650
examples/zedboard/dhrystone.riscv.sim_init
Executable file → Normal file
File diff suppressed because it is too large
Load diff
BIN
examples/zedboard/xilinx_wiring_sample.png
Normal file
BIN
examples/zedboard/xilinx_wiring_sample.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 68 KiB |
374
examples/zedboard/zedboard.xdc
Normal file
374
examples/zedboard/zedboard.xdc
Normal file
|
|
@ -0,0 +1,374 @@
|
|||
# ----------------------------------------------------------------------------
|
||||
# _____
|
||||
# / # /____ \____
|
||||
# / \===\ \==/
|
||||
# /___\===\___\/ AVNET Design Resource Center
|
||||
# \======/ www.em.avnet.com/drc
|
||||
# \====/
|
||||
# ----------------------------------------------------------------------------
|
||||
#
|
||||
# Created With Avnet UCF Generator V0.4.0
|
||||
# Date: Saturday, June 30, 2012
|
||||
# Time: 12:18:55 AM
|
||||
#
|
||||
# This design is the property of Avnet. Publication of this
|
||||
# design is not authorized without written consent from Avnet.
|
||||
#
|
||||
# Please direct any questions to:
|
||||
# ZedBoard.org Community Forums
|
||||
# http://www.zedboard.org
|
||||
#
|
||||
# Disclaimer:
|
||||
# Avnet, Inc. makes no warranty for the use of this code or design.
|
||||
# This code is provided "As Is". Avnet, Inc assumes no responsibility for
|
||||
# any errors, which may appear in this code, nor does it make a commitment
|
||||
# to update the information contained herein. Avnet, Inc specifically
|
||||
# disclaims any implied warranties of fitness for a particular purpose.
|
||||
# Copyright(c) 2012 Avnet, Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
# ----------------------------------------------------------------------------
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 10 August 2012
|
||||
# IO standards based upon Bank 34 and Bank 35 Vcco supply options of 1.8V,
|
||||
# 2.5V, or 3.3V are possible based upon the Vadj jumper (J18) settings.
|
||||
# By default, Vadj is expected to be set to 1.8V but if a different
|
||||
# voltage is used for a particular design, then the corresponding IO
|
||||
# standard within this UCF should also be updated to reflect the actual
|
||||
# Vadj jumper selection.
|
||||
#
|
||||
# 09 September 2012
|
||||
# Net names are not allowed to contain hyphen characters '-' since this
|
||||
# is not a legal VHDL87 or Verilog character within an identifier.
|
||||
# HDL net names are adjusted to contain no hyphen characters '-' but
|
||||
# rather use underscore '_' characters. Comment net name with the hyphen
|
||||
# characters will remain in place since these are intended to match the
|
||||
# schematic net names in order to better enable schematic search.
|
||||
#
|
||||
# 17 April 2014
|
||||
# Pin constraint for toggle switch SW7 was corrected to M15 location.
|
||||
#
|
||||
# 16 April 2015
|
||||
# Corrected the way that entire banks are assigned to a particular IO
|
||||
# standard so that it works with more recent versions of Vivado Design
|
||||
# Suite and moved the IO standard constraints to the end of the file
|
||||
# along with some better organization and notes like we do with our SOMs.
|
||||
#
|
||||
# 6 June 2016
|
||||
# Corrected error in signal name for package pin N19 (FMC Expansion Connector)
|
||||
#
|
||||
#
|
||||
# ----------------------------------------------------------------------------
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# Audio Codec - Bank 13
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN AB1 [get_ports {AC_ADR0}]; # "AC-ADR0"
|
||||
#set_property PACKAGE_PIN Y5 [get_ports {AC_ADR1}]; # "AC-ADR1"
|
||||
#set_property PACKAGE_PIN Y8 [get_ports {SDATA_O}]; # "AC-GPIO0"
|
||||
#set_property PACKAGE_PIN AA7 [get_ports {SDATA_I}]; # "AC-GPIO1"
|
||||
#set_property PACKAGE_PIN AA6 [get_ports {BCLK_O}]; # "AC-GPIO2"
|
||||
#set_property PACKAGE_PIN Y6 [get_ports {LRCLK_O}]; # "AC-GPIO3"
|
||||
#set_property PACKAGE_PIN AB2 [get_ports {MCLK_O}]; # "AC-MCLK"
|
||||
#set_property PACKAGE_PIN AB4 [get_ports {iic_rtl_scl_io}]; # "AC-SCK"
|
||||
#set_property PACKAGE_PIN AB5 [get_ports {iic_rtl_sda_io}]; # "AC-SDA"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# Clock Source - Bank 13
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN Y9 [get_ports axi_clk]
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# JA Pmod - Bank 13
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN Y11 [get_ports {JA1}]; # "JA1"
|
||||
#set_property PACKAGE_PIN AA8 [get_ports {JA10}]; # "JA10"
|
||||
#set_property PACKAGE_PIN AA11 [get_ports {JA2}]; # "JA2"
|
||||
set_property PACKAGE_PIN Y10 [get_ports sin]
|
||||
set_property PACKAGE_PIN AA9 [get_ports sout]
|
||||
#set_property PACKAGE_PIN AB11 [get_ports {JA7}]; # "JA7"
|
||||
#set_property PACKAGE_PIN AB10 [get_ports {JA8}]; # "JA8"
|
||||
#set_property PACKAGE_PIN AB9 [get_ports {JA9}]; # "JA9"
|
||||
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# JB Pmod - Bank 13
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN W12 [get_ports {JB1}]; # "JB1"
|
||||
#set_property PACKAGE_PIN W11 [get_ports {JB2}]; # "JB2"
|
||||
#set_property PACKAGE_PIN V10 [get_ports {JB3}]; # "JB3"
|
||||
#set_property PACKAGE_PIN W8 [get_ports {JB4}]; # "JB4"
|
||||
#set_property PACKAGE_PIN V12 [get_ports {JB7}]; # "JB7"
|
||||
#set_property PACKAGE_PIN W10 [get_ports {JB8}]; # "JB8"
|
||||
#set_property PACKAGE_PIN V9 [get_ports {JB9}]; # "JB9"
|
||||
#set_property PACKAGE_PIN V8 [get_ports {JB10}]; # "JB10"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# JC Pmod - Bank 13
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN AB6 [get_ports {JC1_N}]; # "JC1_N"
|
||||
#set_property PACKAGE_PIN AB7 [get_ports {JC1_P}]; # "JC1_P"
|
||||
#set_property PACKAGE_PIN AA4 [get_ports {JC2_N}]; # "JC2_N"
|
||||
#set_property PACKAGE_PIN Y4 [get_ports {JC2_P}]; # "JC2_P"
|
||||
#set_property PACKAGE_PIN T6 [get_ports {JC3_N}]; # "JC3_N"
|
||||
#set_property PACKAGE_PIN R6 [get_ports {JC3_P}]; # "JC3_P"
|
||||
#set_property PACKAGE_PIN U4 [get_ports {JC4_N}]; # "JC4_N"
|
||||
#set_property PACKAGE_PIN T4 [get_ports {JC4_P}]; # "JC4_P"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# JD Pmod - Bank 13
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN W7 [get_ports {JD1_N}]; # "JD1_N"
|
||||
#set_property PACKAGE_PIN V7 [get_ports {JD1_P}]; # "JD1_P"
|
||||
#set_property PACKAGE_PIN V4 [get_ports {JD2_N}]; # "JD2_N"
|
||||
#set_property PACKAGE_PIN V5 [get_ports {JD2_P}]; # "JD2_P"
|
||||
#set_property PACKAGE_PIN W5 [get_ports {JD3_N}]; # "JD3_N"
|
||||
#set_property PACKAGE_PIN W6 [get_ports {JD3_P}]; # "JD3_P"
|
||||
#set_property PACKAGE_PIN U5 [get_ports {JD4_N}]; # "JD4_N"
|
||||
#set_property PACKAGE_PIN U6 [get_ports {JD4_P}]; # "JD4_P"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# OLED Display - Bank 13
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN U10 [get_ports {OLED_DC}]; # "OLED-DC"
|
||||
#set_property PACKAGE_PIN U9 [get_ports {OLED_RES}]; # "OLED-RES"
|
||||
#set_property PACKAGE_PIN AB12 [get_ports {OLED_SCLK}]; # "OLED-SCLK"
|
||||
#set_property PACKAGE_PIN AA12 [get_ports {OLED_SDIN}]; # "OLED-SDIN"
|
||||
#set_property PACKAGE_PIN U11 [get_ports {OLED_VBAT}]; # "OLED-VBAT"
|
||||
#set_property PACKAGE_PIN U12 [get_ports {OLED_VDD}]; # "OLED-VDD"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# HDMI Output - Bank 33
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN W18 [get_ports {HD_CLK}]; # "HD-CLK"
|
||||
#set_property PACKAGE_PIN Y13 [get_ports {HD_D0}]; # "HD-D0"
|
||||
#set_property PACKAGE_PIN AA13 [get_ports {HD_D1}]; # "HD-D1"
|
||||
#set_property PACKAGE_PIN W13 [get_ports {HD_D10}]; # "HD-D10"
|
||||
#set_property PACKAGE_PIN W15 [get_ports {HD_D11}]; # "HD-D11"
|
||||
#set_property PACKAGE_PIN V15 [get_ports {HD_D12}]; # "HD-D12"
|
||||
#set_property PACKAGE_PIN U17 [get_ports {HD_D13}]; # "HD-D13"
|
||||
#set_property PACKAGE_PIN V14 [get_ports {HD_D14}]; # "HD-D14"
|
||||
#set_property PACKAGE_PIN V13 [get_ports {HS_D15}]; # "HD-D15"
|
||||
#set_property PACKAGE_PIN AA14 [get_ports {HD_D2}]; # "HD-D2"
|
||||
#set_property PACKAGE_PIN Y14 [get_ports {HD_D3}]; # "HD-D3"
|
||||
#set_property PACKAGE_PIN AB15 [get_ports {HD_D4}]; # "HD-D4"
|
||||
#set_property PACKAGE_PIN AB16 [get_ports {HD_D5}]; # "HD-D5"
|
||||
#set_property PACKAGE_PIN AA16 [get_ports {HD_D6}]; # "HD-D6"
|
||||
#set_property PACKAGE_PIN AB17 [get_ports {HD_D7}]; # "HD-D7"
|
||||
#set_property PACKAGE_PIN AA17 [get_ports {HD_D8}]; # "HD-D8"
|
||||
#set_property PACKAGE_PIN Y15 [get_ports {HD_D9}]; # "HD-D9"
|
||||
#set_property PACKAGE_PIN U16 [get_ports {HD_DE}]; # "HD-DE"
|
||||
#set_property PACKAGE_PIN V17 [get_ports {HD_HSYNC}]; # "HD-HSYNC"
|
||||
#set_property PACKAGE_PIN W16 [get_ports {HD_INT}]; # "HD-INT"
|
||||
#set_property PACKAGE_PIN AA18 [get_ports {HD_SCL}]; # "HD-SCL"
|
||||
#set_property PACKAGE_PIN Y16 [get_ports {HD_SDA}]; # "HD-SDA"
|
||||
#set_property PACKAGE_PIN U15 [get_ports {HD_SPDIF}]; # "HD-SPDIF"
|
||||
#set_property PACKAGE_PIN Y18 [get_ports {HD_SPDIFO}]; # "HD-SPDIFO"
|
||||
#set_property PACKAGE_PIN W17 [get_ports {HD_VSYNC}]; # "HD-VSYNC"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# User LEDs - Bank 33
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN T22 [get_ports {LD0}]; # "LD0"
|
||||
#set_property PACKAGE_PIN T21 [get_ports {LD1}]; # "LD1"
|
||||
#set_property PACKAGE_PIN U22 [get_ports {LD2}]; # "LD2"
|
||||
#set_property PACKAGE_PIN U21 [get_ports {LD3}]; # "LD3"
|
||||
#set_property PACKAGE_PIN V22 [get_ports {LD4}]; # "LD4"
|
||||
#set_property PACKAGE_PIN W22 [get_ports {LD5}]; # "LD5"
|
||||
#set_property PACKAGE_PIN U19 [get_ports {LD6}]; # "LD6"
|
||||
#set_property PACKAGE_PIN U14 [get_ports {LD7}]; # "LD7"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# VGA Output - Bank 33
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN Y21 [get_ports {VGA_B1}]; # "VGA-B1"
|
||||
#set_property PACKAGE_PIN Y20 [get_ports {VGA_B2}]; # "VGA-B2"
|
||||
#set_property PACKAGE_PIN AB20 [get_ports {VGA_B3}]; # "VGA-B3"
|
||||
#set_property PACKAGE_PIN AB19 [get_ports {VGA_B4}]; # "VGA-B4"
|
||||
#set_property PACKAGE_PIN AB22 [get_ports {VGA_G1}]; # "VGA-G1"
|
||||
#set_property PACKAGE_PIN AA22 [get_ports {VGA_G2}]; # "VGA-G2"
|
||||
#set_property PACKAGE_PIN AB21 [get_ports {VGA_G3}]; # "VGA-G3"
|
||||
#set_property PACKAGE_PIN AA21 [get_ports {VGA_G4}]; # "VGA-G4"
|
||||
#set_property PACKAGE_PIN AA19 [get_ports {VGA_HS}]; # "VGA-HS"
|
||||
#set_property PACKAGE_PIN V20 [get_ports {VGA_R1}]; # "VGA-R1"
|
||||
#set_property PACKAGE_PIN U20 [get_ports {VGA_R2}]; # "VGA-R2"
|
||||
#set_property PACKAGE_PIN V19 [get_ports {VGA_R3}]; # "VGA-R3"
|
||||
#set_property PACKAGE_PIN V18 [get_ports {VGA_R4}]; # "VGA-R4"
|
||||
#set_property PACKAGE_PIN Y19 [get_ports {VGA_VS}]; # "VGA-VS"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# User Push Buttons - Bank 34
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN P16 [get_ports resetn]
|
||||
#set_property PACKAGE_PIN R16 [get_ports {BTND}]; # "BTND"
|
||||
#set_property PACKAGE_PIN N15 [get_ports {BTNL}]; # "BTNL"
|
||||
#set_property PACKAGE_PIN R18 [get_ports {BTNR}]; # "BTNR"
|
||||
#set_property PACKAGE_PIN T18 [get_ports {BTNU}]; # "BTNU"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# USB OTG Reset - Bank 34
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN L16 [get_ports {OTG_VBUSOC}]; # "OTG-VBUSOC"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# XADC GIO - Bank 34
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN H15 [get_ports {XADC_GIO0}]; # "XADC-GIO0"
|
||||
#set_property PACKAGE_PIN R15 [get_ports {XADC_GIO1}]; # "XADC-GIO1"
|
||||
#set_property PACKAGE_PIN K15 [get_ports {XADC_GIO2}]; # "XADC-GIO2"
|
||||
#set_property PACKAGE_PIN J15 [get_ports {XADC_GIO3}]; # "XADC-GIO3"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# Miscellaneous - Bank 34
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN K16 [get_ports {PUDC_B}]; # "PUDC_B"
|
||||
|
||||
## ----------------------------------------------------------------------------
|
||||
## USB OTG Reset - Bank 35
|
||||
## ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN G17 [get_ports {OTG_RESETN}]; # "OTG-RESETN"
|
||||
|
||||
## ----------------------------------------------------------------------------
|
||||
## User DIP Switches - Bank 35
|
||||
## ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN F22 [get_ports {SW0}]; # "SW0"
|
||||
#set_property PACKAGE_PIN G22 [get_ports {SW1}]; # "SW1"
|
||||
#set_property PACKAGE_PIN H22 [get_ports {SW2}]; # "SW2"
|
||||
#set_property PACKAGE_PIN F21 [get_ports {SW3}]; # "SW3"
|
||||
#set_property PACKAGE_PIN H19 [get_ports {SW4}]; # "SW4"
|
||||
#set_property PACKAGE_PIN H18 [get_ports {SW5}]; # "SW5"
|
||||
#set_property PACKAGE_PIN H17 [get_ports {SW6}]; # "SW6"
|
||||
#set_property PACKAGE_PIN M15 [get_ports {SW7}]; # "SW7"
|
||||
|
||||
## ----------------------------------------------------------------------------
|
||||
## XADC AD Channels - Bank 35
|
||||
## ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN E16 [get_ports {AD0N_R}]; # "XADC-AD0N-R"
|
||||
#set_property PACKAGE_PIN F16 [get_ports {AD0P_R}]; # "XADC-AD0P-R"
|
||||
#set_property PACKAGE_PIN D17 [get_ports {AD8N_N}]; # "XADC-AD8N-R"
|
||||
#set_property PACKAGE_PIN D16 [get_ports {AD8P_R}]; # "XADC-AD8P-R"
|
||||
|
||||
## ----------------------------------------------------------------------------
|
||||
## FMC Expansion Connector - Bank 13
|
||||
## ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN R7 [get_ports {FMC_SCL}]; # "FMC-SCL"
|
||||
#set_property PACKAGE_PIN U7 [get_ports {FMC_SDA}]; # "FMC-SDA"
|
||||
|
||||
## ----------------------------------------------------------------------------
|
||||
## FMC Expansion Connector - Bank 33
|
||||
## ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN AB14 [get_ports {FMC_PRSNT}]; # "FMC-PRSNT"
|
||||
|
||||
## ----------------------------------------------------------------------------
|
||||
## FMC Expansion Connector - Bank 34
|
||||
## ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN L19 [get_ports {FMC_CLK0_N}]; # "FMC-CLK0_N"
|
||||
#set_property PACKAGE_PIN L18 [get_ports {FMC_CLK0_P}]; # "FMC-CLK0_P"
|
||||
#set_property PACKAGE_PIN M20 [get_ports {FMC_LA00_CC_N}]; # "FMC-LA00_CC_N"
|
||||
#set_property PACKAGE_PIN M19 [get_ports {FMC_LA00_CC_P}]; # "FMC-LA00_CC_P"
|
||||
#set_property PACKAGE_PIN N20 [get_ports {FMC_LA01_CC_N}]; # "FMC-LA01_CC_N"
|
||||
#set_property PACKAGE_PIN N19 [get_ports {FMC_LA01_CC_P}]; # "FMC-LA01_CC_P" - corrected 6/6/16 GE
|
||||
#set_property PACKAGE_PIN P18 [get_ports {FMC_LA02_N}]; # "FMC-LA02_N"
|
||||
#set_property PACKAGE_PIN P17 [get_ports {FMC_LA02_P}]; # "FMC-LA02_P"
|
||||
#set_property PACKAGE_PIN P22 [get_ports {FMC_LA03_N}]; # "FMC-LA03_N"
|
||||
#set_property PACKAGE_PIN N22 [get_ports {FMC_LA03_P}]; # "FMC-LA03_P"
|
||||
#set_property PACKAGE_PIN M22 [get_ports {FMC_LA04_N}]; # "FMC-LA04_N"
|
||||
#set_property PACKAGE_PIN M21 [get_ports {FMC_LA04_P}]; # "FMC-LA04_P"
|
||||
#set_property PACKAGE_PIN K18 [get_ports {FMC_LA05_N}]; # "FMC-LA05_N"
|
||||
#set_property PACKAGE_PIN J18 [get_ports {FMC_LA05_P}]; # "FMC-LA05_P"
|
||||
#set_property PACKAGE_PIN L22 [get_ports {FMC_LA06_N}]; # "FMC-LA06_N"
|
||||
#set_property PACKAGE_PIN L21 [get_ports {FMC_LA06_P}]; # "FMC-LA06_P"
|
||||
#set_property PACKAGE_PIN T17 [get_ports {FMC_LA07_N}]; # "FMC-LA07_N"
|
||||
#set_property PACKAGE_PIN T16 [get_ports {FMC_LA07_P}]; # "FMC-LA07_P"
|
||||
#set_property PACKAGE_PIN J22 [get_ports {FMC_LA08_N}]; # "FMC-LA08_N"
|
||||
#set_property PACKAGE_PIN J21 [get_ports {FMC_LA08_P}]; # "FMC-LA08_P"
|
||||
#set_property PACKAGE_PIN R21 [get_ports {FMC_LA09_N}]; # "FMC-LA09_N"
|
||||
#set_property PACKAGE_PIN R20 [get_ports {FMC_LA09_P}]; # "FMC-LA09_P"
|
||||
#set_property PACKAGE_PIN T19 [get_ports {FMC_LA10_N}]; # "FMC-LA10_N"
|
||||
#set_property PACKAGE_PIN R19 [get_ports {FMC_LA10_P}]; # "FMC-LA10_P"
|
||||
#set_property PACKAGE_PIN N18 [get_ports {FMC_LA11_N}]; # "FMC-LA11_N"
|
||||
#set_property PACKAGE_PIN N17 [get_ports {FMC_LA11_P}]; # "FMC-LA11_P"
|
||||
#set_property PACKAGE_PIN P21 [get_ports {FMC_LA12_N}]; # "FMC-LA12_N"
|
||||
#set_property PACKAGE_PIN P20 [get_ports {FMC_LA12_P}]; # "FMC-LA12_P"
|
||||
#set_property PACKAGE_PIN M17 [get_ports {FMC_LA13_N}]; # "FMC-LA13_N"
|
||||
#set_property PACKAGE_PIN L17 [get_ports {FMC_LA13_P}]; # "FMC-LA13_P"
|
||||
#set_property PACKAGE_PIN K20 [get_ports {FMC_LA14_N}]; # "FMC-LA14_N"
|
||||
#set_property PACKAGE_PIN K19 [get_ports {FMC_LA14_P}]; # "FMC-LA14_P"
|
||||
#set_property PACKAGE_PIN J17 [get_ports {FMC_LA15_N}]; # "FMC-LA15_N"
|
||||
#set_property PACKAGE_PIN J16 [get_ports {FMC_LA15_P}]; # "FMC-LA15_P"
|
||||
#set_property PACKAGE_PIN K21 [get_ports {FMC_LA16_N}]; # "FMC-LA16_N"
|
||||
#set_property PACKAGE_PIN J20 [get_ports {FMC_LA16_P}]; # "FMC-LA16_P"
|
||||
|
||||
## ----------------------------------------------------------------------------
|
||||
## FMC Expansion Connector - Bank 35
|
||||
## ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN C19 [get_ports {FMC_CLK1_N}]; # "FMC-CLK1_N"
|
||||
#set_property PACKAGE_PIN D18 [get_ports {FMC_CLK1_P}]; # "FMC-CLK1_P"
|
||||
#set_property PACKAGE_PIN B20 [get_ports {FMC_LA17_CC_N}]; # "FMC-LA17_CC_N"
|
||||
#set_property PACKAGE_PIN B19 [get_ports {FMC_LA17_CC_P}]; # "FMC-LA17_CC_P"
|
||||
#set_property PACKAGE_PIN C20 [get_ports {FMC_LA18_CC_N}]; # "FMC-LA18_CC_N"
|
||||
#set_property PACKAGE_PIN D20 [get_ports {FMC_LA18_CC_P}]; # "FMC-LA18_CC_P"
|
||||
#set_property PACKAGE_PIN G16 [get_ports {FMC_LA19_N}]; # "FMC-LA19_N"
|
||||
#set_property PACKAGE_PIN G15 [get_ports {FMC_LA19_P}]; # "FMC-LA19_P"
|
||||
#set_property PACKAGE_PIN G21 [get_ports {FMC_LA20_N}]; # "FMC-LA20_N"
|
||||
#set_property PACKAGE_PIN G20 [get_ports {FMC_LA20_P}]; # "FMC-LA20_P"
|
||||
#set_property PACKAGE_PIN E20 [get_ports {FMC_LA21_N}]; # "FMC-LA21_N"
|
||||
#set_property PACKAGE_PIN E19 [get_ports {FMC_LA21_P}]; # "FMC-LA21_P"
|
||||
#set_property PACKAGE_PIN F19 [get_ports {FMC_LA22_N}]; # "FMC-LA22_N"
|
||||
#set_property PACKAGE_PIN G19 [get_ports {FMC_LA22_P}]; # "FMC-LA22_P"
|
||||
#set_property PACKAGE_PIN D15 [get_ports {FMC_LA23_N}]; # "FMC-LA23_N"
|
||||
#set_property PACKAGE_PIN E15 [get_ports {FMC_LA23_P}]; # "FMC-LA23_P"
|
||||
#set_property PACKAGE_PIN A19 [get_ports {FMC_LA24_N}]; # "FMC-LA24_N"
|
||||
#set_property PACKAGE_PIN A18 [get_ports {FMC_LA24_P}]; # "FMC-LA24_P"
|
||||
#set_property PACKAGE_PIN C22 [get_ports {FMC_LA25_N}]; # "FMC-LA25_N"
|
||||
#set_property PACKAGE_PIN D22 [get_ports {FMC_LA25_P}]; # "FMC-LA25_P"
|
||||
#set_property PACKAGE_PIN E18 [get_ports {FMC_LA26_N}]; # "FMC-LA26_N"
|
||||
#set_property PACKAGE_PIN F18 [get_ports {FMC_LA26_P}]; # "FMC-LA26_P"
|
||||
#set_property PACKAGE_PIN D21 [get_ports {FMC_LA27_N}]; # "FMC-LA27_N"
|
||||
#set_property PACKAGE_PIN E21 [get_ports {FMC_LA27_P}]; # "FMC-LA27_P"
|
||||
#set_property PACKAGE_PIN A17 [get_ports {FMC_LA28_N}]; # "FMC-LA28_N"
|
||||
#set_property PACKAGE_PIN A16 [get_ports {FMC_LA28_P}]; # "FMC-LA28_P"
|
||||
#set_property PACKAGE_PIN C18 [get_ports {FMC_LA29_N}]; # "FMC-LA29_N"
|
||||
#set_property PACKAGE_PIN C17 [get_ports {FMC_LA29_P}]; # "FMC-LA29_P"
|
||||
#set_property PACKAGE_PIN B15 [get_ports {FMC_LA30_N}]; # "FMC-LA30_N"
|
||||
#set_property PACKAGE_PIN C15 [get_ports {FMC_LA30_P}]; # "FMC-LA30_P"
|
||||
#set_property PACKAGE_PIN B17 [get_ports {FMC_LA31_N}]; # "FMC-LA31_N"
|
||||
#set_property PACKAGE_PIN B16 [get_ports {FMC_LA31_P}]; # "FMC-LA31_P"
|
||||
#set_property PACKAGE_PIN A22 [get_ports {FMC_LA32_N}]; # "FMC-LA32_N"
|
||||
#set_property PACKAGE_PIN A21 [get_ports {FMC_LA32_P}]; # "FMC-LA32_P"
|
||||
#set_property PACKAGE_PIN B22 [get_ports {FMC_LA33_N}]; # "FMC-LA33_N"
|
||||
#set_property PACKAGE_PIN B21 [get_ports {FMC_LA33_P}]; # "FMC-LA33_P"
|
||||
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# IOSTANDARD Constraints
|
||||
#
|
||||
# Note that these IOSTANDARD constraints are applied to all IOs currently
|
||||
# assigned within an I/O bank. If these IOSTANDARD constraints are
|
||||
# evaluated prior to other PACKAGE_PIN constraints being applied, then
|
||||
# the IOSTANDARD specified will likely not be applied properly to those
|
||||
# pins. Therefore, bank wide IOSTANDARD constraints should be placed
|
||||
# within the XDC file in a location that is evaluated AFTER all
|
||||
# PACKAGE_PIN constraints within the target bank have been evaluated.
|
||||
#
|
||||
# Un-comment one or more of the following IOSTANDARD constraints according to
|
||||
# the bank pin assignments that are required within a design.
|
||||
# ----------------------------------------------------------------------------
|
||||
|
||||
# Note that the bank voltage for IO Bank 33 is fixed to 3.3V on ZedBoard.
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 33]];
|
||||
|
||||
# Set the bank voltage for IO Bank 34 to 1.8V by default.
|
||||
# set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 34]];
|
||||
# set_property IOSTANDARD LVCMOS25 [get_ports -of_objects [get_iobanks 34]];
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 34]]
|
||||
|
||||
# Set the bank voltage for IO Bank 35 to 1.8V by default.
|
||||
# set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 35]];
|
||||
# set_property IOSTANDARD LVCMOS25 [get_ports -of_objects [get_iobanks 35]];
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 35]];
|
||||
|
||||
# Note that the bank voltage for IO Bank 13 is fixed to 3.3V on ZedBoard.
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]
|
||||
165
scripts/xilinx/local_memory_IP.tcl
Normal file
165
scripts/xilinx/local_memory_IP.tcl
Normal file
|
|
@ -0,0 +1,165 @@
|
|||
#*****************************************************************************************
|
||||
# Vivado (TM) v2018.3 (64-bit)
|
||||
#
|
||||
# tmp_edit_project.tcl: Tcl script for re-creating project 'tmp_edit_project'
|
||||
#
|
||||
# Generated by Vivado on Thu Dec 20 14:43:20 PST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
#
|
||||
# This file contains the Vivado Tcl commands for re-creating the project to the state*
|
||||
# when this script was generated. In order to re-create the project, please source this
|
||||
# file in the Vivado Tcl Shell.
|
||||
#
|
||||
# * Note that the runs in the created project will be configured the same way as the
|
||||
# original project, however they will not be launched automatically. To regenerate the
|
||||
# run results please launch the synthesis/implementation runs as needed.
|
||||
#
|
||||
#*****************************************************************************************
|
||||
|
||||
# Set the reference directory for source file relative paths (by default the value is script directory path)
|
||||
set origin_dir "."
|
||||
#set origin_dir [file dirname [info script]]
|
||||
|
||||
# Use origin directory path location variable, if specified in the tcl shell
|
||||
if { [info exists ::origin_dir_loc] } {
|
||||
set origin_dir $::origin_dir_loc
|
||||
}
|
||||
|
||||
# Set the project name
|
||||
set _xil_proj_name_ "local_memory_IP"
|
||||
|
||||
# Use project name variable, if specified in the tcl shell
|
||||
if { [info exists ::user_project_name] } {
|
||||
set _xil_proj_name_ $::user_project_name
|
||||
}
|
||||
|
||||
variable script_file
|
||||
set script_file "local_memory_IP.tcl"
|
||||
|
||||
# Help information for this script
|
||||
proc print_help {} {
|
||||
variable script_file
|
||||
puts "\nDescription:"
|
||||
puts "Recreate a Vivado project from this script. The created project will be"
|
||||
puts "functionally equivalent to the original project for which this script was"
|
||||
puts "generated. The script contains commands for creating a project, filesets,"
|
||||
puts "runs, adding/importing sources and setting properties on various objects.\n"
|
||||
puts "Syntax:"
|
||||
puts "$script_file"
|
||||
puts "$script_file -tclargs \[--origin_dir <path>\]"
|
||||
puts "$script_file -tclargs \[--project_name <name>\]"
|
||||
puts "$script_file -tclargs \[--help\]\n"
|
||||
puts "Usage:"
|
||||
puts "Name Description"
|
||||
puts "-------------------------------------------------------------------------"
|
||||
puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
|
||||
puts " origin_dir path value is \".\", otherwise, the value"
|
||||
puts " that was set with the \"-paths_relative_to\" switch"
|
||||
puts " when this script was generated.\n"
|
||||
puts "\[--project_name <name>\] Create project with the specified name. Default"
|
||||
puts " name is the name of the project from where this"
|
||||
puts " script was generated.\n"
|
||||
puts "\[--help\] Print help information for this script"
|
||||
puts "-------------------------------------------------------------------------\n"
|
||||
exit 0
|
||||
}
|
||||
|
||||
if { $::argc > 0 } {
|
||||
for {set i 0} {$i < $::argc} {incr i} {
|
||||
set option [string trim [lindex $::argv $i]]
|
||||
switch -regexp -- $option {
|
||||
"--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
|
||||
"--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
|
||||
"--help" { print_help }
|
||||
default {
|
||||
if { [regexp {^-} $option] } {
|
||||
puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
|
||||
return 1
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
# Set the directory path for the original project from where this script was exported
|
||||
#This is where the IP project gets stored ?
|
||||
set orig_proj_dir "[file normalize "$origin_dir/"]"
|
||||
|
||||
# Create project
|
||||
create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z020clg484-1
|
||||
|
||||
# Set the directory path for the new project
|
||||
set proj_dir [get_property directory [current_project]]
|
||||
|
||||
# Reconstruct message rules
|
||||
# None
|
||||
|
||||
# Set project properties
|
||||
set obj [current_project]
|
||||
set_property -name "board_part" -value "em.avnet.com:zed:part0:1.4" -objects $obj
|
||||
set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
|
||||
set_property -name "ip_cache_permissions" -value "read write" -objects $obj
|
||||
set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
|
||||
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
|
||||
set_property -name "simulator_language" -value "Mixed" -objects $obj
|
||||
set_property -name "target_language" -value "Verilog" -objects $obj
|
||||
|
||||
# Create 'sources_1' fileset (if not found)
|
||||
if {[string equal [get_filesets -quiet sources_1] ""]} {
|
||||
create_fileset -srcset sources_1
|
||||
}
|
||||
|
||||
#import all sources from taiga repo directory
|
||||
import_files -fileset [get_filesets sources_1] $origin_dir/local_memory
|
||||
import_files -norecurse $origin_dir/core/byte_en_BRAM.sv -force
|
||||
import_files -norecurse $origin_dir/core/xilinx/xilinx_byte_enable_ram.sv -force
|
||||
import_files -norecurse $origin_dir/core/taiga_config.sv -force
|
||||
import_files -norecurse $origin_dir/core/taiga_types.sv -force
|
||||
|
||||
# Set IP repository paths
|
||||
#set obj [get_filesets sources_1]
|
||||
#set_property "ip_repo_paths" "[file normalize "$origin_dir/Clean_Taiga_IP"]" $obj
|
||||
|
||||
# Rebuild user ip_repo's index before adding any source files
|
||||
update_ip_catalog -rebuild
|
||||
|
||||
# Add/Import constrs file and set constrs file properties
|
||||
|
||||
# Set 'sources_1' fileset file properties for remote files
|
||||
# None
|
||||
|
||||
# Set 'sources_1' fileset file properties for local files
|
||||
|
||||
# Set 'sources_1' fileset properties
|
||||
set obj [get_filesets sources_1]
|
||||
set_property -name "top" -value "local_mem" -objects $obj
|
||||
set_property -name "top_auto_set" -value "0" -objects $obj
|
||||
set_property -name "top_file" -value "${origin_dir}/local_memory/local_mem.sv" -objects $obj
|
||||
|
||||
|
||||
# Remove interface files for taiga
|
||||
puts "INFO: Project created:${_xil_proj_name_}"
|
||||
|
||||
##############IP Packaging########################################
|
||||
ipx::package_project -import_files -force -root_dir $proj_dir
|
||||
update_compile_order -fileset sources_1
|
||||
set_property core_revision 2 [ipx::current_core]
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
ipx::update_checksums [ipx::current_core]
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
|
||||
set_property ip_repo_paths $origin_dir/${_xil_proj_name_} [current_project]
|
||||
current_project $_xil_proj_name_
|
||||
update_ip_catalog
|
||||
|
||||
|
||||
update_compile_order -fileset sources_1
|
||||
ipx::merge_project_changes files [ipx::current_core]
|
||||
set_property core_revision 3 [ipx::current_core]
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
ipx::update_checksums [ipx::current_core]
|
||||
ipx::save_core [ipx::current_core]
|
||||
current_project local_memory_IP
|
||||
update_ip_catalog -rebuild -repo_path $origin_dir/${_xil_proj_name_}
|
||||
|
||||
261
scripts/xilinx/taiga_wrapper_IP.tcl
Normal file
261
scripts/xilinx/taiga_wrapper_IP.tcl
Normal file
|
|
@ -0,0 +1,261 @@
|
|||
#*****************************************************************************************
|
||||
# Vivado (TM) v2018.3 (64-bit)
|
||||
#
|
||||
# tmp_edit_project.tcl: Tcl script for re-creating project 'tmp_edit_project'
|
||||
#
|
||||
# Generated by Vivado on Thu Dec 20 14:43:20 PST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
#
|
||||
# This file contains the Vivado Tcl commands for re-creating the project to the state*
|
||||
# when this script was generated. In order to re-create the project, please source this
|
||||
# file in the Vivado Tcl Shell.
|
||||
#
|
||||
# * Note that the runs in the created project will be configured the same way as the
|
||||
# original project, however they will not be launched automatically. To regenerate the
|
||||
# run results please launch the synthesis/implementation runs as needed.
|
||||
#
|
||||
#*****************************************************************************************
|
||||
|
||||
# Set the reference directory for source file relative paths (by default the value is script directory path)
|
||||
set origin_dir "."
|
||||
#set origin_dir [file dirname [info script]]
|
||||
|
||||
# Use origin directory path location variable, if specified in the tcl shell
|
||||
if { [info exists ::origin_dir_loc] } {
|
||||
set origin_dir $::origin_dir_loc
|
||||
}
|
||||
|
||||
# Set the project name
|
||||
set _xil_proj_name_ "taiga_wrapper_IP"
|
||||
|
||||
# Use project name variable, if specified in the tcl shell
|
||||
if { [info exists ::user_project_name] } {
|
||||
set _xil_proj_name_ $::user_project_name
|
||||
}
|
||||
|
||||
variable script_file
|
||||
set script_file "taiga_wrapper_IP.tcl"
|
||||
|
||||
# Help information for this script
|
||||
proc print_help {} {
|
||||
variable script_file
|
||||
puts "\nDescription:"
|
||||
puts "Recreate a Vivado project from this script. The created project will be"
|
||||
puts "functionally equivalent to the original project for which this script was"
|
||||
puts "generated. The script contains commands for creating a project, filesets,"
|
||||
puts "runs, adding/importing sources and setting properties on various objects.\n"
|
||||
puts "Syntax:"
|
||||
puts "$script_file"
|
||||
puts "$script_file -tclargs \[--origin_dir <path>\]"
|
||||
puts "$script_file -tclargs \[--project_name <name>\]"
|
||||
puts "$script_file -tclargs \[--help\]\n"
|
||||
puts "Usage:"
|
||||
puts "Name Description"
|
||||
puts "-------------------------------------------------------------------------"
|
||||
puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
|
||||
puts " origin_dir path value is \".\", otherwise, the value"
|
||||
puts " that was set with the \"-paths_relative_to\" switch"
|
||||
puts " when this script was generated.\n"
|
||||
puts "\[--project_name <name>\] Create project with the specified name. Default"
|
||||
puts " name is the name of the project from where this"
|
||||
puts " script was generated.\n"
|
||||
puts "\[--help\] Print help information for this script"
|
||||
puts "-------------------------------------------------------------------------\n"
|
||||
exit 0
|
||||
}
|
||||
|
||||
if { $::argc > 0 } {
|
||||
for {set i 0} {$i < $::argc} {incr i} {
|
||||
set option [string trim [lindex $::argv $i]]
|
||||
switch -regexp -- $option {
|
||||
"--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
|
||||
"--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
|
||||
"--help" { print_help }
|
||||
default {
|
||||
if { [regexp {^-} $option] } {
|
||||
puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
|
||||
return 1
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
# Set the directory path for the original project from where this script was exported
|
||||
#This is where the IP project gets stored ?
|
||||
set orig_proj_dir "[file normalize "$origin_dir/"]"
|
||||
|
||||
# Create project
|
||||
create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z020clg484-1
|
||||
|
||||
# Set the directory path for the new project
|
||||
set proj_dir [get_property directory [current_project]]
|
||||
|
||||
# Reconstruct message rules
|
||||
# None
|
||||
|
||||
# Set project properties
|
||||
set obj [current_project]
|
||||
set_property -name "board_part" -value "em.avnet.com:zed:part0:1.4" -objects $obj
|
||||
set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
|
||||
set_property -name "ip_cache_permissions" -value "read write" -objects $obj
|
||||
set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
|
||||
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
|
||||
set_property -name "simulator_language" -value "Mixed" -objects $obj
|
||||
set_property -name "target_language" -value "Verilog" -objects $obj
|
||||
|
||||
# Create 'sources_1' fileset (if not found)
|
||||
if {[string equal [get_filesets -quiet sources_1] ""]} {
|
||||
create_fileset -srcset sources_1
|
||||
}
|
||||
|
||||
#import all sources from taiga repo directory
|
||||
#Zavier: Eric says we only want the wrapper, and whatever type/interface file we need at first.
|
||||
#The reasoning is: less files ati ntial package, less worry
|
||||
#import_files -fileset [get_filesets sources_1] $origin_dir/core
|
||||
#import_files -fileset [get_filesets sources_1] $origin_dir/l2_arbiter
|
||||
#import_files -fileset [get_filesets sources_1] $origin_dir/local_memory
|
||||
|
||||
import_files -norecurse $origin_dir/core/xilinx/taiga_wrapper_xilinx.sv -force
|
||||
import_files -norecurse $origin_dir/l2_arbiter/l2_external_interfaces.sv -force
|
||||
import_files -norecurse $origin_dir/local_memory/local_memory_interface.sv -force
|
||||
import_files -norecurse $origin_dir/core/external_interfaces.sv -force
|
||||
import_files -norecurse $origin_dir/core/taiga_config.sv -force
|
||||
import_files -norecurse $origin_dir/l2_arbiter/l2_config_and_types.sv -force
|
||||
|
||||
# Set IP repository paths
|
||||
set obj [get_filesets sources_1]
|
||||
set_property "ip_repo_paths" "[file normalize "$origin_dir/Clean_Taiga_IP"]" $obj
|
||||
|
||||
# Rebuild user ip_repo's index before adding any source files
|
||||
update_ip_catalog -rebuild
|
||||
|
||||
# Add/Import constrs file and set constrs file properties
|
||||
#set file "[file normalize "$origin_dir/examples/zedboard/zedboard_master_XDC_RevC_D_v3.xdc"]"
|
||||
#set file_imported [import_files -fileset constrs_1 [list $file]]
|
||||
|
||||
# Set 'sources_1' fileset file properties for remote files
|
||||
# None
|
||||
|
||||
# Set 'sources_1' fileset file properties for local files
|
||||
|
||||
# Set 'sources_1' fileset properties
|
||||
set obj [get_filesets sources_1]
|
||||
set_property -name "top" -value "taiga_wrapper_xilinx" -objects $obj
|
||||
set_property -name "top_auto_set" -value "0" -objects $obj
|
||||
set_property -name "top_file" -value " ${origin_dir}/core/taiga_wrapper_xilinx.sv" -objects $obj
|
||||
|
||||
|
||||
# Remove interface files for taiga
|
||||
puts "INFO: Project created:${_xil_proj_name_}"
|
||||
|
||||
#Removal of SystemVerilog interface files, so initial IP packaging can be done
|
||||
#CUrrently Vivado 2018.1 complains if there is any SV interfaces during the intial packaging
|
||||
#But if we were to re-add the SV interface files back into the IP and repackage it, SV will not complain
|
||||
#export_ip_user_files -of_objects [get_files $origin_dir/${_xil_proj_name_}/${_xil_proj_name_}.srcs/sources_1/imports/core/interfaces.sv] -no_script -reset -force -quiet
|
||||
#remove_files $origin_dir/${_xil_proj_name_}/${_xil_proj_name_}.srcs/sources_1/imports/core/interfaces.sv
|
||||
#export_ip_user_files -of_objects [get_files $origin_dir/${_xil_proj_name_}/${_xil_proj_name_}.srcs/sources_1/imports/l2_arbiter/l2_interfaces.sv] -no_script -reset -force -quiet
|
||||
#remove_files $origin_dir/${_xil_proj_name_}/${_xil_proj_name_}.srcs/sources_1/imports/l2_arbiter/l2_interfaces.sv
|
||||
|
||||
############## Initial IP Packaging########################################
|
||||
ipx::package_project -import_files -force -root_dir $proj_dir
|
||||
update_compile_order -fileset sources_1
|
||||
set_property core_revision 2 [ipx::current_core]
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
ipx::update_checksums [ipx::current_core]
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
|
||||
|
||||
# To set the axi interface as aximm and port map all the signals over #
|
||||
set_property abstraction_type_vlnv xilinx.com:interface:aximm_rtl:1.0 [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
||||
set_property bus_type_vlnv xilinx.com:interface:aximm:1.0 [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
||||
ipx::remove_port_map arid [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
||||
ipx::add_port_map WLAST [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
||||
set_property physical_name m_axi_wlast [ipx::get_port_maps WLAST -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
|
||||
ipx::add_port_map BREADY [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
||||
set_property physical_name m_axi_bready [ipx::get_port_maps BREADY -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
|
||||
ipx::add_port_map AWLEN [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
||||
set_property physical_name m_axi_awlen [ipx::get_port_maps AWLEN -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
|
||||
ipx::add_port_map AWREADY [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
||||
set_property physical_name m_axi_awready [ipx::get_port_maps AWREADY -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
|
||||
ipx::add_port_map ARBURST [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
||||
set_property physical_name m_axi_arburst [ipx::get_port_maps ARBURST -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
|
||||
ipx::add_port_map RRESP [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
||||
set_property physical_name m_axi_rresp [ipx::get_port_maps RRESP -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
|
||||
ipx::add_port_map RVALID [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
||||
set_property physical_name m_axi_rvalid [ipx::get_port_maps RVALID -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
|
||||
ipx::add_port_map AWID [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
||||
set_property physical_name m_axi_awid [ipx::get_port_maps AWID -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
|
||||
ipx::add_port_map RLAST [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
||||
set_property physical_name m_axi_rlast [ipx::get_port_maps RLAST -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
|
||||
ipx::add_port_map ARID [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
||||
set_property physical_name m_axi_arid [ipx::get_port_maps ARID -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
|
||||
ipx::add_port_map AWCACHE [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
||||
set_property physical_name m_axi_awcache [ipx::get_port_maps AWCACHE -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
|
||||
ipx::add_port_map WREADY [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
||||
set_property physical_name m_axi_wready [ipx::get_port_maps WREADY -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
|
||||
ipx::add_port_map WSTRB [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
||||
set_property physical_name m_axi_wstrb [ipx::get_port_maps WSTRB -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
|
||||
ipx::add_port_map BRESP [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
||||
set_property physical_name m_axi_bresp [ipx::get_port_maps BRESP -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
|
||||
ipx::add_port_map BID [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
||||
set_property physical_name m_axi_bid [ipx::get_port_maps BID -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
|
||||
ipx::add_port_map ARLEN [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
||||
set_property physical_name m_axi_arlen [ipx::get_port_maps ARLEN -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
|
||||
ipx::add_port_map RDATA [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
||||
set_property physical_name m_axi_rdata [ipx::get_port_maps RDATA -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
|
||||
ipx::add_port_map BVALID [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
||||
set_property physical_name m_axi_bvalid [ipx::get_port_maps BVALID -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
|
||||
ipx::add_port_map ARCACHE [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
||||
set_property physical_name m_axi_arcache [ipx::get_port_maps ARCACHE -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
|
||||
ipx::add_port_map RREADY [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
||||
set_property physical_name m_axi_rready [ipx::get_port_maps RREADY -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
|
||||
ipx::add_port_map AWVALID [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
||||
set_property physical_name m_axi_awvalid [ipx::get_port_maps AWVALID -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
|
||||
ipx::add_port_map ARSIZE [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
||||
set_property physical_name m_axi_arsize [ipx::get_port_maps ARSIZE -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
|
||||
ipx::add_port_map WDATA [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
||||
set_property physical_name m_axi_wdata [ipx::get_port_maps WDATA -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
|
||||
ipx::add_port_map AWSIZE [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
||||
set_property physical_name m_axi_awsize [ipx::get_port_maps AWSIZE -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
|
||||
ipx::add_port_map RID [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
||||
set_property physical_name m_axi_rid [ipx::get_port_maps RID -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
|
||||
ipx::add_port_map ARADDR [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
||||
set_property physical_name m_axi_araddr [ipx::get_port_maps ARADDR -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
|
||||
ipx::add_port_map AWADDR [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
||||
set_property physical_name m_axi_awaddr [ipx::get_port_maps AWADDR -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
|
||||
ipx::add_port_map ARREADY [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
||||
set_property physical_name m_axi_arready [ipx::get_port_maps ARREADY -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
|
||||
ipx::add_port_map WVALID [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
||||
set_property physical_name m_axi_wvalid [ipx::get_port_maps WVALID -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
|
||||
ipx::add_port_map ARVALID [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
||||
set_property physical_name m_axi_arvalid [ipx::get_port_maps ARVALID -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
|
||||
ipx::add_port_map AWBURST [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
||||
set_property physical_name m_axi_awburst [ipx::get_port_maps AWBURST -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
|
||||
|
||||
#####Re-Adding of SV interfaces files
|
||||
#set_property ip_repo_paths $origin_dir/${_xil_proj_name_} [current_project]
|
||||
#current_project $_xil_proj_name_
|
||||
#update_ip_catalog
|
||||
#import_files -norecurse $origin_dir/l2_arbiter/l2_interfaces.sv -force
|
||||
#import_files -norecurse $origin_dir/core/interfaces.sv -force
|
||||
|
||||
#####Re-Adding of project files
|
||||
set_property ip_repo_paths $origin_dir/${_xil_proj_name_} [current_project]
|
||||
current_project $_xil_proj_name_
|
||||
update_ip_catalog
|
||||
import_files -fileset [get_filesets sources_1] $origin_dir/core
|
||||
import_files -fileset [get_filesets sources_1] $origin_dir/l2_arbiter
|
||||
import_files -fileset [get_filesets sources_1] $origin_dir/local_memory
|
||||
|
||||
############## Re-packaging of core
|
||||
update_compile_order -fileset sources_1
|
||||
ipx::merge_project_changes files [ipx::current_core]
|
||||
set_property core_revision 3 [ipx::current_core]
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
ipx::update_checksums [ipx::current_core]
|
||||
ipx::save_core [ipx::current_core]
|
||||
current_project taiga_wrapper_IP
|
||||
update_ip_catalog -rebuild -repo_path $origin_dir/${_xil_proj_name_}
|
||||
|
||||
Loading…
Add table
Add a link
Reference in a new issue