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linting : div interface parameter changes

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This commit is contained in:
Eric Matthews 2020-06-22 15:20:19 -07:00
parent 928f5465c4
commit 904fa6f6f9
3 changed files with 37 additions and 31 deletions
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6
core/div_algorithms/div_algorithm.sv
View file

@ -1,5 +1,5 @@
/*
* Copyright © 2017, 2018 Eric Matthews, Lesley Shannon
* Copyright © 2017-2020 Eric Matthews, Lesley Shannon
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@ -33,8 +33,8 @@ module div_algorithm
generate
case(DIV_ALGORITHM)
RADIX_2 : div_radix2 div_block (.*);
QUICK_CLZ : div_quick_clz div_block (.*);
RADIX_2 : div_radix2 #(.DIV_WIDTH(32)) div_block (.clk(clk), .rst(rst), .div(div));
QUICK_CLZ : div_quick_clz #(.DIV_WIDTH(32)) div_block (.clk(clk), .rst(rst), .div(div));
endcase
endgenerate

27
core/div_algorithms/div_quick_clz.sv
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@ -1,5 +1,5 @@
/*
* Copyright © 2017-2019 Eric Matthews, Lesley Shannon
* Copyright © 2017-2020 Eric Matthews, Lesley Shannon
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@ -23,6 +23,9 @@
module div_quick_clz
#(
parameter DIV_WIDTH = 32
)
(
input logic clk,
input logic rst,
@ -31,24 +34,24 @@ module div_quick_clz
logic running;
logic terminate;
logic [div.DATA_WIDTH-1:0] divisor_r;
logic [DIV_WIDTH-1:0] divisor_r;
logic [div.DATA_WIDTH-1:0] normalized_divisor;
logic [DIV_WIDTH-1:0] normalized_divisor;
logic overflow;
logic [div.DATA_WIDTH-1:0] subtraction1;
logic [div.DATA_WIDTH-1:0] subtraction2;
logic [DIV_WIDTH-1:0] subtraction1;
logic [DIV_WIDTH-1:0] subtraction2;
logic [div.DATA_WIDTH-1:0] new_remainder;
logic [div.DATA_WIDTH-1:0] new_quotient;
logic [DIV_WIDTH-1:0] new_remainder;
logic [DIV_WIDTH-1:0] new_quotient;
logic [div.DATA_WIDTH-1:0] new_Q_bit1;
logic [div.DATA_WIDTH-1:0] new_Q_bit2;
logic [DIV_WIDTH-1:0] new_Q_bit1;
logic [DIV_WIDTH-1:0] new_Q_bit2;
logic [div.DATA_WIDTH-1:0] test_multiple1;
logic [div.DATA_WIDTH-1:0] test_multiple2;
logic [DIV_WIDTH-1:0] test_multiple1;
logic [DIV_WIDTH-1:0] test_multiple2;
localparam CLZ_W = $clog2(div.DATA_WIDTH);
localparam CLZ_W = $clog2(DIV_WIDTH);
logic [CLZ_W-1:0] remainder_CLZ;
logic [CLZ_W-1:0] divisor_CLZ;
logic [CLZ_W-1:0] divisor_CLZ_r;

35
core/div_algorithms/div_radix2.sv
View file

@ -1,5 +1,5 @@
/*
* Copyright © 2017-2019 Eric Matthews, Lesley Shannon
* Copyright © 2017-2020 Eric Matthews, Lesley Shannon
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@ -23,43 +23,46 @@
module div_radix2
(
#(
parameter DIV_WIDTH = 32
)
(
input logic clk,
input logic rst,
unsigned_division_interface.divider div
);
);
logic terminate;
logic [div.DATA_WIDTH-1:0] divisor_r;
logic [div.DATA_WIDTH:0] new_PR;
logic [div.DATA_WIDTH:0] PR;
logic [div.DATA_WIDTH-1:0] shift_count;
logic [DIV_WIDTH-1:0] divisor_r;
logic [DIV_WIDTH:0] new_PR;
logic [DIV_WIDTH:0] PR;
logic [DIV_WIDTH-1:0] shift_count;
logic negative_sub_rst;
//implementation
////////////////////////////////////////////////////
assign new_PR = PR - {1'b0, divisor_r};
assign negative_sub_rst = new_PR[div.DATA_WIDTH];
assign negative_sub_rst = new_PR[DIV_WIDTH];
//Shift reg for
always_ff @ (posedge clk) begin
shift_count <= {shift_count[30:0], div.start};
shift_count <= {shift_count[DIV_WIDTH-2:0], div.start};
end
always_ff @ (posedge clk) begin
if (div.start) begin
divisor_r <= div.divisor;
PR <= {(div.DATA_WIDTH)'(1'b0), div.dividend[div.DATA_WIDTH-1]};
div.quotient <= {div.dividend[div.DATA_WIDTH-2:0], 1'b0};
PR <= {(DIV_WIDTH)'(1'b0), div.dividend[DIV_WIDTH-1]};
div.quotient <= {div.dividend[DIV_WIDTH-2:0], 1'b0};
end
else if (~terminate) begin
PR <= negative_sub_rst ? {PR[div.DATA_WIDTH-1:0], div.quotient[div.DATA_WIDTH-1]} : {new_PR[div.DATA_WIDTH-1:0], div.quotient[div.DATA_WIDTH-1]};
div.quotient <= {div.quotient[div.DATA_WIDTH-2:0], ~negative_sub_rst};
PR <= negative_sub_rst ? {PR[DIV_WIDTH-1:0], div.quotient[DIV_WIDTH-1]} : {new_PR[DIV_WIDTH-1:0], div.quotient[DIV_WIDTH-1]};
div.quotient <= {div.quotient[DIV_WIDTH-2:0], ~negative_sub_rst};
end
end
assign div.remainder = PR[div.DATA_WIDTH:1];
assign div.remainder = PR[DIV_WIDTH:1];
always_ff @ (posedge clk) begin
if (div.start)
@ -74,7 +77,7 @@ module div_radix2
else begin
if (div.start)
terminate <= 0;
if (shift_count[31])
if (shift_count[DIV_WIDTH-1])
terminate <= 1;
end
end
@ -83,7 +86,7 @@ module div_radix2
if (rst)
div.done <= 0;
else begin
if (shift_count[31])
if (shift_count[DIV_WIDTH-1])
div.done <= 1;
else if (div.done)
div.done <= 0;