first patch fixing some comments

apu/busses/axi_adapter.sv

@@ -83,7 +83,7 @@ module axi_adapter
     assign axi.arlen = {3'b0, request_rlen};
     assign axi.arsize = 3'b010; //4 bytes
     assign axi.arburst = 2'b01; //Incrementing
-    assign axi.arcache = 4'b0011; //Bufferable and cacheable memory
+    assign axi.arcache = 4'b0011; //Bufferable and non-cacheable memory
     assign axi.arlock = 0; //Not locked
 
     //R
@@ -114,7 +114,7 @@ module axi_adapter
     assign axi.awlen = '0;
     assign axi.awsize = 3'b010; //4 bytes
     assign axi.awburst = 2'b01; //Incrementing
-    assign axi.awcache = 4'b0011; //Bufferable and cacheable memory
+    assign axi.awcache = 4'b0011; //Bufferable and non-cacheable memory
     assign axi.awlock = 0; //Not locked
 
     //W

core/cva5.sv

@@ -695,13 +695,6 @@ module cva5
 
     ////////////////////////////////////////////////////
     //Assertions
-    //Ensure that reset is held for at least 32 cycles to clear shift regs
-    // always_ff @ (posedge clk) begin
-    //     assert property(@(posedge clk) $rose (rst) |=> rst[*32]) else $error("Reset not held for long enough!");
-    // end
-
-    ////////////////////////////////////////////////////
-    //Assertions
 
 
 endmodule

examples/xilinx/cva5_top.v

@@ -53,7 +53,7 @@ module cva5_top
         output [31:0] m_axi_wdata,
         output [3:0] m_axi_wstrb,
 
-        //write response
+        //B
         output m_axi_bready,
         input m_axi_bvalid,
         input [1:0] m_axi_bresp

examples/xilinx/cva5_wrapper.sv

@@ -56,7 +56,7 @@ module cva5_wrapper
         output logic [31:0] m_axi_wdata,
         output logic [3:0] m_axi_wstrb,
 
-        //write response
+        //B
         output logic m_axi_bready,
         input logic m_axi_bvalid,
         input logic [1:0] m_axi_bresp