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added generate labels

Browse source 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
This commit is contained in:
Eric Matthews 2022-01-30 16:20:29 -08:00
parent 659cc90605
commit 97368c431d
24 changed files with 127 additions and 145 deletions
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6
core/branch_predictor.sv
View file

@ -95,7 +95,7 @@ module branch_predictor
genvar i;
generate if (CONFIG.INCLUDE_BRANCH_PREDICTOR)
for (i=0; i<CONFIG.BP.WAYS; i++) begin : branch_tag_banks
for (i=0; i<CONFIG.BP.WAYS; i++) begin : gen_branch_tag_banks
branch_predictor_ram #(.C_DATA_WIDTH($bits(branch_table_entry_t)), .C_DEPTH(CONFIG.BP.ENTRIES))
tag_bank (
.clk (clk),
@ -110,7 +110,7 @@ module branch_predictor
endgenerate
generate if (CONFIG.INCLUDE_BRANCH_PREDICTOR)
for (i=0; i<CONFIG.BP.WAYS; i++) begin : branch_table_banks
for (i=0; i<CONFIG.BP.WAYS; i++) begin : gen_branch_table_banks
branch_predictor_ram #(.C_DATA_WIDTH(32), .C_DEPTH(CONFIG.BP.ENTRIES))
addr_table (
.clk (clk),
@ -126,7 +126,7 @@ module branch_predictor
endgenerate
generate if (CONFIG.INCLUDE_BRANCH_PREDICTOR)
for (i=0; i<CONFIG.BP.WAYS; i++) begin : branch_hit_detection
for (i=0; i<CONFIG.BP.WAYS; i++) begin : gen_branch_hit_detection
assign tag_matches[i] = ({if_entry[i].valid, if_entry[i].tag} == {1'b1, get_tag(bp.if_pc)});
end
endgenerate

2
core/branch_unit.sv
View file

@ -111,7 +111,7 @@ module branch_unit
////////////////////////////////////////////////////
//Exception support
generate if (CONFIG.INCLUDE_M_MODE) begin
generate if (CONFIG.INCLUDE_M_MODE) begin : gen_branch_exception
logic new_exception;
assign new_exception = new_pc[1] & branch_taken & issue.new_request;

4
core/csr_unit.sv
View file

@ -217,7 +217,7 @@ module csr_unit
const mstatus_t sstatus_mask = '{default:0, mxr:1, sum:1, spp:1, spie:1, sie:1};
generate if (CONFIG.INCLUDE_M_MODE) begin
generate if (CONFIG.INCLUDE_M_MODE) begin : gen_csr_m_mode
privilege_t trap_return_privilege_level;
privilege_t exception_privilege_level;
@ -554,7 +554,7 @@ endgenerate
assign asid = satp.asid;
//******************
generate if (CONFIG.INCLUDE_S_MODE) begin
generate if (CONFIG.INCLUDE_S_MODE) begin : gen_csr_s_mode
////////////////////////////////////////////////////
//MMU interface
assign immu.mxr = mstatus.mxr;

20
core/cycler.sv
View file

@ -32,18 +32,16 @@ module cycler
output logic [C_WIDTH - 1: 0] one_hot
);
generate
if (C_WIDTH == 1) begin
assign one_hot = 1;
end
else begin
always_ff @ (posedge clk) begin
if (rst)
one_hot <= 1;
else if (en)
one_hot <= {one_hot[C_WIDTH-2:0],one_hot[C_WIDTH-1]};//rotate left
end
generate if (C_WIDTH == 1) begin : gen_width_one
assign one_hot = 1;
end else begin : gen_width_two_plus
always_ff @ (posedge clk) begin
if (rst)
one_hot <= 1;
else if (en)
one_hot <= {one_hot[C_WIDTH-2:0],one_hot[C_WIDTH-1]};//rotate left
end
end
endgenerate
endmodule

18
core/decode_and_issue.sv
View file

@ -237,9 +237,9 @@ module decode_and_issue
////////////////////////////////////////////////////
//Unit ready
generate for (i=0; i<NUM_UNITS; i++) begin
generate for (i=0; i<NUM_UNITS; i++)
assign unit_ready[i] = unit_issue[i].ready;
end endgenerate
endgenerate
////////////////////////////////////////////////////
//Issue Determination
@ -343,7 +343,7 @@ module decode_and_issue
assign store_conditional = (amo_type == AMO_SC_FN5);
assign load_reserve = (amo_type == AMO_LR_FN5);
generate if (CONFIG.INCLUDE_AMO) begin
generate if (CONFIG.INCLUDE_AMO) begin : gen_decode_ls_amo
assign ls_inputs.amo.is_lr = load_reserve;
assign ls_inputs.amo.is_sc = store_conditional;
assign ls_inputs.amo.is_amo = amo_op & ~(load_reserve | store_conditional);
@ -500,7 +500,7 @@ module decode_and_issue
////////////////////////////////////////////////////
//CSR unit inputs
generate if (CONFIG.INCLUDE_CSRS) begin
generate if (CONFIG.INCLUDE_CSRS) begin : gen_decode_csr_inputs
assign csr_inputs.addr = issue.instruction[31:20];
assign csr_inputs.op = issue.fn3[1:0];
assign csr_inputs.data = issue.fn3[2] ? {27'b0, issue_rs_addr[RS1]} : rf.data[RS1];
@ -510,7 +510,7 @@ module decode_and_issue
////////////////////////////////////////////////////
//Mul unit inputs
generate if (CONFIG.INCLUDE_MUL) begin
generate if (CONFIG.INCLUDE_MUL) begin : gen_decode_mul_inputs
assign mul_inputs.rs1 = rf.data[RS1];
assign mul_inputs.rs2 = rf.data[RS2];
assign mul_inputs.op = issue.fn3[1:0];
@ -518,7 +518,7 @@ module decode_and_issue
////////////////////////////////////////////////////
//Div unit inputs
generate if (CONFIG.INCLUDE_DIV) begin
generate if (CONFIG.INCLUDE_DIV) begin : gen_decode_div_inputs
phys_addr_t prev_div_rs_addr [2];
logic [1:0] div_rd_match;
logic prev_div_result_valid;
@ -552,7 +552,7 @@ module decode_and_issue
////////////////////////////////////////////////////
//Unit EX signals
generate for (i = 0; i < NUM_UNITS; i++) begin
generate for (i = 0; i < NUM_UNITS; i++) begin : gen_unit_issue_signals
assign unit_issue[i].possible_issue = issue.stage_valid & unit_needed_issue_stage[i] & unit_issue[i].ready;
assign unit_issue[i].new_request = issue_to[i];
assign unit_issue[i].id = issue.id;
@ -564,7 +564,7 @@ module decode_and_issue
////////////////////////////////////////////////////
//Illegal Instruction check
logic illegal_instruction_pattern_r;
generate if (CONFIG.INCLUDE_M_MODE) begin
generate if (CONFIG.INCLUDE_M_MODE) begin : gen_decode_exceptions
illegal_instruction_checker # (.CONFIG(CONFIG))
illegal_op_check (
.instruction(decode.instruction), .illegal_instruction(illegal_instruction_pattern)
@ -646,7 +646,7 @@ module decode_and_issue
////////////////////////////////////////////////////
//Trace Interface
generate if (ENABLE_TRACE_INTERFACE) begin
generate if (ENABLE_TRACE_INTERFACE) begin : gen_decode_trace
assign tr_operand_stall = issue.stage_valid & ~gc.fetch_flush & ~gc.issue_hold & ~pre_issue_exception_pending & ~operands_ready & |issue_ready;
assign tr_unit_stall = issue_valid & ~gc.fetch_flush & ~|issue_ready;
assign tr_no_id_stall = (~issue.stage_valid & ~pc_id_available & ~gc.fetch_flush); //All instructions in execution pipeline

6
core/fetch.sv
View file

@ -211,7 +211,7 @@ module fetch
//In the case of a gc.fetch_flush, a request may already be in progress
//for any sub unit. That request can either be completed or aborted.
//In either case, data_valid must NOT be asserted.
generate if (CONFIG.INCLUDE_ILOCAL_MEM) begin
generate if (CONFIG.INCLUDE_ILOCAL_MEM) begin : gen_fetch_local_mem
assign sub_unit_address_match[BRAM_ID] = bram.address_range_check(translated_address);
assign unit_ready[BRAM_ID] = bram.ready;
assign unit_data_valid[BRAM_ID] = bram.data_valid;
@ -229,7 +229,7 @@ module fetch
);
end
endgenerate
generate if (CONFIG.INCLUDE_ICACHE) begin
generate if (CONFIG.INCLUDE_ICACHE) begin : gen_fetch_icache
assign sub_unit_address_match[ICACHE_ID] = cache.address_range_check(translated_address);
assign unit_ready[ICACHE_ID] = cache.ready;
assign unit_data_valid[ICACHE_ID] = cache.data_valid;
@ -271,7 +271,7 @@ module fetch
assign is_branch_or_jump = fetch_instruction[6:2] inside {JAL_T, JALR_T, BRANCH_T};
assign early_branch_flush = (valid_fetch_result & (|unit_data_valid)) & fetch_attr.is_predicted_branch_or_jump & (~is_branch_or_jump);
assign early_branch_flush_ras_adjust = (valid_fetch_result & (|unit_data_valid)) & fetch_attr.is_branch & (~is_branch_or_jump);
generate if (ENABLE_TRACE_INTERFACE) begin
generate if (ENABLE_TRACE_INTERFACE) begin : gen_fetch_trace
assign tr_early_branch_correction = early_branch_flush;
end endgenerate

4
core/gc_unit.sv
View file

@ -225,7 +225,7 @@ module gc_unit
////////////////////////////////////////////////////
//Exception handling
generate if (CONFIG.INCLUDE_M_MODE) begin
generate if (CONFIG.INCLUDE_M_MODE) begin :gen_gc_m_mode
//Re-assigning interface inputs to array types so that they can be dynamically indexed
logic [NUM_EXCEPTION_SOURCES-1:0] exception_pending;
@ -264,7 +264,7 @@ module gc_unit
//PC determination (trap, flush or return)
//Two cycles: on first cycle the processor front end is flushed,
//on the second cycle the new PC is fetched
generate if (CONFIG.INCLUDE_M_MODE || CONFIG.INCLUDE_IFENCE) begin
generate if (CONFIG.INCLUDE_M_MODE || CONFIG.INCLUDE_IFENCE) begin :gen_gc_pc_override
always_ff @ (posedge clk) begin
gc_pc_override <= next_state inside {PRE_ISSUE_FLUSH, INIT_CLEAR_STATE};

10
core/instruction_metadata_and_id_management.sv
View file

@ -182,7 +182,7 @@ module instruction_metadata_and_id_management
end
//Retire IDs
//Each retire port lags behind the previous one by one index (eg. [3, 2, 1, 0])
generate for (i = 0; i < RETIRE_PORTS; i++) begin
generate for (i = 0; i < RETIRE_PORTS; i++) begin :gen_retire_ids
always_ff @ (posedge clk) begin
if (rst)
retire_ids_next[i] <= LOG2_MAX_IDS'(i);
@ -264,7 +264,7 @@ module instruction_metadata_and_id_management
logic [RETIRE_PORTS-1:0] retire_id_uses_rd;
logic [RETIRE_PORTS-1:0] retire_id_waiting_for_writeback;
generate for (i = 0; i < RETIRE_PORTS; i++) begin
generate for (i = 0; i < RETIRE_PORTS; i++) begin : gen_retire_writeback
assign retire_id_uses_rd[i] = uses_rd_table[retire_ids_next[i]];
assign retire_id_waiting_for_writeback[i] = id_waiting_for_writeback[i];
end endgenerate
@ -326,11 +326,11 @@ module instruction_metadata_and_id_management
//Writeback/Commit support
phys_addr_t commit_phys_addr [CONFIG.NUM_WB_GROUPS];
assign commit_phys_addr[0] = issue.phys_rd_addr;
generate for (i = 1; i < CONFIG.NUM_WB_GROUPS; i++) begin
generate for (i = 1; i < CONFIG.NUM_WB_GROUPS; i++) begin : gen_commit_phys_addr
assign commit_phys_addr[i] = phys_addr_table[wb_packet[i].id];
end endgenerate
generate for (i = 0; i < CONFIG.NUM_WB_GROUPS; i++) begin
generate for (i = 0; i < CONFIG.NUM_WB_GROUPS; i++) begin : gen_commit_packet
assign commit_packet[i].id = wb_packet[i].id;
assign commit_packet[i].phys_addr = commit_phys_addr[i];
assign commit_packet[i].valid = wb_packet[i].valid & |commit_phys_addr[i];
@ -338,7 +338,7 @@ module instruction_metadata_and_id_management
end endgenerate
//Exception Support
generate if (CONFIG.INCLUDE_M_MODE) begin
generate if (CONFIG.INCLUDE_M_MODE) begin : gen_id_exception_support
assign oldest_pc = pc_table[retire_ids_next[0]];
assign current_exception_unit = exception_unit_table[retire_ids_next[0]];
end endgenerate

6
core/l1_arbiter.sv
View file

@ -56,7 +56,7 @@ module l1_arbiter
//Implementation
//Interface to array
generate for (genvar i = 0; i < L1_CONNECTIONS; i++) begin
generate for (genvar i = 0; i < L1_CONNECTIONS; i++) begin : gen_requests
assign requests[i] = l1_request[i].request;
assign l1_request[i].ack = acks[i];
end endgenerate
@ -85,7 +85,7 @@ module l1_arbiter
////////////////////////////////////////////////////
//Interface mapping
generate for (genvar i = 0; i < L1_CONNECTIONS; i++) begin
generate for (genvar i = 0; i < L1_CONNECTIONS; i++) begin : gen_l2_requests
always_comb begin
l2_requests[i].addr = l1_request[i].addr[31:2];
l2_requests[i].rnw = l1_request[i].rnw;
@ -118,7 +118,7 @@ module l1_arbiter
assign l2.amo_type_or_burst_size = l2_requests[arb_sel].amo_type_or_burst_size;
assign l2.sub_id = l2_requests[arb_sel].sub_id;
generate for (genvar i = 0; i < L1_CONNECTIONS; i++) begin
generate for (genvar i = 0; i < L1_CONNECTIONS; i++) begin : gen_l1_responses
assign l1_response[i].data = l2.rd_data;
assign l1_response[i].data_valid = l2.rd_data_valid && (l2.rd_sub_id == i);
end endgenerate

6
core/lfsr.sv
View file

@ -81,11 +81,11 @@ module lfsr
logic feedback;
////////////////////////////////////////////////////
//Implementation
generate if (WIDTH == 2) begin
generate if (WIDTH == 2) begin : gen_width_two
assign feedback = ~value[WIDTH-1];
end
else begin
for (genvar i = 0; i < NUM_TAPS[TAPS_INDEX]; i++) begin
else begin : gen_width_three_plus
for (genvar i = 0; i < NUM_TAPS[TAPS_INDEX]; i++) begin : gen_taps
assign feedback_input[i] = value[TAPS[TAPS_INDEX][i + 1] - 1];
end
//XNOR of taps and range extension to include all ones

2
core/load_store_queue.sv
View file

@ -158,7 +158,7 @@ module load_store_queue //ID-based input buffer for Load/Store Unit
////////////////////////////////////////////////////
//Trace Interface
generate if (ENABLE_TRACE_INTERFACE) begin
generate if (ENABLE_TRACE_INTERFACE) begin : gen_lsq_trace
assign tr_possible_load_conflict_delay = lq_output_valid & (store_conflict | (sq_full & sq_output_valid));
end
endgenerate

10
core/load_store_unit.sv
View file

@ -131,7 +131,7 @@ module load_store_unit
////////////////////////////////////////////////////
//Alignment Exception
generate if (CONFIG.INCLUDE_M_MODE) begin
generate if (CONFIG.INCLUDE_M_MODE) begin : gen_ls_exceptions
logic new_exception;
always_comb begin
case(ls_inputs.fn3)
@ -286,7 +286,7 @@ endgenerate
////////////////////////////////////////////////////
//Unit Instantiation
generate if (CONFIG.INCLUDE_DLOCAL_MEM) begin
generate if (CONFIG.INCLUDE_DLOCAL_MEM) begin : gen_ls_local_mem
assign sub_unit_address_match[BRAM_ID] = bram.address_range_check(shared_inputs.addr);
assign bram.new_request = sub_unit_address_match[BRAM_ID] & issue_request;
@ -304,7 +304,7 @@ endgenerate
end
endgenerate
generate if (CONFIG.INCLUDE_PERIPHERAL_BUS) begin
generate if (CONFIG.INCLUDE_PERIPHERAL_BUS) begin : gen_ls_pbus
assign sub_unit_address_match[BUS_ID] = bus.address_range_check(shared_inputs.addr);
assign bus.new_request = sub_unit_address_match[BUS_ID] & issue_request;
@ -344,7 +344,7 @@ endgenerate
end
endgenerate
generate if (CONFIG.INCLUDE_DCACHE) begin
generate if (CONFIG.INCLUDE_DCACHE) begin : gen_ls_dcache
assign sub_unit_address_match[DCACHE_ID] = cache.address_range_check(shared_inputs.addr);
assign cache.new_request = sub_unit_address_match[DCACHE_ID] & issue_request;
@ -420,7 +420,7 @@ endgenerate
////////////////////////////////////////////////////
//Trace Interface
generate if (ENABLE_TRACE_INTERFACE) begin
generate if (ENABLE_TRACE_INTERFACE) begin : gen_ls_trace
assign tr_load_conflict_delay = tr_possible_load_conflict_delay & ready_for_issue_from_lsq;
end
endgenerate

4
core/one_hot_to_integer.sv
View file

@ -32,9 +32,9 @@ module one_hot_to_integer
);
////////////////////////////////////////////////////
//Implementation
generate if (C_WIDTH == 1)
generate if (C_WIDTH == 1) begin : gen_width_one
assign int_out = 0;
else begin
end else begin : gen_width_two_plus
always_comb begin
int_out = 0;
foreach(one_hot[i])

42
core/priority_encoder.sv
View file

@ -38,31 +38,25 @@ module priority_encoder
if (WIDTH > 12)
$error("Max priority encoder width exceeded!");
localparam LOG2_WIDTH = $clog2(WIDTH);
//Tool workaround
localparam MIN_WIDTH = (WIDTH == 1) ? 2 : WIDTH;
localparam LOG2_WIDTH = $clog2(MIN_WIDTH);
//Table generation for priority encoder
function [2**MIN_WIDTH-1:0][LOG2_WIDTH-1 : 0] table_gen ();
for (int i = 0; i < 2**MIN_WIDTH; i++) begin //Loop through all memory addresses
table_gen[i] = LOG2_WIDTH'(MIN_WIDTH - 1);//Initialize to lowest priority
for (int j = (int'(MIN_WIDTH) - 2); j >= 0; j--) begin//Check each bit in increasing priority
if (i[j])//If bit is set update table value with that bit's index
table_gen[i] = LOG2_WIDTH'(j);
end
end
endfunction
//Initialize Table
localparam logic [2**MIN_WIDTH-1:0][LOG2_WIDTH-1 : 0] ENCODER_ROM = table_gen();
////////////////////////////////////////////////////
//Implementation
generate
if (WIDTH == 1)
assign encoded_result = 0;
else begin
//Table generation for priority encoder
function [2**WIDTH-1:0][LOG2_WIDTH-1 : 0] table_gen ();
for (int i = 0; i < 2**WIDTH; i++) begin //Loop through all memory addresses
table_gen[i] = LOG2_WIDTH'(WIDTH - 1);//Initialize to lowest priority
for (int j = (int'(WIDTH) - 2); j >= 0; j--) begin//Check each bit in increasing priority
if (i[j])//If bit is set update table value with that bit's index
table_gen[i] = LOG2_WIDTH'(j);
end
end
endfunction
//Initialize Table
const logic [2**WIDTH-1:0][LOG2_WIDTH-1 : 0] encoder_rom = table_gen();
assign encoded_result = encoder_rom[priority_vector];
end
endgenerate
assign encoded_result = (WIDTH == 1) ? 0 : ENCODER_ROM[priority_vector];
endmodule

2
core/renamer.sv
View file

@ -194,7 +194,7 @@ module renamer
////////////////////////////////////////////////////
//Renamed Outputs
spec_table_t [REGFILE_READ_PORTS-1:0] spec_table_decode;
generate for (genvar i = 0; i < REGFILE_READ_PORTS; i++) begin
generate for (genvar i = 0; i < REGFILE_READ_PORTS; i++) begin : gen_renamed_addrs
assign spec_table_decode[i] = spec_table_read_data[i+1];
assign decode.phys_rs_addr[i] = spec_table_decode[i].phys_addr;
assign decode.rs_wb_group[i] = spec_table_decode[i].wb_group;

4
core/set_clr_reg_with_rst.sv
View file

@ -42,7 +42,7 @@ module set_clr_reg_with_rst
////////////////////////////////////////////////////
//Implementation
generate if (SET_OVER_CLR) begin
generate if (SET_OVER_CLR) begin : gen_set_over_clear
always_ff @ (posedge clk) begin
if (rst)
result <= RST_VALUE;
@ -50,7 +50,7 @@ module set_clr_reg_with_rst
result <= set | (result & ~clr);
end
end else begin
always_ff @ (posedge clk) begin
always_ff @ (posedge clk) begin : gen_clear_over_set
if (rst)
result <= RST_VALUE;
else

23
core/taiga.sv
View file

@ -235,8 +235,7 @@ module taiga
////////////////////////////////////////////////////
// Memory Interface
generate if (CONFIG.INCLUDE_S_MODE || CONFIG.INCLUDE_ICACHE || CONFIG.INCLUDE_DCACHE)
generate if (CONFIG.INCLUDE_S_MODE || CONFIG.INCLUDE_ICACHE || CONFIG.INCLUDE_DCACHE) begin : gen_l1_arbiter
l1_arbiter #(.CONFIG(CONFIG))
arb(
.clk (clk),
@ -247,7 +246,7 @@ module taiga
.l1_request (l1_request),
.l1_response (l1_response)
);
end
endgenerate
////////////////////////////////////////////////////
@ -333,7 +332,7 @@ module taiga
.ras (ras)
);
generate if (CONFIG.INCLUDE_S_MODE) begin
generate if (CONFIG.INCLUDE_S_MODE) begin : gen_itlb_immu
tlb_lut_ram #(.WAYS(CONFIG.ITLB.WAYS), .DEPTH(CONFIG.ITLB.DEPTH))
i_tlb (
@ -505,7 +504,7 @@ module taiga
.tr_load_conflict_delay (tr_load_conflict_delay)
);
generate if (CONFIG.INCLUDE_S_MODE) begin
generate if (CONFIG.INCLUDE_S_MODE) begin : gen_dtlb_dmmu
tlb_lut_ram #(.WAYS(CONFIG.DTLB.WAYS), .DEPTH(CONFIG.DTLB.DEPTH))
d_tlb (
.clk (clk),
@ -533,7 +532,7 @@ module taiga
end
endgenerate
generate if (CONFIG.INCLUDE_CSRS)
generate if (CONFIG.INCLUDE_CSRS) begin : gen_csrs
csr_unit # (.CONFIG(CONFIG))
csr_unit_block (
.clk(clk),
@ -559,7 +558,7 @@ module taiga
.s_interrupt(s_interrupt),
.m_interrupt(m_interrupt)
);
endgenerate
end endgenerate
gc_unit #(.CONFIG(CONFIG))
gc_unit_block (
@ -587,7 +586,7 @@ module taiga
.post_issue_count (post_issue_count)
);
generate if (CONFIG.INCLUDE_MUL)
generate if (CONFIG.INCLUDE_MUL) begin : gen_mul
mul_unit mul_unit_block (
.clk (clk),
.rst (rst),
@ -595,9 +594,9 @@ module taiga
.issue (unit_issue[UNIT_IDS.MUL]),
.wb (unit_wb[UNIT_IDS.MUL])
);
endgenerate
end endgenerate
generate if (CONFIG.INCLUDE_DIV)
generate if (CONFIG.INCLUDE_DIV) begin : gen_div
div_unit div_unit_block (
.clk (clk),
.rst (rst),
@ -605,7 +604,7 @@ module taiga
.issue (unit_issue[UNIT_IDS.DIV]),
.wb (unit_wb[UNIT_IDS.DIV])
);
endgenerate
end endgenerate
////////////////////////////////////////////////////
//Writeback
@ -641,7 +640,7 @@ module taiga
////////////////////////////////////////////////////
//Trace Interface
generate if (ENABLE_TRACE_INTERFACE) begin
generate if (ENABLE_TRACE_INTERFACE) begin : gen_taiga_trace
always_ff @(posedge clk) begin
tr.events.early_branch_correction <= tr_early_branch_correction;
tr.events.operand_stall <= tr_operand_stall;

6
core/taiga_fifo.sv
View file

@ -45,7 +45,7 @@ module taiga_fifo
////////////////////////////////////////////////////
//Implementation
//If depth is one, the FIFO can be implemented with a single register
generate if (FIFO_DEPTH == 1) begin
generate if (FIFO_DEPTH == 1) begin : gen_width_one
always_ff @ (posedge clk) begin
if (rst)
fifo.valid <= 0;
@ -62,7 +62,7 @@ module taiga_fifo
//If depth is two, the FIFO can be implemented with two registers
//connected as a shift reg for the same resources as a LUTRAM FIFO
//but with better timing
else if (FIFO_DEPTH == 2) begin
else if (FIFO_DEPTH == 2) begin : gen_width_two
logic [DATA_WIDTH-1:0] shift_reg [FIFO_DEPTH];
logic [LOG2_FIFO_DEPTH:0] inflight_count;
////////////////////////////////////////////////////
@ -86,7 +86,7 @@ module taiga_fifo
assign fifo.data_out = shift_reg[~inflight_count[0]];
end
else begin
else begin : gen_width_3_plus
//Force FIFO depth to next power of 2
(* ramstyle = "MLAB, no_rw_check" *) logic [DATA_WIDTH-1:0] lut_ram [(2**LOG2_FIFO_DEPTH)];
logic [LOG2_FIFO_DEPTH-1:0] write_index;

10
core/writeback.sv
View file

@ -73,8 +73,8 @@ module writeback
//Implementation
//Re-assigning interface inputs to array types so that they can be dynamically indexed
generate
for (i = 0; i < CONFIG.NUM_WB_GROUPS; i++) begin
for (j = 0; j < NUM_UNITS[i]; j++) begin
for (i = 0; i < CONFIG.NUM_WB_GROUPS; i++) begin : gen_wb_group_unpacking
for (j = 0; j < NUM_UNITS[i]; j++) begin : gen_wb_unit_unpacking
assign unit_instruction_id[i][j] = unit_wb[CUMULATIVE_NUM_UNITS[i] + j].id;
assign unit_done[i][j] = unit_wb[CUMULATIVE_NUM_UNITS[i] + j].done;
assign unit_wb[CUMULATIVE_NUM_UNITS[i] + j].ack = unit_ack[i][j];
@ -85,8 +85,8 @@ module writeback
//As units are selected for commit ports based on their unit ID,
//for each additional commit port one unit can be skipped for the commit mux
generate
for (i = 0; i < CONFIG.NUM_WB_GROUPS; i++) begin
for (j = 0; j < NUM_UNITS[i]; j++) begin
for (i = 0; i < CONFIG.NUM_WB_GROUPS; i++) begin : gen_wb_port_grouping
for (j = 0; j < NUM_UNITS[i]; j++) begin : gen_wb_unit_grouping
assign unit_rd[i][j] = unit_wb[CUMULATIVE_NUM_UNITS[i] + j].rd;
end
end
@ -97,7 +97,7 @@ module writeback
//Iterating through all commit ports:
// Search for complete units (in fixed unit order)
// Assign to a commit port, mask that unit and commit port
generate for (i = 0; i < CONFIG.NUM_WB_GROUPS; i++) begin
generate for (i = 0; i < CONFIG.NUM_WB_GROUPS; i++) begin : gen_wb_mux
priority_encoder
#(.WIDTH(NUM_UNITS[i]))
unit_done_encoder

4
core/xilinx/xilinx_byte_enable_ram.sv
View file

@ -55,7 +55,7 @@ module xilinx_byte_enable_ram
$readmemh(preload_file,ram, 0, LINES-1);
end
generate
generate begin : gen_xilinx_bram
genvar i;
for (i=0; i < 4; i++) begin
always_ff @(posedge clk) begin
@ -82,6 +82,6 @@ module xilinx_byte_enable_ram
end
end
end
endgenerate
end endgenerate
endmodule

15
l2_arbiter/l2_arbiter.sv
View file

@ -86,8 +86,7 @@ module l2_arbiter
* Input Request FIFOs
*************************************/
genvar i;
generate
for (i=0; i < L2_NUM_PORTS; i++) begin
generate for (i=0; i < L2_NUM_PORTS; i++) begin : gen_requests
//Requester FIFO side
assign input_fifos[i].push = request[i].request_push;
assign input_fifos[i].potential_push = request[i].request_push;
@ -117,8 +116,7 @@ module l2_arbiter
/*************************************
* Input Data FIFOs
*************************************/
generate
for (i=0; i < L2_NUM_PORTS; i++) begin
generate for (i=0; i < L2_NUM_PORTS; i++) begin : gen_input_fifos
//Requester FIFO side
assign input_data_fifos[i].push = request[i].wr_data_push;
assign input_data_fifos[i].potential_push = request[i].wr_data_push;
@ -206,8 +204,7 @@ module l2_arbiter
);
//sc response
generate
for (i=0; i < L2_NUM_PORTS; i++) begin
generate for (i=0; i < L2_NUM_PORTS; i++) begin : gen_sc_response
always_ff @(posedge clk) begin
if (rst) begin
request[i].con_result <= 0;
@ -222,8 +219,7 @@ module l2_arbiter
endgenerate
//inv response
generate
for (i=0; i < L2_NUM_PORTS; i++) begin
generate for (i=0; i < L2_NUM_PORTS; i++) begin : gen_inv_response
//Requester FIFO side
assign inv_response_fifos[i].pop = request[i].inv_ack;
assign request[i].inv_addr = inv_response_fifos[i].data_out;
@ -293,8 +289,7 @@ module l2_arbiter
return_push[mem_return_data.id] = mem_returndata_fifo.valid;
end
generate
for (i=0; i < L2_NUM_PORTS; i++) begin
generate for (i=0; i < L2_NUM_PORTS; i++) begin : gen_return_data
//Requester FIFO side
assign returndata_fifos[i].pop = request[i].rd_data_ack;
assign return_data[i] = returndata_fifos[i].data_out;

4
l2_arbiter/l2_fifo.sv
View file

@ -30,11 +30,11 @@ module l2_fifo #(parameter DATA_WIDTH = 32, parameter FIFO_DEPTH = 4, parameter
l2_fifo_interface.structure fifo
);
generate if (ASYNC) begin
generate if (ASYNC) begin : gen_async
end
else
begin
begin : gen_sync
if (FIFO_DEPTH == 1) begin
always_ff @ (posedge clk) begin

62
l2_arbiter/l2_round_robin.sv
View file

@ -33,47 +33,43 @@ module l2_round_robin
logic [$clog2(L2_NUM_PORTS)-1:0] state;
logic[$clog2(L2_NUM_PORTS)-1:0] muxes [L2_NUM_PORTS-1:0];
generate if(L2_NUM_PORTS == 1)
begin
assign arb.grantee_valid = arb.requests[0];
assign arb.grantee_v = arb.requests;
assign arb.grantee_i = 0;
generate if(L2_NUM_PORTS == 1) begin : gen_width_one
assign arb.grantee_valid = arb.requests[0];
assign arb.grantee_v = arb.requests;
assign arb.grantee_i = 0;
end else begin : gen_width_2plus
//Lowest priority to current state
always_ff @(posedge clk) begin
if (rst)
state <= 0;
else if (arb.strobe)
state <= arb.grantee_i;
end
else
begin
//Lowest priority to current state
always_ff @(posedge clk) begin
if (rst)
state <= 0;
else if (arb.strobe)
state <= arb.grantee_i;
end
//ex: state 0, highest priority to L2_NUM_PORTS-1
always_comb begin
for (int i = 0; i < L2_NUM_PORTS; i++) begin
muxes[i] = $clog2(L2_NUM_PORTS)'(i);
for (int j = 0; j < L2_NUM_PORTS; j++) begin
if (arb.requests[(i+j) % L2_NUM_PORTS])
muxes[i] = $clog2(L2_NUM_PORTS)'((i+j) % L2_NUM_PORTS);
end
//ex: state 0, highest priority to L2_NUM_PORTS-1
always_comb begin
for (int i = 0; i < L2_NUM_PORTS; i++) begin
muxes[i] = $clog2(L2_NUM_PORTS)'(i);
for (int j = 0; j < L2_NUM_PORTS; j++) begin
if (arb.requests[(i + j) % L2_NUM_PORTS])
muxes[i] = $clog2(L2_NUM_PORTS)'((i + j) % L2_NUM_PORTS);
end
end
end
//Select mux output based on current state
assign arb.grantee_i = muxes[state];
//Select mux output based on current state
assign arb.grantee_i = muxes[state];
//Integer to one-hot
always_comb begin
arb.grantee_v = '0;
arb.grantee_v[arb.grantee_i] = 1;
end
//any valid request
assign arb.grantee_valid = |arb.requests;
always_comb begin
arb.grantee_v = '0;
arb.grantee_v[arb.grantee_i] = 1;
end
//any valid request
assign arb.grantee_valid = |arb.requests;
end
endgenerate
endmodule

2
test_benches/verilator/taiga_sim.sv
View file

@ -454,7 +454,7 @@ module taiga_sim
} spec_table_t;
spec_table_t translation [32];
genvar i, j;
generate for (i = 0; i < 32; i++) begin
generate for (i = 0; i < 32; i++) begin : gen_reg_file_sim
for (j = 0; j < EXAMPLE_CONFIG.NUM_WB_GROUPS; j++) begin
if (FPGA_VENDOR == XILINX)
assign translation[i] = cpu.renamer_block.spec_table_ram.xilinx_gen.ram[i];