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https://github.com/openhwgroup/cva5.git
synced 2025-04-20 03:57:18 -04:00
embench benchmarks added and binary tool made more robust
This commit is contained in:
Eric Matthews
parent
553a193a3c
commit
976ad3d5ee
3 changed files with 83 additions and 37 deletions
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@ -50,7 +50,7 @@ int main(int argc, char **argv) {
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VerilatedVcdC *tracer;
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tracer = new VerilatedVcdC;
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tb->trace(tracer, 99);
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tracer->open("sim_results.vcd");
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tracer->open("/data/sim-logs/sim_results.vcd");
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#endif
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cout << "--------------------------------------------------------------\n";
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@ -2,9 +2,9 @@
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MAKEFLAGS += --silent
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MAKEFILE_DIR=$(pwd)
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TAIGA_DIR=..
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TAIGA_DIR=/home/ematthew/taiga
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RISCV_PREFIX ?= riscv32-newlib-elf-
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RISCV_PREFIX ?= riscv32-unknown-elf-
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#Verilator parameters
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@ -24,7 +24,7 @@ export RANLIB
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#Compiance parameters
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###############################################################
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COMPLIANCE_DIR=/home/ematthew/Research/RISCV/riscv-compliance/
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COMPLIANCE_DIR=/home/ematthew/Research/RISCV/software/riscv-compliance/
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COMPLIANCE_TARGET=rv32im
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###############################################################
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@ -45,9 +45,37 @@ BENCHMARKS = \
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###############################################################
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#Benchmark parameters
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#Assumes binaries are in the BENCHMARK_DIR
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###############################################################
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EMBENCH_DIR=/home/ematthew/Research/RISCV/software/embench/build/src
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EMBENCH_BENCHMARKS = \
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aha-mont64 \
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crc32 \
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cubic \
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edn \
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huffbench \
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matmult-int \
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minver \
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nbody \
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nettle-aes \
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nettle-sha256 \
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nsichneu \
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picojpeg \
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qrduino \
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sglib-combined \
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slre \
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st \
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statemate \
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ud \
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wikisort \
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###############################################################
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#Binary to Verilog HW init file
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###############################################################
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ELF_TO_HW_INIT ?= python3 taiga_binary_converter.py $(RISCV_PREFIX) 0x80000000 131072
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ELF_TO_HW_INIT ?= python3 $(TAIGA_DIR)/tools/taiga_binary_converter.py $(RISCV_PREFIX) 0x80000000 131072
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###############################################################
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@ -58,7 +86,7 @@ define verilator_local_mem_test
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mkdir -p $@
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cp $(VERILATOR_DIR)/taiga_local_mem.cc $@/
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verilator -cc --exe --Mdir $@ $(VERILATOR_LINT_IGNORE) $(VERILATOR_CFLAGS) $(TAIGA_SRCS) \
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../test_benches/verilator/taiga_local_mem.sv --top-module taiga_local_mem taiga_local_mem.cc \
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../test_benches/verilator/taiga_local_mem.sv --top-module taiga_local_mem taiga_local_mem.cc \
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-GMEMORY_FILE=$1
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$(MAKE) -C $@ -f Vtaiga_local_mem.mk AR="gcc-ar" RANLIB="gcc-ranlib"
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time ./$@/Vtaiga_local_mem $2 $3
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@ -69,7 +97,7 @@ lint:
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verilator -cc $(TAIGA_SRCS) \
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../test_benches/verilator/taiga_local_mem.sv \
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--top-module taiga_local_mem \
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--lint-only -Wno-WIDTH
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--lint-only
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.PHONY: verilator_taiga_dhrystone
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verilator_taiga_dhrystone:
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@ -81,6 +109,15 @@ verilator_taiga_benchmarks:
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$(call verilator_local_mem_test,\"$(BENCHMARK_DIR)$(BENCHMARK).riscv.hw_init\", $@/$(BENCHMARK).log, "/dev/null") \
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)
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.PHONY: verilator_taiga_embench
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verilator_taiga_embench:
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$(foreach BENCHMARK,$(EMBENCH_BENCHMARKS), \
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cd $(EMBENCH_DIR)/$(BENCHMARK); \
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$(ELF_TO_HW_INIT) $(BENCHMARK) $(BENCHMARK).hw_init $(BENCHMARK).sim_init; \
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cd $(TAIGA_DIR)/tools; \
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$(call verilator_local_mem_test,\"$(EMBENCH_DIR)/$(BENCHMARK)/$(BENCHMARK).hw_init\", $@/$(BENCHMARK).log, "/dev/null"); \
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)
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#Called by compliance makefile
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.PHONY: verilator_taiga_compliance_unit_test
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verilator_taiga_compliance_unit_test:
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@ -88,11 +125,12 @@ verilator_taiga_compliance_unit_test:
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.PHONY: verilator_taiga_compliance_tests
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verilator_taiga_compliance_tests:
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$(MAKE) -C $(COMPLIANCE_DIR) clean
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$(MAKE) -C $(COMPLIANCE_DIR) RISCV_TARGET=taiga RISCV_DEVICE=$(COMPLIANCE_TARGET) RISCV_PREFIX=$(RISCV_PREFIX)
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.PHONY: verilator_taiga_coremark
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verilator_taiga_coremark:
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$(MAKE) -C $(COREMARK_DIR) compile PORT_DIR=taiga-sim ITERATIONS=5000
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$(MAKE) -C $(COREMARK_DIR) compile PORT_DIR=taiga-sim ITERATIONS=5000;
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cd $(MAKEFILE_DIR);
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$(ELF_TO_HW_INIT) $(COREMARK_DIR)/coremark.bin coremark.hw_init coremark.sim_init
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$(call verilator_local_mem_test,\"coremark.hw_init\", "coremark.log", "coremark.sig")
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@ -1,5 +1,5 @@
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#
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# Copyright © 2017 Eric Matthews, Lesley Shannon
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# Copyright © 2017-2019 Eric Matthews, Lesley Shannon
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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@ -52,15 +52,16 @@ parser.add_argument('--quiet', '-q', help='Suppresses diagnostic output ', actio
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args = parser.parse_args()
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# open input file
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subprocess.run([args.toolPrefix + 'objdump', '-Dzs', args.inputFile], stdout=open(args.inputFile + '.dumpDzs', "w"))
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subprocess.run([args.toolPrefix + 'objdump', '-d', args.inputFile], stdout=open(args.inputFile + '.dumpd', "w"))
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print(args.inputFile)
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subprocess.run([args.toolPrefix + 'objcopy', '--gap-fill=0x00', '-O', 'binary', args.inputFile, args.inputFile + '.rawbinary'])
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subprocess.run([args.toolPrefix + 'objdump', '-fd', '--prefix-addresses', args.inputFile], stdout=open(args.inputFile + '.dissasembled', "w"))
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try:
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program_input = open(args.inputFile + '.dumpDzs', 'r')
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opcode_input = open(args.inputFile + '.dumpd', 'r')
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program_input = open(args.inputFile + '.rawbinary', 'rb')
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opcode_input = open(args.inputFile + '.dissasembled', 'r')
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except IOError:
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print('Could not open files: ', args.inputFile + '.dumpDzs ', args.inputFile + '.dumpd')
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print('Could not open files: ', args.inputFile + '.raw ', args.inputFile + '.dissasembled')
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sys.exit()
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program_output = args.inputFile + '.bin'
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@ -82,37 +83,44 @@ except IOError:
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print('array size ', int(int(args.ramSize)/4))
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#Initialize with zero
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ramData = ['00000000'] * int((int(args.ramSize)/4));
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lineRegex = re.compile(r'\s+')
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instLineRegex = re.compile(r'\s+|:\s+')
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dataLineRegex = re.compile(r' [a-f0-9]{8}\s+')
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instLineRegex = re.compile(r'\s+')
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isInstLine = re.compile(r'[a-f0-9]{8}\s+<\S+') #pattern hexaddress <function name and offset> instruction
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#parses the block output format
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addressRegex = re.compile(r'0x[a-f0-9]{8}')
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hexRegex = re.compile(r'[a-f0-9]{8}')
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#parses the block output format
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for line in program_input:
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lineContents = lineRegex.split(line)
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if (dataLineRegex.match(line) != None) :
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index = int((int(lineContents[1],16) - int(args.baseAddr,16))/4)
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for entry in lineContents[2:]: #skip address
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if (hexRegex.match(entry)) :
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ramData[index] = stringByteSwap(entry)
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index+=1
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#Find start address and lowest address in dissasembly file
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index = 0
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lowestAddress = sys.maxsize
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for line in opcode_input:
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if (isInstLine.match(line)) :
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addressMatch = hexRegex.match(line)
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if (int(addressMatch[0],16) < lowestAddress) :
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lowestAddress = int(addressMatch[0],16)
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index = int(lowestAddress/4) - int(int(args.baseAddr,16)/4)
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if (line.find('start address') != -1) :
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addressMatch = addressRegex.search(line)
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print('start address: ', addressMatch[0])
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#Reads binary 4 bytes at a time and converts to Verilog readmemh format
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word = program_input.read(4)
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while word != b"":
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ramData[index] = stringByteSwap(word.hex())
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index+=1
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word = program_input.read(4)
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program_output.write('\n'.join(str(line) for line in ramData))
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#overwrite instruction entries with instruction info
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#<ins hex> <opcode> <instruction details>...
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#append instruction details to data
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opcode_input.seek(0)
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for line in opcode_input:
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lineContents = instLineRegex.split(line)
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if (hexRegex.match(lineContents[0])) :
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if (isInstLine.match(line)) :
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lineContents = list(filter(None, instLineRegex.split(line))) #split line and remove empty strings
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index = int((int(lineContents[0],16) - int(args.baseAddr,16))/4)
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for entry in lineContents[1:]: #skip address
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ramData[index] = lineContents[1] + ' ' + ' '.join(lineContents[2:])
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ramData[index] += ' ' + ' '.join(lineContents[1:])
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sim_output.write(' --\n'.join(str(line) for line in ramData))
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sim_output.write(' --')
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