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https://github.com/openhwgroup/cva5.git
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bug fixes
This commit is contained in:
Eric Matthews
parent
f164ef291d
commit
9df3814782
9 changed files with 79 additions and 67 deletions
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@ -119,24 +119,23 @@ module branch_unit(
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generate if (ENABLE_M_MODE) begin
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always_ff @(posedge clk) begin
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if (instruction_is_completing | ~branch_issued_r)
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if (instruction_is_completing | ~branch_issued_r) begin
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jmp_id <= issue.id;
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branch_exception_is_jump <= (branch_inputs.jal | branch_inputs.jalr);
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end
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end
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assign potential_branch_exception = new_pc[1] & issue.new_request;
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assign branch_exception_is_jump = (branch_inputs.jal | branch_inputs.jalr);
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assign br_exception.valid = new_pc_ex[1] & branch_taken_ex & branch_issued_r;
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assign br_exception.code = INST_ADDR_MISSALIGNED;
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assign br_exception.tval = new_pc_ex;
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assign br_exception.id = jmp_id;
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end
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endgenerate
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////////////////////////////////////////////////////
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//ID Management
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assign branch_complete = (instruction_is_completing & ~jal_jalr_ex);
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assign branch_complete = instruction_is_completing & (~jal_jalr_ex) & (~br_exception.valid);
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assign branch_id = id_ex;
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////////////////////////////////////////////////////
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@ -39,7 +39,6 @@ module csr_regs
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input exception_packet_t gc_exception,
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output exception_packet_t csr_exception,
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output logic [1:0] current_privilege,
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input logic gc_supress_writeback,
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input logic [31:0] exception_pc,
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//exception_control
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@ -55,7 +54,6 @@ module csr_regs
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mmu_interface.csr dmmu,
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//WB
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input logic instruction_retired,
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input logic [$clog2(MAX_COMPLETE_COUNT)-1:0] retire_inc,
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//External
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@ -124,14 +122,13 @@ module csr_regs
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//convert addr into packed struct form
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assign csr_addr = csr_inputs.csr_addr;
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assign supervisor_write = commit && (csr_addr.rw_bits != CSR_READ_ONLY && csr_addr.privilege == SUPERVISOR_PRIVILEGE);
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assign machine_write = commit && (csr_addr.rw_bits != CSR_READ_ONLY && csr_addr.privilege == MACHINE_PRIVILEGE);
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////////////////////////////////////////////////////
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//Exception Check
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assign privilege_exception = new_request & (csr_addr.privilege > privilege_level);
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assign supervisor_write = commit && !privilege_exception && (csr_addr.rw_bits != CSR_READ_ONLY && csr_addr.privilege == SUPERVISOR_PRIVILEGE);
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assign machine_write = commit && !privilege_exception && (csr_addr.rw_bits != CSR_READ_ONLY && csr_addr.privilege == MACHINE_PRIVILEGE);
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logic illegal_instruction;
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assign illegal_instruction = invalid_addr | privilege_exception;
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assign csr_exception.valid = new_request & illegal_instruction;
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assign csr_exception.valid = new_request & (invalid_addr | privilege_exception);
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always_comb begin
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case (csr_inputs.csr_op)
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@ -43,6 +43,7 @@ module decode_and_issue (
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output div_inputs_t div_inputs,
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unit_issue_interface.decode unit_issue [NUM_UNITS-1:0],
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input logic potential_branch_exception,
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output logic alu_issued,
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input logic gc_issue_hold,
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@ -297,7 +298,7 @@ module decode_and_issue (
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assign alu_inputs.shifter_in = rs_data[RS1];
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assign alu_inputs.shift_amount = issue.opcode[5] ? rs_data[RS2][4:0] : issue.rs_addr[RS2];
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assign alu_issued = issue_to[ALU_UNIT_WB_ID];
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assign alu_issued = issue_to[ALU_UNIT_WB_ID] & ~potential_branch_exception;
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////////////////////////////////////////////////////
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//Load Store unit inputs
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@ -534,8 +535,8 @@ module decode_and_issue (
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////////////////////////////////////////////////////
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//Trace Interface
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generate if (ENABLE_TRACE_INTERFACE) begin
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assign tr_operand_stall = |(unit_needed_issue_stage & unit_ready) & issue_valid & ~|(unit_operands_ready & issue_ready);
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assign tr_unit_stall = ~|(unit_needed_issue_stage & unit_ready) & issue_valid & |(unit_operands_ready & issue_ready);
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assign tr_operand_stall = |(unit_needed_issue_stage & unit_ready) & issue_valid & ~|(unit_operands_ready & unit_needed_issue_stage);
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assign tr_unit_stall = ~|(unit_needed_issue_stage & unit_ready) & issue_valid & |(unit_operands_ready & unit_needed_issue_stage);
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assign tr_no_id_stall = 0;
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assign tr_no_instruction_stall = ~issue.stage_valid | gc_fetch_flush;
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assign tr_other_stall = issue.stage_valid & ~instruction_issued & ~(tr_operand_stall | tr_unit_stall | tr_no_id_stall | tr_no_instruction_stall);
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@ -38,13 +38,14 @@ module gc_unit(
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input logic branch_flush,
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//instruction misalignement
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input logic potential_branch_exception,
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input exception_packet_t br_exception,
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input logic branch_exception_is_jump,
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input exception_packet_t br_exception,
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//Illegal instruction
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input logic illegal_instruction,
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//Load Store Unit
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input exception_packet_t ls_exception,
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input logic ls_exception_is_store,
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//TLBs
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output logic tlb_on,
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@ -60,7 +61,6 @@ module gc_unit(
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output id_t system_op_or_exception_id,
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//Exception
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output id_t exception_id,
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input logic [31:0] exception_pc,
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//WB
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@ -105,40 +105,25 @@ module gc_unit(
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//SFENCE
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// flush and hold fetch, wait until L/S input FIFO empty, hold fetch until TLB update complete
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//ECALL, EBREAK, SRET, MRET:
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// flush fetch, update CSRs (could be illegal instruction exception as well)
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// flush fetch, update to CSRs is pipelined
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//Interrupt
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//Hold issue, wait until IDLE state, flush fetch, take exception
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//wait until issue/execute exceptions are no longer possible, flush fetch, take exception
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//Fetch Exception
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//flush fetch, wait until IDLE state, take exception. If decode stage or later exception occurs first, exception is overridden
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//Fetch Exception (TLB and MMU) (fetch stage)
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//flush fetch, wait until issue/execute exceptions are no longer possible, take exception. If decode stage or later exception occurs first, exception is overridden
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//Illegal opcode (decode stage)
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//fetch flush, issue hold, wait until IDLE state, take exception. If execute or later exception occurs first, exception is overridden
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//Illegal opcode (issue stage)
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//fetch flush, take exception. If execute or later exception occurs first, exception is overridden
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//CSR exceptions
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//fetch flush, issue hold, capture ID/rd_non_zero and drain instruction queue, take exception.
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//Branch exceptions (issue/execute stage)
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//fetch flush, take exception.
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//LS exceptions (miss-aligned, TLB and MMU)
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//fetch flush, issue hold, capture ID/rd_non_zero and drain instruction queue, take exception.
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//CSR exceptions (issue/execute stage)
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//fetch flush, take exception.
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//Instruction queue drain:
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// Two possibilities:
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// 1. Instruction stores to reg file. ID in instruction queue, wait until that ID is oldest (either find oldest valid, or for small cycle penalty just look at last entry and wait for ID and valid)
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// 2. Instruction does not store to reg file. If IQ not empty, wait for previously issued ID to complete, if empty no waiting required.
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//
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// After all preceding instructions have been committed, continue popping instructions from queue but supress write-back operation until queue is drained.
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//In-order mode:
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// Turn on when an instruction in the execute phase could cause an interrupt (L/S or CSR)
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// Turn off when exception can no-longer occur (after one cycle for CSR, when L/S input FIFO will be empty)
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//*Complete issued instructions before exception
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//*Drain L/S FIFO then Hold fetch/issue during TLB clear
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//*Hold fetch until all stores committed
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//*Turn on inorder mode when L/S issued, turn off when no instruction can cause interrupt
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// *If in-order mode and inflight queue empty, disable zero cycle write-back (eg. ALU)
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//*Hold fetch during potential fetch exception, when fetch buffer drained, if no other exceptions trigger exception
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//LS exceptions (miss-aligned, TLB and MMU) (issue stage)
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//fetch flush, take exception. If execute or later exception occurs first, exception is overridden
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typedef enum {RST_STATE, IDLE_STATE, TLB_CLEAR_STATE, IQ_DRAIN} gc_state;
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gc_state state;
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@ -157,6 +142,9 @@ module gc_unit(
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logic [XLEN-1:0] wb_csr;
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csr_inputs_t csr_inputs;
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exception_packet_t gc_exception;
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exception_packet_t gc_exception_r;
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id_t exception_or_system_id;
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exception_packet_t csr_exception;
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logic [1:0] current_privilege;
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logic [31:0] trap_pc;
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@ -178,21 +166,24 @@ module gc_unit(
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logic csr_ready_to_complete_r;
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id_t instruction_id;
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//implementation
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////////////////////////////////////////////////////
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//Implementation
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//Input registering
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always_ff @(posedge clk) begin
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if (issue.possible_issue) begin
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if (issue.possible_issue & ~gc_issue_hold) begin
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stage1 <= gc_inputs;
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end
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end
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////////////////////////////////////////////////////
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//ID Management
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assign system_op_or_exception_complete =
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(issue.new_request & (gc_inputs.is_fence | gc_inputs.is_i_fence)) |
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gc_exception.valid;
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assign exception_with_rd_complete = ls_exception.valid;
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assign system_op_or_exception_id = issue.new_request ? issue.id : exception_id;
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always_ff @(posedge clk) begin
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system_op_or_exception_complete <=
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(issue.new_request & (gc_inputs.is_ret | gc_inputs.is_fence | gc_inputs.is_i_fence)) |
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gc_exception.valid;
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system_op_or_exception_id <= exception_or_system_id;
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exception_with_rd_complete <= (ls_exception.valid & ~ls_exception_is_store) | (br_exception.valid & branch_exception_is_jump);
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end
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//Instruction decode
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assign opcode = stage1.instruction[6:0];
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@ -206,7 +197,7 @@ module gc_unit(
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assign gc_fetch_flush = branch_flush | gc_fetch_pc_override;
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always_ff @ (posedge clk) begin
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gc_issue_hold <= issue.new_request || processing_csr || (next_state inside {TLB_CLEAR_STATE, IQ_DRAIN}) || potential_branch_exception;
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gc_issue_hold <= issue.new_request || second_cycle_flush || processing_csr || (next_state inside {TLB_CLEAR_STATE, IQ_DRAIN}) || potential_branch_exception;
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end
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always_ff @ (posedge clk) begin
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@ -234,7 +225,7 @@ module gc_unit(
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case (state)
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RST_STATE : next_state = IDLE_STATE;
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IDLE_STATE : begin
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if (ls_exception.valid | (branch_exception_is_jump & potential_branch_exception)) begin
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if (ls_exception.valid | potential_branch_exception) begin
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next_state = IQ_DRAIN;
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end
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end
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@ -266,8 +257,8 @@ module gc_unit(
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endcase
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end
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assign exception_id =
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potential_branch_exception ? br_exception.id :
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assign exception_or_system_id =
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br_exception.valid ? br_exception.id :
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(ls_exception.valid ? ls_exception.id : issue.id);
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//TODO: check if possible to convert to unique if, verify potential for overlap
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@ -298,6 +289,7 @@ module gc_unit(
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//Two cycles: on first cycle the processor front end is flushed,
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//on the second cycle the new PC is fetched
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always_ff @ (posedge clk) begin
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gc_exception_r <= gc_exception;
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second_cycle_flush <= gc_flush_required;
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gc_fetch_pc_override <= gc_flush_required | second_cycle_flush | ls_exception.valid | br_exception.valid;
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if (gc_exception.valid | stage1.is_i_fence | (issue.new_request & gc_inputs.is_ret)) begin
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@ -315,7 +307,30 @@ module gc_unit(
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assign csr_inputs.rs1_is_zero = (rs1_addr == 0);
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assign csr_inputs.rd_is_zero = (rd_addr == 0);
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csr_regs csr_registers (.*, .new_request(stage1.is_csr), .read_regs(csr_ready_to_complete), .commit(csr_ready_to_complete_r));
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csr_regs csr_registers (
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.clk(clk), .rst(rst),
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.csr_inputs(csr_inputs),
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.new_request(stage1.is_csr),
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.read_regs(csr_ready_to_complete),
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.commit(csr_ready_to_complete_r),
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.gc_exception(gc_exception_r),
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.csr_exception(csr_exception),
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.current_privilege(current_privilege),
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.exception_pc(exception_pc),
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.mret(mret),
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.sret(sret),
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.tlb_on(tlb_on),
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.asid(asid),
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.immu(immu),
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.dmmu(dmmu),
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.retire_inc(retire_inc),
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.interrupt(interrupt),
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.timer_interrupt(timer_interrupt),
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.wb_csr(wb_csr),
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.trap_pc(trap_pc),
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.csr_mepc(csr_mepc),
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.csr_sepc(csr_sepc)
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);
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////////////////////////////////////////////////////
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//Decode / Write-back Handshaking
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@ -75,7 +75,6 @@ module instruction_metadata_and_id_management
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output logic [4:0] retired_rd_addr [COMMIT_PORTS],
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output id_t id_for_rd [COMMIT_PORTS],
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//Exception
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input id_t exception_id,
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output logic [31:0] exception_pc
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);
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@ -336,7 +335,7 @@ module instruction_metadata_and_id_management
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always_comb begin
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for (int i = 0; i < REGFILE_READ_PORTS; i++) begin
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rs_id[i] = rd_to_id_table[issue.rs_addr[i]];
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rs_inuse[i] = (issue.rs_addr[i] == instruction_table[rs_id[i]][11:7]);//11:7 is rd_addr
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rs_inuse[i] = (|issue.rs_addr[i]) & (issue.rs_addr[i] == instruction_table[rs_id[i]][11:7]);//11:7 is rd_addr
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end
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end
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@ -350,7 +349,7 @@ module instruction_metadata_and_id_management
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//Exception Support
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generate if (ENABLE_M_MODE) begin
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assign exception_pc = pc_table[exception_id];
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assign exception_pc = pc_table[system_op_or_exception_id];
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end endgenerate
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////////////////////////////////////////////////////
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@ -149,7 +149,7 @@ module load_store_queue //ID-based input buffer for Load/Store Unit
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if (new_forwarded_store)
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needed_id_r <= lsq.data_id;
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end
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assign wb_store.id_needed = possible_new_forwarded_store ? lsq.data_id : needed_id_r;
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assign wb_store.id_needed = waiting_r ? needed_id_r : lsq.data_id;
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@ -159,7 +159,6 @@ module load_store_queue //ID-based input buffer for Load/Store Unit
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assign oldest_lsq_entry = lsq_entries[oldest_id];
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assign lsq.transaction_ready = oldest_fifo.valid & (~oldest_lsq_entry.forwarded_store | wb_store.id_done);
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assign lsq.id_needed_by_store = oldest_lsq_entry.data_id;
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always_comb begin
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lsq.transaction_out.addr = oldest_lsq_entry.addr;
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@ -62,6 +62,7 @@ module load_store_unit (
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output logic ls_is_idle,
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output exception_packet_t ls_exception,
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output logic ls_exception_is_store,
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unit_writeback_interface.unit wb
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);
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@ -138,7 +139,7 @@ generate if (ENABLE_M_MODE) begin
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default : unaligned_addr = 0;
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endcase
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end
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assign ls_exception_is_store = ls_inputs.store;
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assign ls_exception.valid = unaligned_addr & issue.new_request;
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assign ls_exception.code = ls_inputs.store ? STORE_AMO_ADDR_MISSALIGNED : LOAD_ADDR_MISSALIGNED;
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assign ls_exception.tval = virtual_address;
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@ -228,7 +229,7 @@ endgenerate
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assign ready_for_issue = units_ready & (~unit_switch_stall);
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assign issue.ready = lsq.ready & ~(ls_inputs.forwarded_store & ~ready_for_forwarded_store);
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assign issue.ready = ls_inputs.forwarded_store ? lsq.ready & ready_for_forwarded_store : lsq.ready;
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assign issue_request = lsq.accepted;
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////////////////////////////////////////////////////
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@ -241,7 +242,7 @@ endgenerate
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assign load_attributes.data_in = load_attributes_in;
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assign load_attributes.push = issue_request & shared_inputs.load;
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assign load_attributes.potential_push = ~load_attributes.full;
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assign load_attributes.potential_push = issue_request & shared_inputs.load;
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assign load_attributes.pop = load_complete;
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assign stage2_attr = load_attributes.data_out;
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@ -52,7 +52,7 @@ module mul_unit(
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assign rs1_ext = signed'({mul_inputs.rs1[31] & rs1_signed, mul_inputs.rs1});
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assign rs2_ext = signed'({mul_inputs.rs2[31] & rs2_signed, mul_inputs.rs2});
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assign issue.ready = stage1_advance;
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assign issue.ready = (~done[0] | ~done[1]);//stage1_advance;
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assign stage1_advance = ~done[0] | stage2_advance;
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assign stage2_advance = ~done[1] | wb.ack;
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@ -72,6 +72,7 @@ module taiga (
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logic alu_issued;
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exception_packet_t ls_exception;
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logic ls_exception_is_store;
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unit_writeback_interface unit_wb [NUM_WB_UNITS]();
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