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Remove broken legacy tests
This commit is contained in:
Chris Keilbart
parent
f5a5ee7406
commit
a0f6e3cc54
9 changed files with 0 additions and 2452 deletions
1
.gitignore
vendored
1
.gitignore
vendored
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test_benches/verilator/build
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@ -1,212 +0,0 @@
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/*
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* Copyright © 2017 Eric Matthews, Lesley Shannon
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* Initial code developed under the supervision of Dr. Lesley Shannon,
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* Reconfigurable Computing Lab, Simon Fraser University.
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*
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* Author(s):
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* Eric Matthews <ematthew@sfu.ca>
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*/
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//No error checking for incorrect ordering of axi control signals from Master side of interface
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import tb_tools::*;
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import cva5_config::*;
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module axi_mem_sim
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#(parameter string file_name = "")
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(
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input logic clk,
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input logic rst,
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axi_interface.slave axi,
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input logic[31:0] if_pc,
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input logic[31:0] dec_pc
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);
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typedef struct packed{
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logic [31:0] araddr;
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logic [7:0] arlen;
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logic [2:0] arsize;
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logic [1:0] arburst;
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logic [3:0] arcache;
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logic [5:0] arid;
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} read_request;
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typedef struct packed{
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logic [31:0] awaddr;
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logic [7:0] awlen;
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logic [2:0] awsize;
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logic [1:0] awburst;
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logic [3:0] awcache;
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logic [5:0] awid;
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} write_request;
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const int READ_QUEUE_DEPTH = 8;
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const int WRITE_QUEUE_DEPTH = 4;
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const int WRITE_DATA_QUEUE_DEPTH = 128;
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integer write_queue_size;
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integer read_data_queue_size;
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logic[47:0] write_request_count;
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logic[47:0] read_request_count;
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int read_burst_count;
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int processing_read_request;
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int processing_write_request;
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read_request read_queue[$];
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write_request write_queue[$];
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logic [31:0] write_data_queue[$];
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logic [31:0] read_data_queue[$];
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sim_mem ddr = new();
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//For opcode inspection
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string dec_opcode;
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string if_opcode;
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logic[0:64*8-1] if_inst_text;
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logic[0:64*8-1] dec_inst_text;
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/////////////////////
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function void getReadData (bit[31:0] addr, bit[7:0] len);
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for (int i = 0; i <= len; i=i+1) begin
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read_data_queue.push_back(ddr.readw(addr[31:2]+i));
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end
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endfunction
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//Simulation opcode support
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assign if_opcode = ddr.readopcode(if_pc[31:2]);
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assign dec_opcode = ddr.readopcode(dec_pc[31:2]);
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genvar i;
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generate
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for(i=0; i<64; i=i+1) begin
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always_comb begin
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if_inst_text[8*i: 8*(i+1) -1]=if_opcode[i];
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dec_inst_text[8*i: 8*(i+1) -1]=dec_opcode[i];
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end
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end
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endgenerate
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///////////////////
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initial begin
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ddr.load_program(file_name, RESET_VEC);
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end
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//arready response
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assign axi.arready = read_queue.size() < READ_QUEUE_DEPTH;
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//Read request processing
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always_ff @(posedge clk) begin
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if (rst) begin
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read_request_count <= 0;
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end
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else if(axi.arvalid & axi.arready) begin
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read_queue.push_back(
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{axi.araddr, axi.arlen, axi.arsize, axi.arburst, axi.arcache, axi.arid}
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);
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getReadData(axi.araddr, axi.arlen);
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read_request_count <=read_request_count+1;
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end
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end
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//Write request processing
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always_ff @(posedge clk) begin
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if(axi.awvalid & axi.awready) begin
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write_queue.push_back(
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{axi.awaddr, axi.awlen, axi.awsize, axi.awburst, axi.awcache, axi.awid}
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);
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end
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write_queue_size <= write_queue.size();
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end
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assign axi.awready = write_queue.size() < WRITE_QUEUE_DEPTH;
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assign axi.wready = write_data_queue.size() < WRITE_DATA_QUEUE_DEPTH;
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//bresp
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always_ff @(posedge clk) begin
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if (rst) begin
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axi.bvalid <= 0;
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end
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else if(axi.wvalid & axi.wlast) begin
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axi.bresp <= 0;
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axi.bvalid <=1;
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axi.bid <= write_queue[0].awid;
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write_queue.pop_front();
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end
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else if (axi.bready) begin
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axi.bvalid <=0;
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end
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end
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always_ff @(posedge clk) begin
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if (rst) begin
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write_request_count <= 0;
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end
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else if(axi.wvalid) begin
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write_request_count <= write_request_count + 1;
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end
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end
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//Handle write data
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always_ff @(posedge clk) begin
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if (rst) begin
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end
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else if(axi.wvalid) begin
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ddr.writew(write_queue.size > 0 ? write_queue[0].awaddr[31:2] : axi.awaddr[31:2], axi.wdata, axi.wstrb);
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end
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end
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always_ff @(posedge clk) begin
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read_data_queue_size <= read_data_queue.size();
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end
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//Return data
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always_ff @(posedge clk) begin
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if(rst) begin
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axi.rvalid <= 0;
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axi.rlast <= 0;
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read_burst_count <= 0;
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end
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else if(read_queue.size > 0) begin
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if(axi.rready) begin
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axi.rdata <= read_data_queue.pop_front();
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axi.rvalid <= 1;
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axi.rid <= read_queue[0].arid;
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if( read_queue[0].arlen == read_burst_count) begin
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axi.rlast <= 1;
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read_queue.pop_front();
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read_burst_count <= 0;
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end
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else begin
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read_burst_count <= read_burst_count + 1;
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axi.rlast <= 0;
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end
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end
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else begin
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axi.rvalid <= 0;
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axi.rlast <= 0;
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end
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end
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else begin
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axi.rvalid <= 0;
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axi.rlast <= 0;
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end
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end
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endmodule
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@ -1,341 +0,0 @@
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/*
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* Copyright © 2017 Eric Matthews, Lesley Shannon
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* Initial code developed under the supervision of Dr. Lesley Shannon,
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* Reconfigurable Computing Lab, Simon Fraser University.
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*
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* Author(s):
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* Eric Matthews <ematthew@sfu.ca>
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*/
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`timescale 1ns/1ns
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`define MEMORY_FILE "/home/ematthew/Research/RISCV/software/riscv-tools/riscv-tests/benchmarks/dhrystone.riscv.sim_init"
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`define UART_LOG "/home/ematthew/uart.log"
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module cva5_tb
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import tb_tools::*;
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import cva5_config::*;
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import l2_config_and_types::*;
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import riscv_types::*;
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import cva5_types::*;
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( );
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logic simulator_clk;
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logic simulator_resetn;
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//axi block diagram inputs
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logic axi_clk;
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logic resetn;
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logic sin;
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//AXI memory
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logic [31:0]axi_araddr;
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logic [1:0]axi_arburst;
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logic [3:0]axi_arcache;
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logic [5:0]axi_arid;
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logic [7:0]axi_arlen;
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logic [0:0]axi_arlock;
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logic [2:0]axi_arprot;
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logic [3:0]axi_arqos;
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logic axi_arready;
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logic [3:0]axi_arregion;
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logic [2:0]axi_arsize;
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logic axi_arvalid;
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logic [31:0]axi_awaddr;
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logic [1:0]axi_awburst;
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logic [3:0]axi_awcache;
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logic [5:0]axi_awid;
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logic [7:0]axi_awlen;
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logic [0:0]axi_awlock;
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logic [2:0]axi_awprot;
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logic [3:0]axi_awqos;
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logic axi_awready;
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logic [3:0]axi_awregion;
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logic [2:0]axi_awsize;
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logic axi_awvalid;
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logic [5:0]axi_bid;
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logic axi_bready;
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logic [1:0]axi_bresp;
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logic axi_bvalid;
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logic [31:0]axi_rdata;
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logic [5:0]axi_rid;
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logic axi_rlast;
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logic axi_rready;
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logic [1:0]axi_rresp;
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logic axi_rvalid;
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logic [31:0]axi_wdata;
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logic axi_wlast;
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logic axi_wready;
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logic [3:0]axi_wstrb;
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logic axi_wvalid;
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logic [5:0]axi_wid;
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axi_interface ddr_axi();
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logic [31:0]mem_axi_araddr;
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logic [1:0]mem_axi_arburst;
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logic [3:0]mem_axi_arcache;
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logic [5:0]mem_axi_arid;
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logic [7:0]mem_axi_arlen;
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logic [0:0]mem_axi_arlock;
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logic [2:0]mem_axi_arprot;
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logic [3:0]mem_axi_arqos;
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logic mem_axi_arready;
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logic [3:0]mem_axi_arregion;
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logic [2:0]mem_axi_arsize;
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logic mem_axi_arvalid;
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logic [31:0]mem_axi_awaddr;
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logic [1:0]mem_axi_awburst;
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logic [3:0]mem_axi_awcache;
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logic [5:0]mem_axi_awid;
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logic [7:0]mem_axi_awlen;
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logic [0:0]mem_axi_awlock;
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logic [2:0]mem_axi_awprot;
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logic [3:0]mem_axi_awqos;
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logic mem_axi_awready;
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logic [3:0]mem_axi_awregion;
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logic [2:0]mem_axi_awsize;
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logic mem_axi_awvalid;
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logic [5:0]mem_axi_bid;
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logic mem_axi_bready;
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logic [1:0]mem_axi_bresp;
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logic mem_axi_bvalid;
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logic [31:0]mem_axi_rdata;
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logic [5:0]mem_axi_rid;
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logic mem_axi_rlast;
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logic mem_axi_rready;
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logic [1:0]mem_axi_rresp;
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logic mem_axi_rvalid;
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logic [31:0]mem_axi_wdata;
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logic mem_axi_wlast;
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logic mem_axi_wready;
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logic [3:0]mem_axi_wstrb;
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logic mem_axi_wvalid;
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logic [5:0] mem_axi_wid;
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//AXI bus
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logic ACLK;
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logic [12:0]bus_axi_araddr;
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logic bus_axi_arready;
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logic bus_axi_arvalid;
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logic [12:0]bus_axi_awaddr;
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logic bus_axi_awready;
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logic bus_axi_awvalid;
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logic bus_axi_bready;
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logic [1:0]bus_axi_bresp;
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logic bus_axi_bvalid;
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logic [31:0]bus_axi_rdata;
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logic bus_axi_rready;
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logic [1:0]bus_axi_rresp;
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logic bus_axi_rvalid;
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logic [31:0]bus_axi_wdata;
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logic bus_axi_wready;
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logic [3:0]bus_axi_wstrb;
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logic bus_axi_wvalid;
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//axi block diagram outputs
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logic processor_reset;
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logic processor_clk;
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logic sout;
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logic clk;
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logic rst;
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//*****************************
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assign axi_clk = simulator_clk;
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assign resetn = simulator_resetn;
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assign clk = simulator_clk;
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assign rst = processor_reset;
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local_memory_interface instruction_bram();
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local_memory_interface data_bram();
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axi_interface m_axi();
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avalon_interface m_avalon();
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wishbone_interface dwishbone();
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l2_requester_interface l2[L2_NUM_PORTS-1:0]();
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l2_memory_interface mem();
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logic interrupt;
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logic timer_interrupt;
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logic[31:0] dec_pc_debug;
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logic[31:0] if2_pc_debug;
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integer output_file;
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assign l2[1].request = 0;
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assign l2[1].request_push = 0;
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assign l2[1].wr_data_push = 0;
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assign l2[1].inv_ack = l2[1].inv_valid;
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assign l2[1].rd_data_ack = l2[1].rd_data_valid;
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sim_mem simulation_mem = new();
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//RAM Block
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always_ff @(posedge processor_clk) begin
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if (instruction_bram.en) begin
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instruction_bram.data_out <= simulation_mem.readw(instruction_bram.addr);
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simulation_mem.writew(instruction_bram.addr,instruction_bram.data_in, instruction_bram.be);
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end
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else begin
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instruction_bram.data_out <= 0;
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end
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end
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always_ff @(posedge processor_clk) begin
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if (data_bram.en) begin
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data_bram.data_out <= simulation_mem.readw(data_bram.addr);
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simulation_mem.writew(data_bram.addr,data_bram.data_in, data_bram.be);
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end
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else begin
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data_bram.data_out <= 0;
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end
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end
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cva5 uut (.*, .l2(l2[0]));
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design_2 infra(.*);
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l2_arbiter l2_arb (.*, .request(l2));
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axi_to_arb l2_to_mem (.*, .l2(mem));
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axi_mem_sim #(`MEMORY_FILE) ddr_interface (.*, .axi(ddr_axi), .if_pc(if2_pc_debug), .dec_pc(dec_pc_debug));
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always
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#1 simulator_clk = ~simulator_clk;
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initial begin
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simulator_clk = 0;
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interrupt = 0;
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timer_interrupt = 0;
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simulator_resetn = 0;
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simulation_mem.load_program(`MEMORY_FILE, RESET_VEC);
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output_file = $fopen(`UART_LOG, "w");
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if (output_file == 0) begin
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$error ("couldn't open log file");
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$finish;
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end
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do_reset();
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#1800000;
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$fclose(output_file);
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$finish;
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end
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task do_reset;
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begin
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simulator_resetn = 1'b0;
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#500 simulator_resetn = 1'b1;
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end
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endtask
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assign m_axi.arready = bus_axi_arready;
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assign bus_axi_arvalid = m_axi.arvalid;
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assign bus_axi_araddr = m_axi.araddr[12:0];
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//read data
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assign bus_axi_rready = m_axi.rready;
|
||||
assign m_axi.rvalid = bus_axi_rvalid;
|
||||
assign m_axi.rdata = bus_axi_rdata;
|
||||
assign m_axi.rresp = bus_axi_rresp;
|
||||
|
||||
//Write channel
|
||||
//write address
|
||||
assign m_axi.awready = bus_axi_awready;
|
||||
assign bus_axi_awaddr = m_axi.awaddr[12:0];
|
||||
assign bus_axi_awvalid = m_axi.awvalid;
|
||||
|
||||
|
||||
//write data
|
||||
assign m_axi.wready = bus_axi_wready;
|
||||
assign bus_axi_wvalid = m_axi. wvalid;
|
||||
assign bus_axi_wdata = m_axi.wdata;
|
||||
assign bus_axi_wstrb = m_axi.wstrb;
|
||||
|
||||
//write response
|
||||
assign bus_axi_bready = m_axi.bready;
|
||||
assign m_axi.bvalid = bus_axi_bvalid;
|
||||
assign m_axi.bresp = bus_axi_bresp;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
assign ddr_axi.araddr = mem_axi_araddr;
|
||||
assign ddr_axi.arburst = mem_axi_arburst;
|
||||
assign ddr_axi.arcache = mem_axi_arcache;
|
||||
assign ddr_axi.arid = mem_axi_arid;
|
||||
assign ddr_axi.arlen = mem_axi_arlen;
|
||||
assign mem_axi_arready = ddr_axi.arready;
|
||||
assign ddr_axi.arsize = mem_axi_arsize;
|
||||
assign ddr_axi.arvalid = mem_axi_arvalid;
|
||||
|
||||
assign ddr_axi.awaddr = mem_axi_awaddr;
|
||||
assign ddr_axi.awburst = mem_axi_awburst;
|
||||
assign ddr_axi.awcache = mem_axi_awcache;
|
||||
assign ddr_axi.awid = mem_axi_awid;
|
||||
assign ddr_axi.awlen = mem_axi_awlen;
|
||||
assign mem_axi_awready = ddr_axi.awready;
|
||||
assign ddr_axi.awvalid = mem_axi_awvalid;
|
||||
|
||||
assign mem_axi_bid = ddr_axi.bid;
|
||||
assign ddr_axi.bready = mem_axi_bready;
|
||||
assign mem_axi_bresp = ddr_axi.bresp;
|
||||
assign mem_axi_bvalid = ddr_axi.bvalid;
|
||||
|
||||
assign mem_axi_rdata = ddr_axi.rdata;
|
||||
assign mem_axi_rid = ddr_axi.rid;
|
||||
assign mem_axi_rlast = ddr_axi.rlast;
|
||||
assign ddr_axi.rready = mem_axi_rready;
|
||||
assign mem_axi_rresp = ddr_axi.rresp;
|
||||
assign mem_axi_rvalid = ddr_axi.rvalid;
|
||||
|
||||
assign ddr_axi.wdata = mem_axi_wdata;
|
||||
assign ddr_axi.wlast = mem_axi_wlast;
|
||||
assign mem_axi_wready = ddr_axi.wready;
|
||||
assign ddr_axi.wstrb = mem_axi_wstrb;
|
||||
assign ddr_axi.wvalid = mem_axi_wvalid;
|
||||
|
||||
|
||||
//Capture writes to UART
|
||||
always_ff @(posedge processor_clk) begin
|
||||
if (m_axi.wvalid && bus_axi_wready && m_axi.awaddr[13:0] == 4096) begin
|
||||
$fwrite(output_file, "%c",m_axi.wdata[7:0]);
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
assign sin = 0;
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,958 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<wave_config>
|
||||
<wave_state>
|
||||
</wave_state>
|
||||
<db_ref_list>
|
||||
<db_ref path="cva5_tb_behav.wdb" id="1">
|
||||
<top_modules>
|
||||
<top_module name="glbl" />
|
||||
<top_module name="l2_config_and_types" />
|
||||
<top_module name="cva5_config" />
|
||||
<top_module name="cva5_tb" />
|
||||
<top_module name="cva5_types" />
|
||||
<top_module name="tb_tools" />
|
||||
</top_modules>
|
||||
</db_ref>
|
||||
</db_ref_list>
|
||||
<zoom_setting>
|
||||
<ZoomStartTime time="778020000fs"></ZoomStartTime>
|
||||
<ZoomEndTime time="788800001fs"></ZoomEndTime>
|
||||
<Cursor1Time time="781640000fs"></Cursor1Time>
|
||||
</zoom_setting>
|
||||
<column_width_setting>
|
||||
<NameColumnWidth column_width="297"></NameColumnWidth>
|
||||
<ValueColumnWidth column_width="112"></ValueColumnWidth>
|
||||
</column_width_setting>
|
||||
<WVObjectSize size="230" />
|
||||
<wvobject type="logic" fp_name="/cva5_tb/clk">
|
||||
<obj_property name="ElementShortName">clk</obj_property>
|
||||
<obj_property name="ObjectShortName">clk</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/rst">
|
||||
<obj_property name="ElementShortName">rst</obj_property>
|
||||
<obj_property name="ObjectShortName">rst</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="divider7358" type="divider">
|
||||
<obj_property name="label">Fetch</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/branch_unit_block/branch_inputs.jal">
|
||||
<obj_property name="ElementShortName">.jal</obj_property>
|
||||
<obj_property name="ObjectShortName">.jal</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/branch_unit_block/branch_inputs.jalr">
|
||||
<obj_property name="ElementShortName">.jalr</obj_property>
|
||||
<obj_property name="ObjectShortName">.jalr</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/branch_unit_block/branch_inputs.rs1">
|
||||
<obj_property name="ElementShortName">.rs1[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">.rs1[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/branch_unit_block/branch_inputs.is_call">
|
||||
<obj_property name="ElementShortName">.is_call</obj_property>
|
||||
<obj_property name="ObjectShortName">.is_call</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/branch_unit_block/branch_inputs.is_return">
|
||||
<obj_property name="ElementShortName">.is_return</obj_property>
|
||||
<obj_property name="ObjectShortName">.is_return</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/branch_unit_block/jal_imm">
|
||||
<obj_property name="ElementShortName">jal_imm[19:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">jal_imm[19:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/branch_unit_block/jalr_imm">
|
||||
<obj_property name="ElementShortName">jalr_imm[11:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">jalr_imm[11:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/branch_unit_block/br_imm">
|
||||
<obj_property name="ElementShortName">br_imm[11:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">br_imm[11:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/branch_unit_block/jump_base">
|
||||
<obj_property name="ElementShortName">jump_base[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">jump_base[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/branch_unit_block/pc_offset">
|
||||
<obj_property name="ElementShortName">pc_offset[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">pc_offset[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/bt/jump_pc">
|
||||
<obj_property name="ElementShortName">jump_pc[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">jump_pc[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/bt/njump_pc">
|
||||
<obj_property name="ElementShortName">njump_pc[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">njump_pc[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/fetch_block/next_pc">
|
||||
<obj_property name="ElementShortName">next_pc[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">next_pc[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/fetch_block/if_pc">
|
||||
<obj_property name="ElementShortName">if_pc[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">if_pc[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/bt_block/predicted_pc">
|
||||
<obj_property name="ElementShortName">predicted_pc[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">predicted_pc[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/bt/use_prediction">
|
||||
<obj_property name="ElementShortName">use_prediction</obj_property>
|
||||
<obj_property name="ObjectShortName">use_prediction</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/bt/use_ras">
|
||||
<obj_property name="ElementShortName">use_ras</obj_property>
|
||||
<obj_property name="ObjectShortName">use_ras</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/ras_block/ras/push">
|
||||
<obj_property name="ElementShortName">push</obj_property>
|
||||
<obj_property name="ObjectShortName">push</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/ras_block/ras/pop">
|
||||
<obj_property name="ElementShortName">pop</obj_property>
|
||||
<obj_property name="ObjectShortName">pop</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/ras_block/ras/new_addr">
|
||||
<obj_property name="ElementShortName">new_addr[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">new_addr[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/ras_block/ras/addr">
|
||||
<obj_property name="ElementShortName">addr[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">addr[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/ras_block/ras/valid">
|
||||
<obj_property name="ElementShortName">valid</obj_property>
|
||||
<obj_property name="ObjectShortName">valid</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/ras_block/read_index">
|
||||
<obj_property name="ElementShortName">read_index[2:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">read_index[2:0]</obj_property>
|
||||
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/ras_block/write_index">
|
||||
<obj_property name="ElementShortName">write_index[2:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">write_index[2:0]</obj_property>
|
||||
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/ddr_interface/if_inst_text">
|
||||
<obj_property name="ElementShortName">if_inst_text[0:511]</obj_property>
|
||||
<obj_property name="ObjectShortName">if_inst_text[0:511]</obj_property>
|
||||
<obj_property name="Radix">ASCIIRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/fetch_block/stage2_phys_address">
|
||||
<obj_property name="ElementShortName">stage2_phys_address[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">stage2_phys_address[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/fetch_block/inflight_count">
|
||||
<obj_property name="ElementShortName">inflight_count[2:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">inflight_count[2:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/fetch_block/space_in_inst_buffer">
|
||||
<obj_property name="ElementShortName">space_in_inst_buffer</obj_property>
|
||||
<obj_property name="ObjectShortName">space_in_inst_buffer</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/fetch_block/new_issue">
|
||||
<obj_property name="ElementShortName">new_issue</obj_property>
|
||||
<obj_property name="ObjectShortName">new_issue</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/fetch_block/new_mem_request">
|
||||
<obj_property name="ElementShortName">new_mem_request</obj_property>
|
||||
<obj_property name="ObjectShortName">new_mem_request</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/fetch_block/bt/flush">
|
||||
<obj_property name="ElementShortName">flush</obj_property>
|
||||
<obj_property name="ObjectShortName">flush</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/fetch_block/delayed_flush">
|
||||
<obj_property name="ElementShortName">delayed_flush</obj_property>
|
||||
<obj_property name="ObjectShortName">delayed_flush</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/fetch_block/exception">
|
||||
<obj_property name="ElementShortName">exception</obj_property>
|
||||
<obj_property name="ObjectShortName">exception</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/fetch_block/mem_valid">
|
||||
<obj_property name="ElementShortName">mem_valid</obj_property>
|
||||
<obj_property name="ObjectShortName">mem_valid</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/fetch_block/stage2_valid">
|
||||
<obj_property name="ElementShortName">stage2_valid</obj_property>
|
||||
<obj_property name="ObjectShortName">stage2_valid</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/bt/use_prediction">
|
||||
<obj_property name="ElementShortName">use_prediction</obj_property>
|
||||
<obj_property name="ObjectShortName">use_prediction</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/ib/full">
|
||||
<obj_property name="ElementShortName">full</obj_property>
|
||||
<obj_property name="ObjectShortName">full</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/ib/early_full">
|
||||
<obj_property name="ElementShortName">early_full</obj_property>
|
||||
<obj_property name="ObjectShortName">early_full</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/ib/data_in">
|
||||
<obj_property name="ElementShortName">data_in</obj_property>
|
||||
<obj_property name="ObjectShortName">data_in</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="divider7368" type="divider">
|
||||
<obj_property name="label">I Cache</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/fetch_block/\fetch_sub[1] /stage1_addr">
|
||||
<obj_property name="ElementShortName">stage1_addr[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">stage1_addr[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/fetch_block/\fetch_sub[1] /stage2_addr">
|
||||
<obj_property name="ElementShortName">stage2_addr[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">stage2_addr[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/fetch_block/\fetch_sub[1] /data_out">
|
||||
<obj_property name="ElementShortName">data_out[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">data_out[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/fetch_block/\fetch_sub[1] /data_valid">
|
||||
<obj_property name="ElementShortName">data_valid</obj_property>
|
||||
<obj_property name="ObjectShortName">data_valid</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/fetch_block/new_issue">
|
||||
<obj_property name="ElementShortName">new_issue</obj_property>
|
||||
<obj_property name="ObjectShortName">new_issue</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/fetch_block/\fetch_sub[1] /ready">
|
||||
<obj_property name="ElementShortName">ready</obj_property>
|
||||
<obj_property name="ObjectShortName">ready</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/fetch_block/\fetch_sub[1] /new_request">
|
||||
<obj_property name="ElementShortName">new_request</obj_property>
|
||||
<obj_property name="ObjectShortName">new_request</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/fetch_block/l1_response/data_valid">
|
||||
<obj_property name="ElementShortName">data_valid</obj_property>
|
||||
<obj_property name="ObjectShortName">data_valid</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="divider254" type="divider">
|
||||
<obj_property name="label">Global Control</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/gc_unit_block/clk">
|
||||
<obj_property name="ElementShortName">clk</obj_property>
|
||||
<obj_property name="ObjectShortName">clk</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/gc_unit_block/rst">
|
||||
<obj_property name="ElementShortName">rst</obj_property>
|
||||
<obj_property name="ObjectShortName">rst</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/gc_unit_block/state">
|
||||
<obj_property name="ElementShortName">state[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">state[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/gc_unit_block/next_state">
|
||||
<obj_property name="ElementShortName">next_state[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">next_state[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/gc_unit_block/clear_shift_count">
|
||||
<obj_property name="ElementShortName">clear_shift_count[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">clear_shift_count[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/gc_unit_block/tlb_clear_shift_count">
|
||||
<obj_property name="ElementShortName">tlb_clear_shift_count[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">tlb_clear_shift_count[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/gc_unit_block/gc_issue_hold">
|
||||
<obj_property name="ElementShortName">gc_issue_hold</obj_property>
|
||||
<obj_property name="ObjectShortName">gc_issue_hold</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/gc_unit_block/gc_issue_flush">
|
||||
<obj_property name="ElementShortName">gc_issue_flush</obj_property>
|
||||
<obj_property name="ObjectShortName">gc_issue_flush</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/gc_unit_block/gc_fetch_hold">
|
||||
<obj_property name="ElementShortName">gc_fetch_hold</obj_property>
|
||||
<obj_property name="ObjectShortName">gc_fetch_hold</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/gc_unit_block/gc_fetch_flush">
|
||||
<obj_property name="ElementShortName">gc_fetch_flush</obj_property>
|
||||
<obj_property name="ObjectShortName">gc_fetch_flush</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/gc_unit_block/inuse_clear">
|
||||
<obj_property name="ElementShortName">inuse_clear</obj_property>
|
||||
<obj_property name="ObjectShortName">inuse_clear</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="divider7359" type="divider">
|
||||
<obj_property name="label">Decode/Issue</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/clk">
|
||||
<obj_property name="ElementShortName">clk</obj_property>
|
||||
<obj_property name="ObjectShortName">clk</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/dec_pc">
|
||||
<obj_property name="ElementShortName">dec_pc[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">dec_pc[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/ddr_interface/dec_inst_text">
|
||||
<obj_property name="ElementShortName">dec_inst_text[0:511]</obj_property>
|
||||
<obj_property name="ObjectShortName">dec_inst_text[0:511]</obj_property>
|
||||
<obj_property name="Radix">ASCIIRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/decode_block/ib/data_out.instruction">
|
||||
<obj_property name="ElementShortName">.instruction[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">.instruction[31:0]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/instruction_complete">
|
||||
<obj_property name="ElementShortName">instruction_complete</obj_property>
|
||||
<obj_property name="ObjectShortName">instruction_complete</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/decode_block/issue_valid">
|
||||
<obj_property name="ElementShortName">issue_valid</obj_property>
|
||||
<obj_property name="ObjectShortName">issue_valid</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/decode_block/operands_ready">
|
||||
<obj_property name="ElementShortName">operands_ready</obj_property>
|
||||
<obj_property name="ObjectShortName">operands_ready</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/decode_block/advance">
|
||||
<obj_property name="ElementShortName">advance</obj_property>
|
||||
<obj_property name="ObjectShortName">advance</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/decode_block/new_request">
|
||||
<obj_property name="ElementShortName">new_request[6:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">new_request[6:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/decode_block/issue_ready">
|
||||
<obj_property name="ElementShortName">issue_ready[6:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">issue_ready[6:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/decode_block/issue">
|
||||
<obj_property name="ElementShortName">issue[6:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">issue[6:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/write_back_mux/inorder">
|
||||
<obj_property name="ElementShortName">inorder</obj_property>
|
||||
<obj_property name="ObjectShortName">inorder</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/bt/flush">
|
||||
<obj_property name="ElementShortName">flush</obj_property>
|
||||
<obj_property name="ObjectShortName">flush</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/register_file_block/rs1_feedforward">
|
||||
<obj_property name="ElementShortName">rs1_feedforward</obj_property>
|
||||
<obj_property name="ObjectShortName">rs1_feedforward</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/register_file_block/rs2_feedforward">
|
||||
<obj_property name="ElementShortName">rs2_feedforward</obj_property>
|
||||
<obj_property name="ObjectShortName">rs2_feedforward</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/decode_block/uses_rs1">
|
||||
<obj_property name="ElementShortName">uses_rs1</obj_property>
|
||||
<obj_property name="ObjectShortName">uses_rs1</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/decode_block/uses_rs2">
|
||||
<obj_property name="ElementShortName">uses_rs2</obj_property>
|
||||
<obj_property name="ObjectShortName">uses_rs2</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/decode_block/uses_rd">
|
||||
<obj_property name="ElementShortName">uses_rd</obj_property>
|
||||
<obj_property name="ObjectShortName">uses_rd</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/decode_block/future_rd_addr">
|
||||
<obj_property name="ElementShortName">future_rd_addr[4:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">future_rd_addr[4:0]</obj_property>
|
||||
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/bt_block/miss_predict_br">
|
||||
<obj_property name="ElementShortName">miss_predict_br[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">miss_predict_br[31:0]</obj_property>
|
||||
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/bt_block/miss_predict_ret">
|
||||
<obj_property name="ElementShortName">miss_predict_ret[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">miss_predict_ret[31:0]</obj_property>
|
||||
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="divider3002" type="divider">
|
||||
<obj_property name="label">Register File</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/register_file_block/sim_register">
|
||||
<obj_property name="ElementShortName">sim_register</obj_property>
|
||||
<obj_property name="ObjectShortName">sim_register</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/rf_wb/valid_write">
|
||||
<obj_property name="ElementShortName">valid_write</obj_property>
|
||||
<obj_property name="ObjectShortName">valid_write</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/rf_wb/rd_addr">
|
||||
<obj_property name="ElementShortName">rd_addr[4:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">rd_addr[4:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/register_file_block/inorder">
|
||||
<obj_property name="ElementShortName">inorder</obj_property>
|
||||
<obj_property name="ObjectShortName">inorder</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/register_file_block/inuse_mem/clr">
|
||||
<obj_property name="ElementShortName">clr</obj_property>
|
||||
<obj_property name="ObjectShortName">clr</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/register_file_block/inuse_mem/bankA">
|
||||
<obj_property name="ElementShortName">bankA[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">bankA[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/register_file_block/inuse_mem/bankB">
|
||||
<obj_property name="ElementShortName">bankB[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">bankB[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/register_file_block/inuse_mem/w_clear">
|
||||
<obj_property name="ElementShortName">w_clear[4:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">w_clear[4:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/register_file_block/inuse_mem/rs1_inuse">
|
||||
<obj_property name="ElementShortName">rs1_inuse</obj_property>
|
||||
<obj_property name="ObjectShortName">rs1_inuse</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/register_file_block/inuse_mem/rs2_inuse">
|
||||
<obj_property name="ElementShortName">rs2_inuse</obj_property>
|
||||
<obj_property name="ObjectShortName">rs2_inuse</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/register_file_block/inuse_mem/sim_inuse">
|
||||
<obj_property name="ElementShortName">sim_inuse[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">sim_inuse[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/register_file_block/in_use_match">
|
||||
<obj_property name="ElementShortName">in_use_match</obj_property>
|
||||
<obj_property name="ObjectShortName">in_use_match</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/register_file_block/in_use_by">
|
||||
<obj_property name="ElementShortName">in_use_by[0:31][1:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">in_use_by[0:31][1:0]</obj_property>
|
||||
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="divider3001" type="divider">
|
||||
<obj_property name="label">WB & Inst queue</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/inst_queue/iq/new_issue">
|
||||
<obj_property name="ElementShortName">new_issue</obj_property>
|
||||
<obj_property name="ObjectShortName">new_issue</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/iq/data_in">
|
||||
<obj_property name="ElementShortName">data_in</obj_property>
|
||||
<obj_property name="ObjectShortName">data_in</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/inst_queue/iq/wb/valid">
|
||||
<obj_property name="ElementShortName">valid[3:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">valid[3:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/iq/data_out">
|
||||
<obj_property name="ElementShortName">data_out[3:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">data_out[3:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/write_back_mux/iq/pop">
|
||||
<obj_property name="ElementShortName">pop[3:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">pop[3:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/write_back_mux/unit_id">
|
||||
<obj_property name="ElementShortName">unit_id[2:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">unit_id[2:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/write_back_mux/rd_addr">
|
||||
<obj_property name="ElementShortName">rd_addr[4:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">rd_addr[4:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/write_back_mux/rd_addr_not_zero">
|
||||
<obj_property name="ElementShortName">rd_addr_not_zero</obj_property>
|
||||
<obj_property name="ObjectShortName">rd_addr_not_zero</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/write_back_mux/issue_id">
|
||||
<obj_property name="ElementShortName">issue_id[1:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">issue_id[1:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/write_back_mux/entry_found">
|
||||
<obj_property name="ElementShortName">entry_found</obj_property>
|
||||
<obj_property name="ObjectShortName">entry_found</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/write_back_mux/iq_index">
|
||||
<obj_property name="ElementShortName">iq_index[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">iq_index[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/write_back_mux/done_on_first_cycle">
|
||||
<obj_property name="ElementShortName">done_on_first_cycle[5:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">done_on_first_cycle[5:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/write_back_mux/done_next_cycle">
|
||||
<obj_property name="ElementShortName">done_next_cycle[5:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">done_next_cycle[5:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/write_back_mux/iq/wb_accepting_input">
|
||||
<obj_property name="ElementShortName">wb_accepting_input</obj_property>
|
||||
<obj_property name="ObjectShortName">wb_accepting_input</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/write_back_mux/selected_unit_done_next_cycle">
|
||||
<obj_property name="ElementShortName">selected_unit_done_next_cycle</obj_property>
|
||||
<obj_property name="ObjectShortName">selected_unit_done_next_cycle</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/write_back_mux/accepted">
|
||||
<obj_property name="ElementShortName">accepted[5:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">accepted[5:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="divider3000" type="divider">
|
||||
<obj_property name="label">LS Unit</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/clk">
|
||||
<obj_property name="ElementShortName">clk</obj_property>
|
||||
<obj_property name="ObjectShortName">clk</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/load_store_unit_block/ls_inputs">
|
||||
<obj_property name="ElementShortName">ls_inputs</obj_property>
|
||||
<obj_property name="ObjectShortName">ls_inputs</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/load_store_unit_block/last_unit">
|
||||
<obj_property name="ElementShortName">last_unit[2:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">last_unit[2:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/load_store_unit_block/current_unit">
|
||||
<obj_property name="ElementShortName">current_unit[2:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">current_unit[2:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/load_store_unit_block/unit_stall">
|
||||
<obj_property name="ElementShortName">unit_stall</obj_property>
|
||||
<obj_property name="ObjectShortName">unit_stall</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/load_store_unit_block/issue_request">
|
||||
<obj_property name="ElementShortName">issue_request</obj_property>
|
||||
<obj_property name="ObjectShortName">issue_request</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/load_store_unit_block/inflight_count">
|
||||
<obj_property name="ElementShortName">inflight_count[1:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">inflight_count[1:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/load_store_unit_block/ls_input_fifo/read_index">
|
||||
<obj_property name="ElementShortName">read_index[1:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">read_index[1:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/load_store_unit_block/stage1">
|
||||
<obj_property name="ElementShortName">stage1</obj_property>
|
||||
<obj_property name="ObjectShortName">stage1</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/load_store_unit_block/d_inputs">
|
||||
<obj_property name="ElementShortName">d_inputs</obj_property>
|
||||
<obj_property name="ObjectShortName">d_inputs</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/load_store_unit_block/sub_unit_address_match">
|
||||
<obj_property name="ElementShortName">sub_unit_address_match[2:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">sub_unit_address_match[2:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/load_store_unit_block/unit_ready">
|
||||
<obj_property name="ElementShortName">unit_ready[2:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">unit_ready[2:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/load_store_unit_block/unit_data_valid">
|
||||
<obj_property name="ElementShortName">unit_data_valid[2:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">unit_data_valid[2:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFD700</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/load_store_unit_block/\genblk6.d_bram /data_bram/en">
|
||||
<obj_property name="ElementShortName">en</obj_property>
|
||||
<obj_property name="ObjectShortName">en</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/load_store_unit_block/load_complete">
|
||||
<obj_property name="ElementShortName">load_complete</obj_property>
|
||||
<obj_property name="ObjectShortName">load_complete</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/load_store_unit_block/unit_data_valid">
|
||||
<obj_property name="ElementShortName">unit_data_valid[2:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">unit_data_valid[2:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/load_store_unit_block/unit_data_array">
|
||||
<obj_property name="ElementShortName">unit_data_array[2:0][31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">unit_data_array[2:0][31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/load_store_unit_block/final_load_data">
|
||||
<obj_property name="ElementShortName">final_load_data[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">final_load_data[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="divider2999" type="divider">
|
||||
<obj_property name="label">DCache</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/clk">
|
||||
<obj_property name="ElementShortName">clk</obj_property>
|
||||
<obj_property name="ObjectShortName">clk</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/load_store_unit_block/\genblk8.data_cache /ls/data_valid">
|
||||
<obj_property name="ElementShortName">data_valid</obj_property>
|
||||
<obj_property name="ObjectShortName">data_valid</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/load_store_unit_block/\genblk8.data_cache /ls/ready">
|
||||
<obj_property name="ElementShortName">ready</obj_property>
|
||||
<obj_property name="ObjectShortName">ready</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/load_store_unit_block/\genblk8.data_cache /ls/new_request">
|
||||
<obj_property name="ElementShortName">new_request</obj_property>
|
||||
<obj_property name="ObjectShortName">new_request</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/load_store_unit_block/wb_fifo/full">
|
||||
<obj_property name="ElementShortName">full</obj_property>
|
||||
<obj_property name="ObjectShortName">full</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/load_store_unit_block/\genblk8.data_cache /second_cycle">
|
||||
<obj_property name="ElementShortName">second_cycle</obj_property>
|
||||
<obj_property name="ObjectShortName">second_cycle</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/load_store_unit_block/\genblk8.data_cache /request">
|
||||
<obj_property name="ElementShortName">request</obj_property>
|
||||
<obj_property name="ObjectShortName">request</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/load_store_unit_block/\genblk8.data_cache /tag_hit">
|
||||
<obj_property name="ElementShortName">tag_hit</obj_property>
|
||||
<obj_property name="ObjectShortName">tag_hit</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/load_store_unit_block/\genblk8.data_cache /line_complete">
|
||||
<obj_property name="ElementShortName">line_complete</obj_property>
|
||||
<obj_property name="ObjectShortName">line_complete</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/load_store_unit_block/\genblk8.data_cache /read_miss_complete">
|
||||
<obj_property name="ElementShortName">read_miss_complete</obj_property>
|
||||
<obj_property name="ObjectShortName">read_miss_complete</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/load_store_unit_block/\genblk8.data_cache /store_complete">
|
||||
<obj_property name="ElementShortName">store_complete</obj_property>
|
||||
<obj_property name="ObjectShortName">store_complete</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/load_store_unit_block/\genblk8.data_cache /idle">
|
||||
<obj_property name="ElementShortName">idle</obj_property>
|
||||
<obj_property name="ObjectShortName">idle</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/load_store_unit_block/load_attributes/valid">
|
||||
<obj_property name="ElementShortName">valid</obj_property>
|
||||
<obj_property name="ObjectShortName">valid</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/load_store_unit_block/\genblk8.data_cache /replacement_policy/clk">
|
||||
<obj_property name="ElementShortName">clk</obj_property>
|
||||
<obj_property name="ObjectShortName">clk</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/load_store_unit_block/\genblk8.data_cache /replacement_policy/rst">
|
||||
<obj_property name="ElementShortName">rst</obj_property>
|
||||
<obj_property name="ObjectShortName">rst</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/load_store_unit_block/\genblk8.data_cache /replacement_policy/en">
|
||||
<obj_property name="ElementShortName">en</obj_property>
|
||||
<obj_property name="ObjectShortName">en</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/load_store_unit_block/\genblk8.data_cache /replacement_policy/one_hot">
|
||||
<obj_property name="ElementShortName">one_hot[1:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">one_hot[1:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/load_store_unit_block/\genblk8.data_cache /replacement_policy/C_WIDTH">
|
||||
<obj_property name="ElementShortName">C_WIDTH[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">C_WIDTH[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/load_store_unit_block/\genblk8.data_cache /update_way_conv/one_hot">
|
||||
<obj_property name="ElementShortName">one_hot[1:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">one_hot[1:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/load_store_unit_block/\genblk8.data_cache /update_way_conv/int_out">
|
||||
<obj_property name="ElementShortName">int_out[0:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">int_out[0:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/load_store_unit_block/\genblk8.data_cache /update_way_conv/C_WIDTH">
|
||||
<obj_property name="ElementShortName">C_WIDTH[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">C_WIDTH[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="divider2998" type="divider">
|
||||
<obj_property name="label">L2</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/\genblk1.arb /requests">
|
||||
<obj_property name="ElementShortName">requests[3:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">requests[3:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/\genblk1.arb /acks">
|
||||
<obj_property name="ElementShortName">acks[3:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">acks[3:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/\genblk1.arb /push_ready">
|
||||
<obj_property name="ElementShortName">push_ready</obj_property>
|
||||
<obj_property name="ObjectShortName">push_ready</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/\genblk1.arb /request_exists">
|
||||
<obj_property name="ElementShortName">request_exists</obj_property>
|
||||
<obj_property name="ObjectShortName">request_exists</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/uut/\genblk1.arb /busy">
|
||||
<obj_property name="ElementShortName">busy</obj_property>
|
||||
<obj_property name="ObjectShortName">busy</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/uut/\genblk1.arb /l2_requests">
|
||||
<obj_property name="ElementShortName">l2_requests[3:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">l2_requests[3:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/l2_arb/\request[0] /request">
|
||||
<obj_property name="ElementShortName">request</obj_property>
|
||||
<obj_property name="ObjectShortName">request</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_arb/\request[0] /request_push">
|
||||
<obj_property name="ElementShortName">request_push</obj_property>
|
||||
<obj_property name="ObjectShortName">request_push</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/l2_arb/requests">
|
||||
<obj_property name="ElementShortName">requests[1:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">requests[1:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/l2_arb/arb/requests">
|
||||
<obj_property name="ElementShortName">requests[1:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">requests[1:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/l2_arb/arb/grantee_i">
|
||||
<obj_property name="ElementShortName">grantee_i[0:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">grantee_i[0:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/l2_arb/arb/grantee_v">
|
||||
<obj_property name="ElementShortName">grantee_v[1:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">grantee_v[1:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_arb/arb/grantee_valid">
|
||||
<obj_property name="ElementShortName">grantee_valid</obj_property>
|
||||
<obj_property name="ObjectShortName">grantee_valid</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_arb/arb/strobe">
|
||||
<obj_property name="ElementShortName">strobe</obj_property>
|
||||
<obj_property name="ObjectShortName">strobe</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_arb/\input_fifos[0] /pop">
|
||||
<obj_property name="ElementShortName">pop</obj_property>
|
||||
<obj_property name="ObjectShortName">pop</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_arb/\request[0] /request_full">
|
||||
<obj_property name="ElementShortName">request_full</obj_property>
|
||||
<obj_property name="ObjectShortName">request_full</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_arb/advance">
|
||||
<obj_property name="ElementShortName">advance</obj_property>
|
||||
<obj_property name="ObjectShortName">advance</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/l2_arb/\request[0] /inv_addr">
|
||||
<obj_property name="ElementShortName">inv_addr[31:2]</obj_property>
|
||||
<obj_property name="ObjectShortName">inv_addr[31:2]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_arb/\request[0] /inv_valid">
|
||||
<obj_property name="ElementShortName">inv_valid</obj_property>
|
||||
<obj_property name="ObjectShortName">inv_valid</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_arb/\request[0] /inv_ack">
|
||||
<obj_property name="ElementShortName">inv_ack</obj_property>
|
||||
<obj_property name="ObjectShortName">inv_ack</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_arb/\request[0] /con_result">
|
||||
<obj_property name="ElementShortName">con_result</obj_property>
|
||||
<obj_property name="ObjectShortName">con_result</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_arb/\request[0] /con_valid">
|
||||
<obj_property name="ElementShortName">con_valid</obj_property>
|
||||
<obj_property name="ObjectShortName">con_valid</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/l2_arb/\request[0] /wr_data">
|
||||
<obj_property name="ElementShortName">wr_data[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">wr_data[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_arb/\request[0] /wr_data_push">
|
||||
<obj_property name="ElementShortName">wr_data_push</obj_property>
|
||||
<obj_property name="ObjectShortName">wr_data_push</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_arb/\request[0] /data_full">
|
||||
<obj_property name="ElementShortName">data_full</obj_property>
|
||||
<obj_property name="ObjectShortName">data_full</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/l2_arb/\request[0] /rd_data">
|
||||
<obj_property name="ElementShortName">rd_data[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">rd_data[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/l2_arb/\request[0] /rd_sub_id">
|
||||
<obj_property name="ElementShortName">rd_sub_id[1:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">rd_sub_id[1:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_arb/\request[0] /rd_data_valid">
|
||||
<obj_property name="ElementShortName">rd_data_valid</obj_property>
|
||||
<obj_property name="ObjectShortName">rd_data_valid</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_arb/\request[0] /rd_data_ack">
|
||||
<obj_property name="ElementShortName">rd_data_ack</obj_property>
|
||||
<obj_property name="ObjectShortName">rd_data_ack</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/l2_arb/mem/request">
|
||||
<obj_property name="ElementShortName">request</obj_property>
|
||||
<obj_property name="ObjectShortName">request</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_arb/mem/request_pop">
|
||||
<obj_property name="ElementShortName">request_pop</obj_property>
|
||||
<obj_property name="ObjectShortName">request_pop</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_arb/mem/request_valid">
|
||||
<obj_property name="ElementShortName">request_valid</obj_property>
|
||||
<obj_property name="ObjectShortName">request_valid</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_arb/mem/abort_request">
|
||||
<obj_property name="ElementShortName">abort_request</obj_property>
|
||||
<obj_property name="ObjectShortName">abort_request</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/l2_arb/mem/wr_data">
|
||||
<obj_property name="ElementShortName">wr_data[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">wr_data[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_arb/mem/wr_data_valid">
|
||||
<obj_property name="ElementShortName">wr_data_valid</obj_property>
|
||||
<obj_property name="ObjectShortName">wr_data_valid</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_arb/mem/wr_data_read">
|
||||
<obj_property name="ElementShortName">wr_data_read</obj_property>
|
||||
<obj_property name="ObjectShortName">wr_data_read</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/l2_arb/mem/rd_data">
|
||||
<obj_property name="ElementShortName">rd_data[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">rd_data[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/l2_arb/mem/rd_id">
|
||||
<obj_property name="ElementShortName">rd_id[2:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">rd_id[2:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_arb/mem/rd_data_valid">
|
||||
<obj_property name="ElementShortName">rd_data_valid</obj_property>
|
||||
<obj_property name="ObjectShortName">rd_data_valid</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_arb/reserv_valid">
|
||||
<obj_property name="ElementShortName">reserv_valid</obj_property>
|
||||
<obj_property name="ObjectShortName">reserv_valid</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/l2_arb/reserv_request">
|
||||
<obj_property name="ElementShortName">reserv_request</obj_property>
|
||||
<obj_property name="ObjectShortName">reserv_request</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/l2_arb/reserv_id">
|
||||
<obj_property name="ElementShortName">reserv_id[0:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">reserv_id[0:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/l2_arb/reserv_id_v">
|
||||
<obj_property name="ElementShortName">reserv_id_v[1:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">reserv_id_v[1:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/l2_arb/new_attr">
|
||||
<obj_property name="ElementShortName">new_attr</obj_property>
|
||||
<obj_property name="ObjectShortName">new_attr</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/l2_arb/data_attributes_fifo/\genblk1.genblk1.lut_ram ">
|
||||
<obj_property name="ElementShortName">\genblk1.genblk1.lut_ram [15:0][6:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">\genblk1.genblk1.lut_ram [15:0][6:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/l2_arb/data_attributes_fifo/\genblk1.genblk1.read_index ">
|
||||
<obj_property name="ElementShortName">\genblk1.genblk1.read_index [3:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">\genblk1.genblk1.read_index [3:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/l2_arb/data_attributes_fifo/\genblk1.genblk1.write_index ">
|
||||
<obj_property name="ElementShortName">\genblk1.genblk1.write_index [3:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">\genblk1.genblk1.write_index [3:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/l2_arb/current_attr">
|
||||
<obj_property name="ElementShortName">current_attr</obj_property>
|
||||
<obj_property name="ObjectShortName">current_attr</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_arb/data_attributes/valid">
|
||||
<obj_property name="ElementShortName">valid</obj_property>
|
||||
<obj_property name="ObjectShortName">valid</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_arb/data_attributes/push">
|
||||
<obj_property name="ElementShortName">push</obj_property>
|
||||
<obj_property name="ObjectShortName">push</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_arb/data_attributes/pop">
|
||||
<obj_property name="ElementShortName">pop</obj_property>
|
||||
<obj_property name="ObjectShortName">pop</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="divider2818" type="divider">
|
||||
<obj_property name="label">Mem AXI</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/clk">
|
||||
<obj_property name="ElementShortName">clk</obj_property>
|
||||
<obj_property name="ObjectShortName">clk</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/l2_to_mem/axi_araddr">
|
||||
<obj_property name="ElementShortName">axi_araddr[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">axi_araddr[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_to_mem/axi_arready">
|
||||
<obj_property name="ElementShortName">axi_arready</obj_property>
|
||||
<obj_property name="ObjectShortName">axi_arready</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_to_mem/axi_arvalid">
|
||||
<obj_property name="ElementShortName">axi_arvalid</obj_property>
|
||||
<obj_property name="ObjectShortName">axi_arvalid</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_to_mem/axi_rready">
|
||||
<obj_property name="ElementShortName">axi_rready</obj_property>
|
||||
<obj_property name="ObjectShortName">axi_rready</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_to_mem/axi_rvalid">
|
||||
<obj_property name="ElementShortName">axi_rvalid</obj_property>
|
||||
<obj_property name="ObjectShortName">axi_rvalid</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/l2_to_mem/axi_awburst">
|
||||
<obj_property name="ElementShortName">axi_awburst[1:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">axi_awburst[1:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/l2_to_mem/axi_rdata">
|
||||
<obj_property name="ElementShortName">axi_rdata[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">axi_rdata[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/l2_to_mem/axi_awaddr">
|
||||
<obj_property name="ElementShortName">axi_awaddr[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">axi_awaddr[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_to_mem/axi_awready">
|
||||
<obj_property name="ElementShortName">axi_awready</obj_property>
|
||||
<obj_property name="ObjectShortName">axi_awready</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_to_mem/axi_awvalid">
|
||||
<obj_property name="ElementShortName">axi_awvalid</obj_property>
|
||||
<obj_property name="ObjectShortName">axi_awvalid</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_to_mem/axi_wready">
|
||||
<obj_property name="ElementShortName">axi_wready</obj_property>
|
||||
<obj_property name="ObjectShortName">axi_wready</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_to_mem/axi_wvalid">
|
||||
<obj_property name="ElementShortName">axi_wvalid</obj_property>
|
||||
<obj_property name="ObjectShortName">axi_wvalid</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_to_mem/axi_wlast">
|
||||
<obj_property name="ElementShortName">axi_wlast</obj_property>
|
||||
<obj_property name="ObjectShortName">axi_wlast</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/l2_to_mem/axi_wdata">
|
||||
<obj_property name="ElementShortName">axi_wdata[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">axi_wdata[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/l2_to_mem/axi_wstrb">
|
||||
<obj_property name="ElementShortName">axi_wstrb[3:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">axi_wstrb[3:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_to_mem/write_in_progress">
|
||||
<obj_property name="ElementShortName">write_in_progress</obj_property>
|
||||
<obj_property name="ObjectShortName">write_in_progress</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/cva5_tb/l2_to_mem/write_transfer_complete">
|
||||
<obj_property name="ElementShortName">write_transfer_complete</obj_property>
|
||||
<obj_property name="ObjectShortName">write_transfer_complete</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/ddr_interface/write_request_count">
|
||||
<obj_property name="ElementShortName">write_request_count[47:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">write_request_count[47:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/cva5_tb/ddr_interface/read_request_count">
|
||||
<obj_property name="ElementShortName">read_request_count[47:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">read_request_count[47:0]</obj_property>
|
||||
</wvobject>
|
||||
</wave_config>
|
||||
|
|
@ -1,345 +0,0 @@
|
|||
/*
|
||||
* Copyright © 2017 Eric Matthews, Lesley Shannon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* Initial code developed under the supervision of Dr. Lesley Shannon,
|
||||
* Reconfigurable Computing Lab, Simon Fraser University.
|
||||
*
|
||||
* Author(s):
|
||||
* Alec Lu <fla30@sfu.ca>
|
||||
* Eric Matthews <ematthew@sfu.ca>
|
||||
*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
import cva5_config::*;
|
||||
import cva5_types::*;
|
||||
|
||||
typedef struct packed{
|
||||
alu_inputs_t module_input;
|
||||
logic [31: 0] expected_result;
|
||||
} alu_result_t;
|
||||
|
||||
module alu_unit_tb();
|
||||
//DUT Regs and Wires
|
||||
logic clk;
|
||||
logic rst;
|
||||
func_unit_ex_interface alu_ex();
|
||||
unit_writeback_interface alu_wb();
|
||||
alu_inputs_t alu_inputs;
|
||||
|
||||
//Internal Regs and Wires
|
||||
integer test_number;
|
||||
|
||||
//Input
|
||||
logic [31: 0] in1_rand;//contains sign padding bit for slt operation
|
||||
logic [31: 0] in2_rand;//contains sign padding bit for slt operation
|
||||
logic subtract_rand;
|
||||
logic arith_rand;//contains sign padding bit for arithmetic shift right operation
|
||||
logic lshift_rand;
|
||||
logic [ 2: 0] fn3_rand;
|
||||
logic [ 1: 0] op_rand;
|
||||
logic [31: 0] result_rand;
|
||||
logic [32: 0] result_rshift;
|
||||
logic [32: 0] result_slt;
|
||||
|
||||
//Result
|
||||
// logic [31: 0] result_queue[$];
|
||||
// logic [31: 0] temp_result;
|
||||
alu_result_t result_queue[$];
|
||||
alu_result_t temp_result;
|
||||
logic [31: 0] alu_wb_rd_d;
|
||||
|
||||
//Latency
|
||||
parameter MAX_RESPONSE_LATENCY = 32'hF;
|
||||
logic wb_done;
|
||||
logic firstPop;
|
||||
logic [31: 0] latency_queue[$];
|
||||
logic [31: 0] wb_done_acc;
|
||||
logic [31: 0] response_latency;
|
||||
|
||||
//DUT
|
||||
alu_unit uut (.*);
|
||||
|
||||
//Reset
|
||||
task reset;
|
||||
begin
|
||||
rst = 1'b1;
|
||||
#100 rst = 1'b0;
|
||||
end
|
||||
endtask
|
||||
|
||||
//Clock Gen
|
||||
always
|
||||
#1 clk = ~clk;
|
||||
|
||||
//Latency Logic
|
||||
function int genRandLatency();
|
||||
genRandLatency = $random & MAX_RESPONSE_LATENCY;
|
||||
endfunction
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst) begin
|
||||
wb_done_acc <= 32'h1;
|
||||
firstPop <= 1'b1;
|
||||
response_latency <= 32'hFFFFFFFF;
|
||||
end else begin
|
||||
if (alu_wb.done_next_cycle) begin
|
||||
wb_done_acc <= wb_done_acc + 1;
|
||||
end else begin
|
||||
wb_done_acc <= 32'h1;
|
||||
end
|
||||
|
||||
if (firstPop | alu_wb.accepted) begin
|
||||
response_latency <= latency_queue.pop_front();
|
||||
firstPop <= 1'b0;
|
||||
end else begin
|
||||
response_latency <= response_latency;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign wb_done = alu_wb.done_next_cycle & (wb_done_acc >= response_latency);
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst)
|
||||
alu_wb.accepted <= 0;
|
||||
else
|
||||
alu_wb.accepted <= wb_done;
|
||||
end
|
||||
|
||||
//Output checker
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst) begin
|
||||
alu_wb_rd_d <= 32'h0;
|
||||
end else begin
|
||||
alu_wb_rd_d <= alu_wb.rd;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst)
|
||||
test_number <= 1;
|
||||
if (alu_wb.accepted) begin
|
||||
test_number <= test_number + 1;
|
||||
temp_result = result_queue.pop_front();
|
||||
if (temp_result.expected_result != 32'hxxxxxxxx) begin
|
||||
assert (alu_wb_rd_d == temp_result.expected_result)
|
||||
else $error("Incorrect result on test number %d. (%h, should be: %h)\n\t Input: in1: %d, in2: %d, subtract: %b, arith: %b, lshift: %b, shifter_in: %d, logic_op: %b, op: %b",
|
||||
test_number, alu_wb_rd_d, temp_result.expected_result,
|
||||
temp_result.module_input.in1, temp_result.module_input.in2,
|
||||
temp_result.module_input.subtract, temp_result.module_input.arith,
|
||||
temp_result.module_input.lshift, temp_result.module_input.shifter_in,
|
||||
temp_result.module_input.logic_op, temp_result.module_input.op);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
//Driver
|
||||
task test_alu (
|
||||
input logic [XLEN:0] in1,
|
||||
input logic [XLEN:0] in2,
|
||||
input logic subtract,
|
||||
input logic arith,
|
||||
input logic lshift,
|
||||
input logic [ 2: 0] fn3,
|
||||
input logic [ 1: 0] op,
|
||||
input logic [31: 0] latency,
|
||||
input logic [XLEN-1:0] result
|
||||
);
|
||||
wait (~clk & alu_ex.ready);
|
||||
alu_inputs.in1 = in1;
|
||||
alu_inputs.in2 = in2;
|
||||
alu_inputs.subtract = subtract;
|
||||
alu_inputs.arith = arith;
|
||||
alu_inputs.lshift = lshift;
|
||||
alu_inputs.shifter_in <= lshift ? {<<{in1}} : in1;
|
||||
|
||||
case (fn3)
|
||||
SLT_fn3 : alu_inputs.logic_op = ALU_LOGIC_ADD;
|
||||
SLTU_fn3 : alu_inputs.logic_op = ALU_LOGIC_ADD;
|
||||
SLL_fn3 : alu_inputs.logic_op = ALU_LOGIC_ADD;
|
||||
XOR_fn3 : alu_inputs.logic_op = ALU_LOGIC_XOR;
|
||||
OR_fn3 : alu_inputs.logic_op = ALU_LOGIC_OR;
|
||||
AND_fn3 : alu_inputs.logic_op = ALU_LOGIC_AND;
|
||||
SRA_fn3 : alu_inputs.logic_op = ALU_LOGIC_ADD;
|
||||
ADD_SUB_fn3 : alu_inputs.logic_op = ALU_LOGIC_ADD;
|
||||
endcase
|
||||
|
||||
alu_inputs.op = op;
|
||||
result_queue.push_back({alu_inputs, result});
|
||||
latency_queue.push_back(latency);
|
||||
alu_ex.new_request_dec = 1; #2
|
||||
alu_ex.new_request_dec = 0;
|
||||
endtask
|
||||
|
||||
//Generator + Transaction
|
||||
task test_gen();
|
||||
//TODO: move all randomizing parameters out here
|
||||
op_rand = $urandom % 4;
|
||||
in1_rand = $random;
|
||||
in2_rand = $random;
|
||||
subtract_rand = $urandom % 2;
|
||||
fn3_rand = $urandom % 8;
|
||||
lshift_rand = $urandom % 2;
|
||||
arith_rand = $urandom % 2;
|
||||
|
||||
//SW model
|
||||
case (op_rand)
|
||||
ALU_ADD_SUB: begin
|
||||
case (fn3_rand)
|
||||
XOR_fn3 : begin result_rand = in1_rand ^ in2_rand; subtract_rand = 0; end
|
||||
OR_fn3 : begin result_rand = in1_rand | in2_rand; subtract_rand = 0; end
|
||||
AND_fn3 : begin result_rand = in1_rand & in2_rand; subtract_rand = 0; end
|
||||
default : result_rand = subtract_rand ? in1_rand - in2_rand : in1_rand + in2_rand;
|
||||
endcase
|
||||
end
|
||||
ALU_SLT: begin
|
||||
subtract_rand = 1;
|
||||
fn3_rand = 0;
|
||||
result_slt = {1'b0, in1_rand} - {1'b0, in2_rand};
|
||||
result_rand = {31'b0, result_slt[32]};
|
||||
end
|
||||
default: begin //ALU_SHIFT
|
||||
if (lshift_rand) begin
|
||||
arith_rand = 0;
|
||||
result_rand = in1_rand << in2_rand[4:0];
|
||||
end else begin
|
||||
result_rshift = signed'({arith_rand,in1_rand}) >>> in2_rand[4:0];
|
||||
result_rand = result_rshift[31:0];
|
||||
end
|
||||
end
|
||||
endcase
|
||||
|
||||
test_alu({1'b0, in1_rand}, {1'b0, in2_rand}, subtract_rand, arith_rand, lshift_rand, fn3_rand, op_rand, genRandLatency(), result_rand);
|
||||
endtask
|
||||
|
||||
initial
|
||||
begin
|
||||
clk = 0;
|
||||
rst = 1;
|
||||
alu_inputs.in1 = 0;
|
||||
alu_inputs.in2 = 0;
|
||||
alu_inputs.subtract = 0;
|
||||
alu_inputs.arith = 0;
|
||||
alu_inputs.lshift = 0;
|
||||
alu_inputs.logic_op = 0;
|
||||
alu_inputs.op = 0;
|
||||
alu_ex.new_request_dec = 0;
|
||||
alu_wb.accepted = 0;
|
||||
|
||||
reset();
|
||||
|
||||
for (int i=0; i < 6; i = i+5)
|
||||
begin
|
||||
//ALU_ADD_SUB = 2'b00,
|
||||
// Add
|
||||
test_alu(33'h00000000, 33'h00000000, 1'b0, 1'b0, 1'b0, 3'b000, 2'b00, i, 32'h00000000);
|
||||
test_alu(33'h00000001, 33'h00000001, 1'b0, 1'b0, 1'b0, 3'b000, 2'b00, i, 32'h00000002);
|
||||
test_alu(33'h00000003, 33'h00000007, 1'b0, 1'b0, 1'b0, 3'b000, 2'b00, i, 32'h0000000a);
|
||||
// Sub
|
||||
test_alu(33'h00000000, 33'h00000000, 1'b1, 1'b0, 1'b0, 3'b000, 2'b00, i, 32'h00000000);
|
||||
test_alu(33'h00000001, 33'h00000001, 1'b1, 1'b0, 1'b0, 3'b000, 2'b00, i, 32'h00000000);
|
||||
test_alu(33'h00000003, 33'h00000007, 1'b1, 1'b0, 1'b0, 3'b000, 2'b00, i, 32'hfffffffc);
|
||||
|
||||
//ALU_LOGIC = 2'b01
|
||||
// AND
|
||||
test_alu(33'hff00ff00, 33'h0f0f0f0f, 1'b0, 1'b0, 1'b0, 3'b111, 2'b00, i, 32'h0f000f00);
|
||||
test_alu(33'h0ff00ff0, 33'hf0f0f0f0, 1'b0, 1'b0, 1'b0, 3'b111, 2'b00, i, 32'h00f000f0);
|
||||
test_alu(33'h00ff00ff, 33'h0f0f0f0f, 1'b0, 1'b0, 1'b0, 3'b111, 2'b00, i, 32'h000f000f);
|
||||
test_alu(33'hf00ff00f, 33'hf0f0f0f0, 1'b0, 1'b0, 1'b0, 3'b111, 2'b00, i, 32'hf000f000);
|
||||
// OR
|
||||
test_alu(33'hff00ff00, 33'h0f0f0f0f, 1'b0, 1'b0, 1'b0, 3'b110, 2'b00, i, 32'hff0fff0f);
|
||||
test_alu(33'h0ff00ff0, 33'hf0f0f0f0, 1'b0, 1'b0, 1'b0, 3'b110, 2'b00, i, 32'hfff0fff0);
|
||||
test_alu(33'h00ff00ff, 33'h0f0f0f0f, 1'b0, 1'b0, 1'b0, 3'b110, 2'b00, i, 32'h0fff0fff);
|
||||
test_alu(33'hf00ff00f, 33'hf0f0f0f0, 1'b0, 1'b0, 1'b0, 3'b110, 2'b00, i, 32'hf0fff0ff);
|
||||
// XOR
|
||||
test_alu(33'hff00ff00, 33'h0f0f0f0f, 1'b0, 1'b0, 1'b0, 3'b100, 2'b00, i, 32'hf00ff00f);
|
||||
test_alu(33'h0ff00ff0, 33'hf0f0f0f0, 1'b0, 1'b0, 1'b0, 3'b100, 2'b00, i, 32'hff00ff00);
|
||||
test_alu(33'h00ff00ff, 33'h0f0f0f0f, 1'b0, 1'b0, 1'b0, 3'b100, 2'b00, i, 32'h0ff00ff0);
|
||||
test_alu(33'hf00ff00f, 33'hf0f0f0f0, 1'b0, 1'b0, 1'b0, 3'b100, 2'b00, i, 32'h00ff00ff);
|
||||
|
||||
//ALU_SLT = 2'b10
|
||||
// Add
|
||||
test_alu(33'h00000000, 33'h00000000, 1'b0, 1'b0, 1'b0, 3'b000, 2'b01, i, 32'h0);
|
||||
test_alu(33'h00000001, 33'h00000001, 1'b0, 1'b0, 1'b0, 3'b000, 2'b01, i, 32'h0);
|
||||
test_alu(33'h00000003, 33'h00000007, 1'b0, 1'b0, 1'b0, 3'b000, 2'b01, i, 32'h0);
|
||||
// Sub
|
||||
test_alu(33'h00000000, 33'h00000000, 1'b1, 1'b0, 1'b0, 3'b000, 2'b01, i, 32'h0);
|
||||
test_alu(33'h00000001, 33'h00000001, 1'b1, 1'b0, 1'b0, 3'b000, 2'b01, i, 32'h0);
|
||||
test_alu(33'h00000003, 33'h00000007, 1'b1, 1'b0, 1'b0, 3'b000, 2'b01, i, 32'h1);
|
||||
|
||||
//ALU_SHIFT =2'b11
|
||||
// SLL
|
||||
test_alu(33'h00000001, 33'h00000000, 1'b0, 1'b0, 1'b1, 3'b000, 2'b10, i, 32'h00000001);
|
||||
test_alu(33'h00000001, 33'h00000001, 1'b0, 1'b0, 1'b1, 3'b000, 2'b10, i, 32'h00000002);
|
||||
test_alu(33'h00000001, 33'h00000007, 1'b0, 1'b0, 1'b1, 3'b000, 2'b10, i, 32'h00000080);
|
||||
test_alu(33'h00000001, 33'h0000000E, 1'b0, 1'b0, 1'b1, 3'b000, 2'b10, i, 32'h00004000);
|
||||
test_alu(33'h00000001, 33'h0000001F, 1'b0, 1'b0, 1'b1, 3'b000, 2'b10, i, 32'h80000000);
|
||||
test_alu(33'hffffffff, 33'h00000000, 1'b0, 1'b0, 1'b1, 3'b000, 2'b10, i, 32'hffffffff);
|
||||
test_alu(33'hffffffff, 33'h00000001, 1'b0, 1'b0, 1'b1, 3'b000, 2'b10, i, 32'hfffffffe);
|
||||
test_alu(33'hffffffff, 33'h00000007, 1'b0, 1'b0, 1'b1, 3'b000, 2'b10, i, 32'hffffff80);
|
||||
test_alu(33'hffffffff, 33'h0000000E, 1'b0, 1'b0, 1'b1, 3'b000, 2'b10, i, 32'hffffc000);
|
||||
test_alu(33'hffffffff, 33'h0000001F, 1'b0, 1'b0, 1'b1, 3'b000, 2'b10, i, 32'h80000000);
|
||||
test_alu(33'h21212121, 33'h00000000, 1'b0, 1'b0, 1'b1, 3'b000, 2'b10, i, 32'h21212121);
|
||||
test_alu(33'h21212121, 33'h00000001, 1'b0, 1'b0, 1'b1, 3'b000, 2'b10, i, 32'h42424242);
|
||||
test_alu(33'h21212121, 33'h00000007, 1'b0, 1'b0, 1'b1, 3'b000, 2'b10, i, 32'h90909080);
|
||||
test_alu(33'h21212121, 33'h0000000E, 1'b0, 1'b0, 1'b1, 3'b000, 2'b10, i, 32'h48484000);
|
||||
test_alu(33'h21212121, 33'h0000001F, 1'b0, 1'b0, 1'b1, 3'b000, 2'b10, i, 32'h80000000);
|
||||
// SRL
|
||||
test_alu(33'h80000000, 33'h00000000, 1'b0, 1'b0, 1'b0, 3'b000, 2'b10, i, 32'h80000000);
|
||||
test_alu(33'h80000000, 33'h00000001, 1'b0, 1'b0, 1'b0, 3'b000, 2'b10, i, 32'h40000000);
|
||||
test_alu(33'h80000000, 33'h00000007, 1'b0, 1'b0, 1'b0, 3'b000, 2'b10, i, 32'h01000000);
|
||||
test_alu(33'h80000000, 33'h0000000E, 1'b0, 1'b0, 1'b0, 3'b000, 2'b10, i, 32'h00020000);
|
||||
test_alu(33'h80000000, 33'h0000001F, 1'b0, 1'b0, 1'b0, 3'b000, 2'b10, i, 32'h00000001);
|
||||
test_alu(33'h7fffffff, 33'h00000000, 1'b0, 1'b0, 1'b0, 3'b000, 2'b10, i, 32'h7fffffff);
|
||||
test_alu(33'h7fffffff, 33'h00000001, 1'b0, 1'b0, 1'b0, 3'b000, 2'b10, i, 32'h3fffffff);
|
||||
test_alu(33'h7fffffff, 33'h00000007, 1'b0, 1'b0, 1'b0, 3'b000, 2'b10, i, 32'h00ffffff);
|
||||
test_alu(33'h7fffffff, 33'h0000000E, 1'b0, 1'b0, 1'b0, 3'b000, 2'b10, i, 32'h0001ffff);
|
||||
test_alu(33'h7fffffff, 33'h0000001F, 1'b0, 1'b0, 1'b0, 3'b000, 2'b10, i, 32'h00000000);
|
||||
test_alu(33'h81818181, 33'h00000000, 1'b0, 1'b0, 1'b0, 3'b000, 2'b10, i, 32'h81818181);
|
||||
test_alu(33'h81818181, 33'h00000001, 1'b0, 1'b0, 1'b0, 3'b000, 2'b10, i, 32'h40c0c0c0);
|
||||
test_alu(33'h81818181, 33'h00000007, 1'b0, 1'b0, 1'b0, 3'b000, 2'b10, i, 32'h01030303);
|
||||
test_alu(33'h81818181, 33'h0000000E, 1'b0, 1'b0, 1'b0, 3'b000, 2'b10, i, 32'h00020606);
|
||||
test_alu(33'h81818181, 33'h0000001F, 1'b0, 1'b0, 1'b0, 3'b000, 2'b10, i, 32'h00000001);
|
||||
// SRA
|
||||
test_alu(33'h80000000, 33'h00000000, 1'b0, 1'b1, 1'b0, 3'b000, 2'b10, i, 32'h80000000);
|
||||
test_alu(33'h80000000, 33'h00000001, 1'b0, 1'b1, 1'b0, 3'b000, 2'b10, i, 32'hc0000000);
|
||||
test_alu(33'h80000000, 33'h00000007, 1'b0, 1'b1, 1'b0, 3'b000, 2'b10, i, 32'hff000000);
|
||||
test_alu(33'h80000000, 33'h0000000E, 1'b0, 1'b1, 1'b0, 3'b000, 2'b10, i, 32'hfffe0000);
|
||||
test_alu(33'h80000000, 33'h0000001F, 1'b0, 1'b1, 1'b0, 3'b000, 2'b10, i, 32'hffffffff);
|
||||
test_alu(33'h81818181, 33'h00000000, 1'b0, 1'b1, 1'b0, 3'b000, 2'b10, i, 32'h81818181);
|
||||
test_alu(33'h81818181, 33'h00000001, 1'b0, 1'b1, 1'b0, 3'b000, 2'b10, i, 32'hc0c0c0c0);
|
||||
test_alu(33'h81818181, 33'h00000007, 1'b0, 1'b1, 1'b0, 3'b000, 2'b10, i, 32'hff030303);
|
||||
test_alu(33'h81818181, 33'h0000000E, 1'b0, 1'b1, 1'b0, 3'b000, 2'b10, i, 32'hfffe0606);
|
||||
test_alu(33'h81818181, 33'h0000001F, 1'b0, 1'b1, 1'b0, 3'b000, 2'b10, i, 32'hffffffff);
|
||||
end
|
||||
|
||||
//Randomized Test (operation + latency)
|
||||
for (int i=0; i < 1000; i = i+1) begin
|
||||
test_gen();
|
||||
end
|
||||
|
||||
wait (result_queue.size() == 0);
|
||||
wait (latency_queue.size() == 0);
|
||||
#200;
|
||||
if (result_queue.size() == 0) begin
|
||||
// $display("queue size: %d", result_queue.size());
|
||||
$display("ALU Unit Test -------------------- Passed");
|
||||
end
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -1,303 +0,0 @@
|
|||
/*
|
||||
* Copyright © 2017 Eric Matthews, Lesley Shannon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* Initial code developed under the supervision of Dr. Lesley Shannon,
|
||||
* Reconfigurable Computing Lab, Simon Fraser University.
|
||||
*
|
||||
* Author(s):
|
||||
* Eric Matthews <ematthew@sfu.ca>
|
||||
* Alec Lu <fla30@sfu.ca>
|
||||
*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
import cva5_config::*;
|
||||
import cva5_types::*;
|
||||
|
||||
typedef struct packed{
|
||||
div_inputs_t module_input;
|
||||
logic [31: 0] expected_result;
|
||||
} div_result_t;
|
||||
|
||||
module div_unit_tb ();
|
||||
//DUT Regs and Wires
|
||||
logic clk;
|
||||
logic rst;
|
||||
logic gc_fetch_flush;
|
||||
unit_issue_interface issue();
|
||||
unit_writeback_t wb;
|
||||
div_inputs_t div_inputs;
|
||||
//Internal Regs and Wires
|
||||
integer test_number;
|
||||
//Input
|
||||
integer rs1_rand;
|
||||
integer rs2_rand;
|
||||
int unsigned rs1_urand;
|
||||
int unsigned rs2_urand;
|
||||
integer result_rand;
|
||||
logic [ 1: 0] op_rand;
|
||||
logic reuse_rand;
|
||||
logic accept;
|
||||
//Result
|
||||
div_result_t result_queue[$];
|
||||
div_result_t temp_result;
|
||||
//Latency
|
||||
parameter MAX_RESPONSE_LATENCY = 32'hF;
|
||||
logic wb_done;
|
||||
logic firstPop;
|
||||
logic [31: 0] latency_queue[$];
|
||||
logic [31: 0] wb_done_acc;
|
||||
logic [31: 0] response_latency;
|
||||
|
||||
//DUT
|
||||
div_unit uut (.*);
|
||||
|
||||
//Reset
|
||||
task reset;
|
||||
begin
|
||||
rst = 1'b1;
|
||||
#100 rst = 1'b0;
|
||||
end
|
||||
endtask
|
||||
|
||||
//Clock Gen
|
||||
always
|
||||
#1 clk = ~clk;
|
||||
|
||||
//Latency Logic
|
||||
function int genRandLatency();
|
||||
genRandLatency = $random & MAX_RESPONSE_LATENCY;
|
||||
endfunction
|
||||
|
||||
//With Latency
|
||||
//always_ff @(posedge clk) begin
|
||||
// if (rst) begin
|
||||
// wb_done_acc <= 32'h1;
|
||||
// firstPop <= 1'b1;
|
||||
// response_latency <= 32'hFFFFFFFF;
|
||||
// end else begin
|
||||
// if (wb.done) begin
|
||||
// wb_done_acc <= wb_done_acc + 1;
|
||||
// end else begin
|
||||
// wb_done_acc <= 32'h1;
|
||||
// end
|
||||
|
||||
// if (firstPop | accept) begin
|
||||
// response_latency <= latency_queue.pop_front();
|
||||
// firstPop <= 1'b0;
|
||||
// end else begin
|
||||
// response_latency <= response_latency;
|
||||
// end
|
||||
// end
|
||||
//end
|
||||
//always_ff @(posedge clk) begin
|
||||
// if (rst)
|
||||
// accept <= 0;
|
||||
// else
|
||||
// accept <= wb_done;
|
||||
//end
|
||||
//assign wb_done = wb.done & (wb_done_acc >= response_latency);
|
||||
|
||||
//Without Latency
|
||||
assign wb_done = wb.done;
|
||||
assign accept = wb_done;
|
||||
|
||||
//Output checker
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst)
|
||||
test_number <= 1;
|
||||
if (accept) begin
|
||||
test_number <= test_number + 1;
|
||||
temp_result = result_queue.pop_front();
|
||||
assert (wb.rd == temp_result.expected_result)
|
||||
else $error("Incorrect result on test number %d. (%h, should be: %h)\n\t Input: rs1: %d, rs2: %d, op: %b, reuse_result: %b",
|
||||
test_number, wb.rd, temp_result.expected_result,
|
||||
temp_result.module_input.rs1, temp_result.module_input.rs2,
|
||||
temp_result.module_input.op, temp_result.module_input.reuse_result);
|
||||
end
|
||||
end
|
||||
|
||||
//Driver
|
||||
task test_div (input integer a, b, result, latency, logic[1:0] op, logic reuse);
|
||||
wait (~clk & issue.ready);
|
||||
div_inputs.rs1 = a;
|
||||
div_inputs.rs2 = b;
|
||||
div_inputs.op = op;
|
||||
div_inputs.reuse_result = reuse;
|
||||
div_inputs.instruction_id = 0; //dont care
|
||||
result_queue.push_back({div_inputs, result});
|
||||
latency_queue.push_back(latency);
|
||||
issue.new_request = 1; #2
|
||||
issue.new_request = 0;
|
||||
endtask
|
||||
|
||||
//Generator + Transaction
|
||||
task test_gen();
|
||||
op_rand = $urandom % 4;
|
||||
rs1_rand = $random;
|
||||
rs2_rand = $random;
|
||||
reuse_rand = 0;
|
||||
|
||||
//SW model
|
||||
case (op_rand)
|
||||
2'b00:begin //Div
|
||||
if (rs2_rand == 0) begin
|
||||
result_rand = -1;
|
||||
end else begin
|
||||
result_rand = rs1_rand / rs2_rand;
|
||||
end
|
||||
end
|
||||
2'b01:begin //uDiv
|
||||
if (rs2_rand == 0) begin
|
||||
result_rand = -1;
|
||||
end else begin
|
||||
rs1_urand = rs1_rand;
|
||||
rs2_urand = rs2_rand;
|
||||
result_rand = rs1_urand / rs2_urand;
|
||||
end
|
||||
end
|
||||
2'b10:begin //Rem
|
||||
if (rs2_rand == 0) begin
|
||||
result_rand = rs1_rand;
|
||||
end else begin
|
||||
result_rand = rs1_rand % rs2_rand;
|
||||
end
|
||||
end
|
||||
2'b11:begin //uRem
|
||||
if (rs2_rand == 0) begin
|
||||
result_rand = rs1_rand;
|
||||
end else begin
|
||||
rs1_urand = rs1_rand;
|
||||
rs2_urand = rs2_rand;
|
||||
result_rand = rs1_urand % rs2_urand;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
|
||||
test_div (rs1_rand, rs2_rand, result_rand, genRandLatency(), op_rand, reuse_rand);
|
||||
endtask
|
||||
|
||||
initial
|
||||
begin
|
||||
clk = 0;
|
||||
rst = 1;
|
||||
gc_fetch_flush = 0;
|
||||
div_inputs.rs1 = 0;
|
||||
div_inputs.rs2 = 0;
|
||||
div_inputs.op = 0;
|
||||
div_inputs.reuse_result = 0;
|
||||
issue.new_request = 0;
|
||||
|
||||
reset();
|
||||
|
||||
// //Randomized Test (operation + latency)
|
||||
// for (int i=0; i < 5000; i = i+1) begin
|
||||
// test_gen();
|
||||
// end
|
||||
|
||||
for (int i=0; i < 6; i = i+5) begin
|
||||
//Div test
|
||||
test_div( 20, 6, 3, i, 2'b00, 0);
|
||||
test_div(-20, -3, 6, i, 2'b00, 0);
|
||||
test_div(-20, 6, -3, i, 2'b00, 0);
|
||||
test_div( 20, -6, -3, i, 2'b00, 0);
|
||||
test_div(-20, -6, 3, i, 2'b00, 0);
|
||||
|
||||
test_div(-1<<31, 1, -1<<31, i, 2'b00, 0);
|
||||
test_div(-1<<31, -1, -1<<31, i, 2'b00, 0);
|
||||
|
||||
test_div(-1<<31, 0, -1, i, 2'b00, 0);
|
||||
test_div(-1, 0, -1, i, 2'b00, 0);
|
||||
test_div(0, 0, -1, i, 2'b00, 0);
|
||||
|
||||
//uDiv test
|
||||
test_div( 20, 6, 3, i, 2'b01, 0);
|
||||
test_div(-20, 6, 715827879, i, 2'b01, 0);
|
||||
test_div( 20, -6, 0, i, 2'b01, 0);
|
||||
test_div(-20, -6, 0, i, 2'b01, 0);
|
||||
|
||||
test_div(-1<<31, 1, -1<<31, i, 2'b01, 0);
|
||||
test_div(-1<<31, -1, 0, i, 2'b01, 0);
|
||||
|
||||
test_div(-1<<31, 0, -1, i, 2'b01, 0);
|
||||
test_div( 1, 0, -1, i, 2'b01, 0);
|
||||
test_div( 0, 0, -1, i, 2'b01, 0);
|
||||
|
||||
test_div(486456, 1, 486456, i, 2'b01, 0);
|
||||
test_div( 200, 200, 1, i, 2'b01, 0);
|
||||
test_div(234678, 2, 234678/2, i, 2'b01, 0);
|
||||
|
||||
//rem test
|
||||
test_div( 20, 6, 2, i, 2'b10, 0);
|
||||
test_div(-20, 6, -2, i, 2'b10, 0);
|
||||
test_div( 20, -6, 2, i, 2'b10, 0);
|
||||
test_div(-20, -6, -2, i, 2'b10, 0);
|
||||
|
||||
test_div(-1<<31, 1, 0, i, 2'b10, 0);
|
||||
test_div(-1<<31, -1, 0, i, 2'b10, 0);
|
||||
|
||||
test_div(-1<<31, 0, -1<<31, i, 2'b10, 0);
|
||||
test_div( 1, 0, 1, i, 2'b10, 0);
|
||||
test_div( 0, 0, 0, i, 2'b10, 0);
|
||||
|
||||
//remu test
|
||||
test_div( 20, 6, 2, i, 2'b11, 0);
|
||||
test_div(-20, 6, 2, i, 2'b11, 0);
|
||||
test_div( 20, -6, 20, i, 2'b11, 0);
|
||||
test_div(-20, -6, -20, i, 2'b11, 0);
|
||||
|
||||
test_div(-1<<31, 1, 0, i, 2'b11, 0);
|
||||
test_div(-1<<31, -1, -1<<31, i, 2'b11, 0);
|
||||
|
||||
test_div(-1<<31, 0, -1<<31, i, 2'b11, 0);
|
||||
test_div( 1, 0, 1, i, 2'b11, 0);
|
||||
test_div( 0, 0, 0, i, 2'b11, 0);
|
||||
|
||||
//reuse result tests
|
||||
test_div(20, 6, 2, i, 2'b11, 0);
|
||||
test_div(20, 6, 2, i, 2'b10, 1);
|
||||
test_div(20, 6, 3, i, 2'b00, 1);
|
||||
|
||||
test_div(200, 200, 1, i, 2'b01, 0);
|
||||
test_div(200, 200, 1, i, 2'b00, 1);
|
||||
end
|
||||
|
||||
wait (result_queue.size() == 0);
|
||||
//wait (latency_queue.size() == 0);
|
||||
#200;
|
||||
if (result_queue.size() == 0) begin
|
||||
// $display("queue size: %d", result_queue.size());
|
||||
|
||||
case(DIV_ALGORITHM)
|
||||
RADIX_2 : $display("RADIX_2");
|
||||
RADIX_2_EARLY_TERMINATE : $display("RADIX_2_EARLY_TERMINATE");
|
||||
RADIX_2_EARLY_TERMINATE_FULL : $display("RADIX_2_EARLY_TERMINATE_FULL");
|
||||
RADIX_4 : $display("RADIX_4");
|
||||
RADIX_4_EARLY_TERMINATE : $display("RADIX_4_EARLY_TERMINATE");
|
||||
RADIX_8 : $display("RADIX_8");
|
||||
RADIX_8_EARLY_TERMINATE : $display("RADIX_8_EARLY_TERMINATE");
|
||||
RADIX_16 : $display("RADIX_16");
|
||||
QUICK_NAIVE : $display("QUICK_NAIVE");
|
||||
QUICK_CLZ : $display("QUICK_CLZ");
|
||||
QUICK_CLZ_MK2 : $display("QUICK_CLZ_MK2");
|
||||
QUICK_RADIX_4 : $display("QUCIK_RADIX_4");
|
||||
default : $error("invalid div selection");
|
||||
endcase
|
||||
$display("Div Unit Test -------------------- Passed");
|
||||
end
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,289 +0,0 @@
|
|||
/*
|
||||
* Copyright © 2017 Eric Matthews, Lesley Shannon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* Initial code developed under the supervision of Dr. Lesley Shannon,
|
||||
* Reconfigurable Computing Lab, Simon Fraser University.
|
||||
*
|
||||
* Author(s):
|
||||
* Alec Lu <fla30@sfu.ca>
|
||||
* Eric Matthews <ematthew@sfu.ca>
|
||||
*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
import cva5_config::*;
|
||||
import cva5_types::*;
|
||||
|
||||
typedef struct packed{
|
||||
mul_inputs_t module_input;
|
||||
logic [31: 0] expected_result;
|
||||
} mul_result_t;
|
||||
|
||||
module mul_unit_tb();
|
||||
//DUT Regs and Wires
|
||||
logic clk;
|
||||
logic rst;
|
||||
func_unit_ex_interface mul_ex();
|
||||
unit_writeback_interface mul_wb();
|
||||
mul_inputs_t mul_inputs;
|
||||
|
||||
//Internal Regs and Wires
|
||||
integer test_number;
|
||||
//Input
|
||||
int rs1_rand;
|
||||
int rs2_rand;
|
||||
int unsigned rs1_urand;
|
||||
int unsigned rs2_urand;
|
||||
longint signedMulResult;
|
||||
longint unsigned unsignedMulResult;
|
||||
logic [31: 0] result_rand;
|
||||
logic [ 1: 0] op_rand;
|
||||
//Result
|
||||
mul_result_t result_queue[$];
|
||||
mul_result_t temp_result;
|
||||
//Latency
|
||||
parameter MAX_RESPONSE_LATENCY = 32'hF;
|
||||
logic wb_done;
|
||||
logic firstPop;
|
||||
logic [31: 0] latency_queue[$];
|
||||
logic [31: 0] wb_done_acc;
|
||||
logic [31: 0] response_latency;
|
||||
|
||||
//DUT
|
||||
mul_unit uut (.*);
|
||||
|
||||
//Reset
|
||||
task reset;
|
||||
begin
|
||||
rst = 1'b1;
|
||||
#100 rst = 1'b0;
|
||||
end
|
||||
endtask
|
||||
|
||||
//Clock Gen
|
||||
always
|
||||
#1 clk = ~clk;
|
||||
|
||||
//Latency Logic
|
||||
function int genRandLatency();
|
||||
genRandLatency = $random & MAX_RESPONSE_LATENCY;
|
||||
endfunction
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst) begin
|
||||
wb_done_acc <= 32'h1;
|
||||
firstPop <= 1'b1;
|
||||
response_latency <= 32'hFFFFFFFF;
|
||||
end else begin
|
||||
if (mul_wb.done_next_cycle) begin
|
||||
wb_done_acc <= wb_done_acc + 1;
|
||||
end else begin
|
||||
wb_done_acc <= 32'h1;
|
||||
end
|
||||
|
||||
if (firstPop | mul_wb.accepted) begin
|
||||
response_latency <= latency_queue.pop_front();
|
||||
firstPop <= 1'b0;
|
||||
end else begin
|
||||
response_latency <= response_latency;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign wb_done = mul_wb.done_next_cycle & (wb_done_acc >= response_latency);
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst)
|
||||
mul_wb.accepted <= 0;
|
||||
else
|
||||
mul_wb.accepted <= wb_done;
|
||||
end
|
||||
|
||||
//Output checker
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst)
|
||||
test_number <= 1;
|
||||
if (mul_wb.accepted) begin
|
||||
test_number <= test_number + 1;
|
||||
temp_result = result_queue.pop_front();
|
||||
if (temp_result.expected_result != 32'hxxxxxxxx) begin
|
||||
assert (mul_wb.rd == temp_result.expected_result)
|
||||
else $error("Incorrect result on test number %d. (%h, should be: %h)\n\t Input: rs1: %d, rs2: %d, op: %b",
|
||||
test_number, mul_wb.rd, temp_result.expected_result,
|
||||
temp_result.module_input.rs1, temp_result.module_input.rs2,
|
||||
temp_result.module_input.op);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
//Driver
|
||||
task test_div (input logic [XLEN-1:0] a, b, result, latency, logic[1:0] op);
|
||||
wait (~clk & mul_ex.ready);
|
||||
mul_inputs.rs1 = a;
|
||||
mul_inputs.rs2 = b;
|
||||
mul_inputs.op = op;
|
||||
result_queue.push_back({mul_inputs, result});
|
||||
latency_queue.push_back(latency);
|
||||
mul_ex.new_request_dec = 1; #2
|
||||
mul_ex.new_request_dec = 0;
|
||||
endtask
|
||||
|
||||
//Generator + Transaction
|
||||
task test_gen();
|
||||
op_rand = $urandom % 4;
|
||||
rs1_rand = $random;
|
||||
rs2_rand = $random;
|
||||
|
||||
//SW model
|
||||
case (op_rand)
|
||||
2'b00:begin //MUL
|
||||
signedMulResult = rs1_rand * rs2_rand;
|
||||
result_rand = signedMulResult[31: 0];
|
||||
end
|
||||
2'b01:begin //MULH
|
||||
signedMulResult = rs1_rand * rs2_rand;
|
||||
result_rand = signedMulResult[63:32];
|
||||
end
|
||||
2'b10:begin //MULHSU - rs1(signed) & rs2(unsigned)
|
||||
if (rs1_rand[31]) begin
|
||||
rs1_urand = rs1_rand * -1;
|
||||
rs2_urand = rs2_rand;
|
||||
unsignedMulResult = rs1_urand * rs2_urand;
|
||||
signedMulResult = unsignedMulResult;
|
||||
signedMulResult = signedMulResult * -1;
|
||||
result_rand = signedMulResult[63:32];
|
||||
end else begin
|
||||
rs1_urand = rs1_rand;
|
||||
rs2_urand = rs2_rand;
|
||||
unsignedMulResult = rs1_urand * rs2_urand;
|
||||
result_rand = unsignedMulResult[63:32];
|
||||
end
|
||||
end
|
||||
2'b11:begin //MULHU
|
||||
rs1_urand = rs1_rand;
|
||||
rs2_urand = rs2_rand;
|
||||
unsignedMulResult = rs1_urand * rs2_urand;
|
||||
result_rand = unsignedMulResult[63:32];
|
||||
end
|
||||
endcase
|
||||
|
||||
test_div (rs1_rand, rs2_rand, result_rand, genRandLatency(), op_rand);
|
||||
endtask
|
||||
|
||||
initial
|
||||
begin
|
||||
clk = 0;
|
||||
rst = 1;
|
||||
mul_inputs.rs1 = 0;
|
||||
mul_inputs.rs2 = 0;
|
||||
mul_inputs.op = 0;
|
||||
mul_ex.new_request_dec = 0;
|
||||
mul_wb.accepted = 0;
|
||||
|
||||
reset();
|
||||
|
||||
//Randomized Test (operation + latency)
|
||||
for (int i=0; i < 1000; i = i+1) begin
|
||||
test_gen();
|
||||
end
|
||||
|
||||
for (int i=0; i < 6; i = i+5) begin
|
||||
//MUL
|
||||
test_div (32'h00007e00, 32'hb6db6db7, 32'h00001200, i, 2'b00);
|
||||
test_div (32'h00007fc0, 32'hb6db6db7, 32'h00001240, i, 2'b00);
|
||||
|
||||
test_div (32'h00000000, 32'h00000000, 32'h00000000, i, 2'b00);
|
||||
test_div (32'h00000001, 32'h00000001, 32'h00000001, i, 2'b00);
|
||||
test_div (32'h00000003, 32'h00000007, 32'h00000015, i, 2'b00);
|
||||
|
||||
test_div (32'hffff8000, 32'h00000000, 32'h00000000, i, 2'b00);
|
||||
test_div (32'h00000000, 32'h80000000, 32'h00000000, i, 2'b00);
|
||||
test_div (32'hffff8000, 32'h80000000, 32'h00000000, i, 2'b00);
|
||||
|
||||
test_div (32'haaaaaaab, 32'h0002fe7d, 32'h0000ff7f, i, 2'b00);
|
||||
test_div (32'h0002fe7d, 32'haaaaaaab, 32'h0000ff7f, i, 2'b00);
|
||||
|
||||
test_div (32'hff000000, 32'hff000000, 32'h00000000, i, 2'b00);
|
||||
|
||||
test_div (32'hffffffff, 32'hffffffff, 32'h00000001, i, 2'b00);
|
||||
test_div (32'h00000001, 32'hffffffff, 32'hffffffff, i, 2'b00);
|
||||
test_div (32'hffffffff, 32'h00000001, 32'hffffffff, i, 2'b00);
|
||||
|
||||
//MULH
|
||||
test_div (32'h00000000, 32'h00000000, 32'h00000000, i, 2'b01);
|
||||
test_div (32'h00000001, 32'h00000001, 32'h00000000, i, 2'b01);
|
||||
test_div (32'h00000003, 32'h00000007, 32'h00000000, i, 2'b01);
|
||||
|
||||
test_div (32'h00000000, 32'hffff8000, 32'h00000000, i, 2'b01);
|
||||
test_div (32'h80000000, 32'h00000000, 32'h00000000, i, 2'b01);
|
||||
test_div (32'h80000000, 32'h00000000, 32'h00000000, i, 2'b01);
|
||||
|
||||
test_div (32'haaaaaaab, 32'h0002fe7d, 32'hffff0081, i, 2'b01);
|
||||
test_div (32'h0002fe7d, 32'haaaaaaab, 32'hffff0081, i, 2'b01);
|
||||
|
||||
test_div (32'hff000000, 32'hff000000, 32'h00010000, i, 2'b01);
|
||||
|
||||
test_div (32'hffffffff, 32'hffffffff, 32'h00000000, i, 2'b01);
|
||||
test_div (32'hffffffff, 32'h00000001, 32'hffffffff, i, 2'b01);
|
||||
test_div (32'h00000001, 32'hffffffff, 32'hffffffff, i, 2'b01);
|
||||
|
||||
//MULHSU - rs1(signed) & rs2(unsigned)
|
||||
test_div (32'h00000000, 32'h00000000, 32'h00000000, i, 2'b10);
|
||||
test_div (32'h00000001, 32'h00000001, 32'h00000000, i, 2'b10);
|
||||
test_div (32'h00000007, 32'h00000003, 32'h00000000, i, 2'b10);
|
||||
|
||||
test_div (32'hffff8000, 32'h00000000, 32'h00000000, i, 2'b10);
|
||||
test_div (32'h00000000, 32'h80000000, 32'h00000000, i, 2'b10);
|
||||
test_div (32'h80000000, 32'hffff8000, 32'h80004000, i, 2'b10);
|
||||
|
||||
test_div (32'haaaaaaab, 32'h0002fe7d, 32'hffff0081, i, 2'b10);
|
||||
test_div (32'h0002fe7d, 32'haaaaaaab, 32'h0001fefe, i, 2'b10);
|
||||
|
||||
test_div (32'hff000000, 32'hff000000, 32'hff010000, i, 2'b10);
|
||||
|
||||
test_div (32'hffffffff, 32'hffffffff, 32'hffffffff, i, 2'b10);
|
||||
test_div (32'hffffffff, 32'h00000001, 32'hffffffff, i, 2'b10);
|
||||
test_div (32'h00000001, 32'hffffffff, 32'h00000000, i, 2'b10);
|
||||
|
||||
//MULHU
|
||||
test_div (32'h00000000, 32'h00000000, 32'h00000000, i, 2'b11);
|
||||
test_div (32'h00000001, 32'h00000001, 32'h00000000, i, 2'b11);
|
||||
test_div (32'h00000003, 32'h00000007, 32'h00000000, i, 2'b11);
|
||||
|
||||
test_div (32'hffff8000, 32'h00000000, 32'h00000000, i, 2'b11);
|
||||
test_div (32'h80000000, 32'h00000000, 32'h00000000, i, 2'b11);
|
||||
test_div (32'h80000000, 32'hffff8000, 32'h7fffc000, i, 2'b11);
|
||||
|
||||
test_div (32'haaaaaaab, 32'h0002fe7d, 32'h0001fefe, i, 2'b11);
|
||||
test_div (32'h0002fe7d, 32'haaaaaaab, 32'h0001fefe, i, 2'b11);
|
||||
|
||||
test_div (32'hff000000, 32'hff000000, 32'hfe010000, i, 2'b11);
|
||||
|
||||
test_div (32'hffffffff, 32'hffffffff, 32'hfffffffe, i, 2'b11);
|
||||
test_div (32'hffffffff, 32'h00000001, 32'h00000000, i, 2'b11);
|
||||
test_div (32'h00000001, 32'hffffffff, 32'h00000000, i, 2'b11);
|
||||
end
|
||||
|
||||
wait (result_queue.size() == 0);
|
||||
wait (latency_queue.size() == 0);
|
||||
#200;
|
||||
if (result_queue.size() == 0) begin
|
||||
// $display("queue size: %d", result_queue.size());
|
||||
$display("Mul Unit Test -------------------- Passed");
|
||||
end
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
3
tools/.gitignore
vendored
3
tools/.gitignore
vendored
|
|
@ -1,3 +0,0 @@
|
|||
*.log
|
||||
*.hw_init
|
||||
*.sim_init
|
||||
Loading…
Add table
Add a link
Reference in a new issue