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makefile refactor

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This commit is contained in:
Eric Matthews 2020-07-29 10:28:12 -07:00
parent 81f2ac3bc7
commit a15921cdf3
9 changed files with 174 additions and 540 deletions
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4
test_benches/verilator/TaigaTracer.cc
View file

@ -187,9 +187,9 @@ TaigaTracer<TB>::TaigaTracer(std::ifstream& programFile) {
tb = new TB;
#ifdef DDR_LOAD_FILE
axi_ddr = new axi_ddr_sim<Vtaiga_local_mem>(DDR_INIT_FILE,DDR_FILE_STARTING_LOCATION,DDR_FILE_NUM_BYTES);
axi_ddr = new axi_ddr_sim<Vtaiga_sim>(DDR_INIT_FILE,DDR_FILE_STARTING_LOCATION,DDR_FILE_NUM_BYTES);
#else
axi_ddr = new axi_ddr_sim<Vtaiga_local_mem>(programFile, tb);
axi_ddr = new axi_ddr_sim<Vtaiga_sim>(programFile, tb);
#endif
programFile.clear();

2
test_benches/verilator/TaigaTracer.h
View file

@ -26,7 +26,7 @@
#include <iostream>
#include <iterator>
#include "SimMem.h"
#include "axi_ddr_sim.h"
#include "AXI_DDR_simulation/axi_ddr_sim.h"
//#define TRACE_ON
#define COMPLIANCE_SIG_PHASE_NOP 0x00B00013U

134
test_benches/verilator/id_stack_sim.cc
View file

@ -1,134 +0,0 @@
#include <stdlib.h>
#include <iostream>
#include <random>
#include "Vid_stack.h"
#include "verilated.h"
#include "verilated_vcd_c.h"
using namespace std;
int stack_occupancy_count;
bool id_check(Vid_stack *tb) {
bool result = true;
for (int i = 0; i < 4; i++) {
for (int j = i + 1; j < 4; j++) {
result = result && (tb->ordering[i] != tb->ordering[j]);
}
}
return result;
}
bool inuse[4];
//Only retire IDs that have been issued (or true if none issued)
bool retired_id_valid(Vid_stack *tb) {
return (stack_occupancy_count == 0) || inuse[tb->retired_id];
}
std::mt19937 rng;
std::bernoulli_distribution dist(0.5);
void generate_random_valid_inputs(Vid_stack *tb) {
int occupancy_change;
do {
occupancy_change = 0;
tb->issued = dist(rng);
tb->retired = dist(rng);
tb->retired_id = (dist(rng) << 1) | dist(rng);
occupancy_change += tb->issued;
occupancy_change -= tb->retired;
} while (
(tb->retired && stack_occupancy_count == 0) ||
(tb->issued && tb->retired && stack_occupancy_count == 4) ||
(stack_occupancy_count + occupancy_change) < 0 || (stack_occupancy_count + occupancy_change) > 4
|| !retired_id_valid(tb));
if (tb->retired)
inuse[tb->retired_id] = false;
if (tb->issued)
inuse[tb->ordering[3-stack_occupancy_count]] = true;
int id_index = 0;
for(int i=0; i < 4; i++) {
if (tb->retired_id == tb->ordering[i])
id_index = i;
}
tb->shift_bits = (1 << (id_index + 1)) - 1;
stack_occupancy_count += occupancy_change;
cout << "gen: "<< (int)(tb->issued) << " " << (int)(tb->retired) << " " << (int)(tb->retired_id) << " " << stack_occupancy_count;
cout << " [";
for(int i=0; i < 4; i++)
cout << inuse[i] << " ";
cout << "]" << "\n";
}
int main(int argc, char **argv) {
// Initialize Verilators variables
Verilated::commandArgs(argc, argv);
Verilated::traceEverOn(true);
// Create an instance of our module under test
Vid_stack *tb = new Vid_stack;
VerilatedVcdC *tracer = new VerilatedVcdC;
tb->trace(tracer, 99);
tracer->open("id_stack_sim_results.vcd");
cout << "Starting test\n";
cout << "******************************\n";
int reset_count = 0;
long int cycle_cout = 0;
stack_occupancy_count = 0;
tb->rst = 1;
tb->issued = 0;
tb->retired = 0;
tb->retired_id = 0;
tb->clk = 0;
tb->shift_bits = 0;
for(int i=0; i < 4; i++)
inuse[i] = false;
// Tick the clock until we are done
while (!Verilated::gotFinish()) {
if (reset_count > 64) {
tb->rst = 0;
} else {
reset_count++;
}
if (cycle_cout >= 1000) {
break;
}
tb->clk = 0;
tb->eval();
tb->clk = 1;
tb->eval();
if (tb->rst == 0)
generate_random_valid_inputs(tb);
tracer->dump(vluint64_t(cycle_cout));
cycle_cout++;
}
tracer->flush();
tracer->close();
cout << "******************************\n";
cout << "Test Done\n";
cout << "Simulated: " << cycle_cout << " cycles.";
delete tb;
exit (EXIT_SUCCESS);
}

130
test_benches/verilator/taiga_local_mem_compliance.cc
View file

@ -1,130 +0,0 @@
#include <stdlib.h>
#include <iostream>
#include <fstream>
#include "Vtaiga_local_mem_compliance.h"
#include "verilated.h"
#include "verilated_vcd_c.h"
using namespace std;
int main(int argc, char **argv) {
ofstream logFile, sigFile;
bool logPhase;
bool stallDetected = false;
int stall_cycles = 0;
// Initialize Verilators variables
Verilated::commandArgs(argc, argv);
#ifdef TRACE_ON
Verilated::traceEverOn(true);
#endif
if (!argv[1]) {
cout << "Missing log file name.\n";
exit(EXIT_FAILURE);
}
if (!argv[2]) {
cout << "Missing signature file name.\n";
exit(EXIT_FAILURE);
}
logFile.open (argv[1]);
sigFile.open (argv[2]);
// Create an instance of our module under test
Vtaiga_local_mem_compliance *tb = new Vtaiga_local_mem_compliance;
#ifdef TRACE_ON
VerilatedVcdC *tracer;
tracer = new VerilatedVcdC;
tb->trace(tracer, 99);
tracer->open("sim_results.vcd");
#endif
cout << "\n\nStarting test: " << argv[2] << "\n";
cout << "******************************\n";
int reset_count = 0;
long int cycle_cout = 0;
tb->rst = 1;
logPhase = true;
// Tick the clock until we are done
while(!Verilated::gotFinish()) {
if (reset_count > 64) {
tb->rst = 0;
}
else {
reset_count++;
}
tb->clk = 1;
tb->eval();
tb->clk = 0;
tb->eval();
//Custom nop to change to signature phase
if (tb->dec_instruction_r == 0x00B00013U) {
logPhase = false;
cout << "******************************\n";
cout << "\n\n**********Signature***********\n";
}
//if (!logPhase) {
// std::cout << std::hex << tb-> dec_pc_debug_r << std::endl;
//}
if (tb->write_uart) {
if (logPhase) {
cout << tb->uart_byte;
logFile << tb->uart_byte;
} else {
cout << tb->uart_byte;
sigFile << tb->uart_byte;
}
}
//Custom nop for termination
if (tb->dec_instruction_r == 0x00F00013U) {
cout << "\n\nError!!!!\n\n";
break;
}
else if (tb->dec_instruction_r == 0x00A00013U) {
break;
}
#ifdef TRACE_ON
tracer->dump(vluint64_t(cycle_cout));
#endif
cycle_cout++;
if (!tb->dec_advance_debug) {
stall_cycles++;
if (stall_cycles > 2000) {
stall_cycles = 0;
cout << "\n\nError!!!!\n";
cout << "PC unchanged for at least 2000 cycles!\n\n";
break;
}
} else {
stall_cycles = 0;
}
}
#ifdef TRACE_ON
tracer->flush();
tracer->close();
#endif
cout << "\n******************************\n\n";
cout << "Test Done\n";
cout << "Simulated: " << cycle_cout << " cycles.\n\n\n";
logFile.close();
sigFile.close();
delete tb;
exit(EXIT_SUCCESS);
}

6
test_benches/verilator/taiga_local_mem.cc → test_benches/verilator/taiga_sim.cc
View file

@ -2,12 +2,12 @@
#include <stdlib.h>
#include <iostream>
#include <fstream>
#include "Vtaiga_local_mem.h"
#include "Vtaiga_sim.h"
#include "verilated.h"
#include "verilated_vcd_c.h"
#include "TaigaTracer.h"
TaigaTracer<Vtaiga_local_mem> *taigaTracer;
TaigaTracer<Vtaiga_sim> *taigaTracer;
//For time index on assertions
double sc_time_stamp () {
@ -62,7 +62,7 @@ int main(int argc, char **argv) {
}
// Create an instance of our module under test
taigaTracer = new TaigaTracer<Vtaiga_local_mem>(programFile);
taigaTracer = new TaigaTracer<Vtaiga_sim>(programFile);
taigaTracer->set_log_file(&logFile);
#ifdef TRACE_ON
taigaTracer->start_tracer(argv[4]);

4
test_benches/verilator/taiga_local_mem.sv → test_benches/verilator/taiga_sim.sv
View file

@ -25,7 +25,7 @@ import taiga_types::*;
import l2_config_and_types::*;
module taiga_local_mem # (
module taiga_sim # (
parameter MEMORY_FILE = "/home/ematthew/Research/RISCV/software/riscv-tools/riscv-tests/benchmarks/dhrystone.riscv.hw_init" //change this to appropriate location "/home/ematthew/Downloads/dhrystone.riscv.sim_init"
)
(
@ -431,4 +431,4 @@ module taiga_local_mem # (
taiga_events[$bits(taiga_trace_events_t)-1-i] = taiga_events_packed[i];
end
endmodule
endmodule

199
tools/Makefile
View file

@ -1,199 +0,0 @@
#MAKEFLAGS += --silent
-include internal.mak
MAKEFILE_DIR=$(pwd)
TAIGA_DIR=/home/ematthew/taiga
RISCV_PREFIX ?= riscv32-unknown-elf-
#Verilator parameters
###############################################################
VERILATOR_DIR=$(TAIGA_DIR)/test_benches/verilator
TAIGA_SRCS = $(shell cat taiga_compile_order)
#Tracing: Set to True or False
TRACE_ENABLE=False
VERILATOR_TRACE_FILE="/data/sim-logs/sim_results.vcd"
#DDR Pre-Initialization
LOAD_DDR_FROM_FILE = False
DDR_FILE = "\"path_to_DDR_init_file\""
DDR_FILE_STARTING_LOCATION = 0
DDR_FILE_NUM_BYTES = 0
#AXI DDR Parameters
DDR_SIZE_GB = 4
PAGE_SIZE_KB = 2
MAX_READ_REQ = 8
MAX_WRITE_REQ = $(MAX_READ_REQ)
MIN_RD_DELAY = 1
MAX_RD_DELAY = 1
MIN_WR_DELAY = 1
MAX_WR_DELAY = 1
DELAY_SEED = 867583
######################################################################
ddr_size_def = DDR_SIZE=\(long\)$(DDR_SIZE_GB)*\(long\)1073741824
page_size_def = PAGE_SIZE=\($(PAGE_SIZE_KB)*1024\)
max_inflight_read_requests = MAX_INFLIGHT_RD_REQ=$(MAX_READ_REQ)
max_inflight_write_requests = MAX_INFLIGHT_WD_REQ=$(MAX_WRITE_REQ)
mix_delay_read = MIN_DELAY_RD=$(MIN_RD_DELAY)
max_delay_read = MAX_DELAY_RD=$(MAX_RD_DELAY)
min_delay_write = MIN_DELAY_WR=$(MIN_WR_DELAY)
max_delay_write = MAX_DELAY_WR=$(MAX_WR_DELAY)
delay_seed = DELAY_SEED=$(DELAY_SEED)
ddr_init_file = DDR_INIT_FILE=$(DDR_FILE)
ddr_start_loc = DDR_FILE_STARTING_LOCATION=$(DDR_FILE_STARTING_LOCATION)
ddr_num_bytes = DDR_FILE_NUM_BYTES=$(DDR_FILE_NUM_BYTES)
CFLAGS = -g0 -O3 -march=native -D$(ddr_size_def) -D$(page_size_def) -D$(max_inflight_read_requests) -D$(max_inflight_write_requests)\
-D$(mix_delay_read) -D$(max_delay_read) -D$(min_delay_write) -D$(max_delay_write) -D$(delay_seed)\
-D$(ddr_init_file) -D$(ddr_start_loc) -D$(ddr_num_bytes)
#Verilator
################################################################################
VERILATOR_LINT_IGNORE= -Wno-LITENDIAN -Wno-SYMRSVDWORD
ifeq ($(TRACE_ENABLE), True)
VERILATOR_CFLAGS = --trace --trace-structs --CFLAGS "$(CFLAGS) -D TRACE_ON"
else
VERILATOR_CFLAGS = --CFLAGS "$(CFLAGS)"
endif
ifeq ($(LOAD_DDR_FROM_FILE), True)
VERILATOR_CFLAGS := $(VERILATOR_CFLAGS) -D LOAD_DDR_FROM_FILE"
endif
##################################################################################
#Compliance parameters
###############################################################
COMPLIANCE_DIR=/home/ematthew/Research/RISCV/sfu-rcl/taiga-riscv-compliance/
COMPLIANCE_TARGET=rv32im
###############################################################
#Benchmark parameters
#Assumes binaries are in the BENCHMARK_DIR
###############################################################
EMBENCH_DIR=/home/ematthew/Research/RISCV/sfu-rcl/taiga-embench
EMBENCH_BENCHMARKS = \
aha-mont64 \
crc32 \
cubic \
edn \
huffbench \
matmult-int \
minver \
nbody \
nettle-aes \
nettle-sha256 \
nsichneu \
picojpeg \
qrduino \
sglib-combined \
slre \
st \
statemate \
ud \
wikisort \
embench_logs = $(addsuffix _full.log, $(EMBENCH_BENCHMARKS))
embench_hw = $(addsuffix .hw_init, $(EMBENCH_BENCHMARKS))
embench_sim = $(addsuffix .sim_init, $(EMBENCH_BENCHMARKS))
###############################################################
COREMARK_DIR=/home/ematthew/Research/RISCV/software/coremark
#Binary to Verilog HW init file
###############################################################
ELF_TO_HW_INIT ?= python3 $(TAIGA_DIR)/tools/taiga_binary_converter.py $(RISCV_PREFIX) 0x80000000 131072
###############################################################
.PHONY: lint
lint:
verilator -cc $(TAIGA_SRCS) \
../test_benches/verilator/taiga_local_mem.sv \
--top-module taiga_local_mem \
--lint-only
.PHONY: lint_full
lint_full:
verilator -cc $(TAIGA_SRCS) \
../test_benches/verilator/taiga_local_mem.sv \
--top-module taiga_local_mem \
--lint-only -Wall
.PHONY: build_embench
build_embench :
cd $(EMBENCH_DIR);\
rm -rf build;\
mkdir build;\
cd build;\
../configure --host=riscv32-unknown-elf --with-chip=speed-test --with-board=taiga-sim;\
make
.PHONY: build_coremark
build_coremark:
$(MAKE) -C $(COREMARK_DIR) compile PORT_DIR=taiga-sim ITERATIONS=5000
cd $(MAKEFILE_DIR);
$(ELF_TO_HW_INIT) $(COREMARK_DIR)/coremark.bin coremark.hw_init coremark.sim_init
.PHONY: run_coremark_verilator
run_coremark_verilator :
./build_taiga_sim/Vtaiga_local_mem "/dev/null" "/dev/null" $(TAIGA_DIR)/tools/coremark.hw_init $(VERILATOR_TRACE_FILE) > $@
#Benchmarks already built
.PHONY : $(EMBENCH_BENCHMARKS)
#Create hw_init files for benchmarks
$(embench_hw) : %.hw_init : %
$(ELF_TO_HW_INIT) $(EMBENCH_DIR)/build/src/$</$< $@ $<.sim_init
build_taiga_sim: $(TAIGA_SRCS)
mkdir -p $@
cp $(VERILATOR_DIR)/TaigaTracer.h $@/
cp $(VERILATOR_DIR)/TaigaTracer.cc $@/
cp $(VERILATOR_DIR)/SimMem.h $@/
cp $(VERILATOR_DIR)/SimMem.cc $@/
cp $(VERILATOR_DIR)/taiga_local_mem.cc $@/
cp $(VERILATOR_DIR)/AXI_DDR_simulation/axi_ddr_sim.cc $@/
cp $(VERILATOR_DIR)/AXI_DDR_simulation/axi_ddr_sim.h $@/
cp $(VERILATOR_DIR)/AXI_DDR_simulation/ddr_page.cc $@/
cp $(VERILATOR_DIR)/AXI_DDR_simulation/ddr_page.h $@/
cp $(VERILATOR_DIR)/AXI_DDR_simulation/axi_interface.h $@/
verilator --cc --exe --Mdir $@ -DENABLE_SIMULATION_ASSERTIONS --assert $(VERILATOR_LINT_IGNORE) $(VERILATOR_CFLAGS) $(TAIGA_SRCS) \
../test_benches/verilator/taiga_local_mem.sv --top-module taiga_local_mem taiga_local_mem.cc ddr_page.cc SimMem.cc
$(MAKE) -C $@ -f Vtaiga_local_mem.mk
#Run verilator
$(embench_logs) : %_full.log : % $(embench_hw) build_taiga_sim
@echo $< > $@
./build_taiga_sim/Vtaiga_local_mem "/dev/null" "/dev/null" $(TAIGA_DIR)/tools/$<.hw_init $(VERILATOR_TRACE_FILE) >> $@
run_embench_verilator: $(embench_logs)
cat $^ > embench.log
CRUFT= $(EMBENCH_BENCHMARKS) $(embench_hw) $(embench_sim) $(embench_logs) embench.log build_taiga_sim
#Called by compliance makefile
.PHONY: verilator_taiga_compliance_unit_test
verilator_taiga_compliance_unit_test: build_taiga_sim
./build_taiga_sim/Vtaiga_local_mem $(LOG_FILE_NAME) $(SIG_FILE_NAME) $(HW_INIT) $(VERILATOR_TRACE_FILE) >> $@
.PHONY: verilator_taiga_compliance_tests
run_compliance_tests_verilator: build_taiga_sim
$(MAKE) -C $(COMPLIANCE_DIR) clean
$(MAKE) -C $(COMPLIANCE_DIR) RISCV_TARGET=taiga RISCV_DEVICE=$(COMPLIANCE_TARGET) RISCV_PREFIX=$(RISCV_PREFIX) TAIGA_ROOT=$(TAIGA_DIR)/tools
.PHONY: run_dhrystone_verilator
run_dhrystone_verilator : build_taiga_sim
./build_taiga_sim/Vtaiga_local_mem "/dev/null" "/dev/null" /home/ematthew/Research/RISCV/software/taiga-benchmarks/dhrystone.riscv.hw_init $(VERILATOR_TRACE_FILE) > $@
clean:
rm -rf $(CRUFT)

97
tools/taiga.mak Normal file
View file

@ -0,0 +1,97 @@
###############################################################
VERILATOR_DIR=$(TAIGA_DIR)/test_benches/verilator
# Sources for verilator
TAIGA_HW_SRCS = $(addprefix $(TAIGA_DIR)/, $(shell cat $(TAIGA_DIR)/tools/taiga_compile_order))
TAIGA_SIM_SRCS = $(addprefix $(VERILATOR_DIR)/, TaigaTracer.cc SimMem.cc taiga_sim.cc AXI_DDR_simulation/axi_ddr_sim.cc AXI_DDR_simulation/ddr_page.cc)
TAIGA_INCLUDED_SIM_SRCS = $(addprefix $(VERILATOR_DIR)/, taiga_sim.cc AXI_DDR_simulation/ddr_page.cc SimMem.cc)
#Tracing: Set to True or False
TRACE_ENABLE?=False
#Simulation Binary Name
TAIGA_SIM_DIR?=$(VERILATOR_DIR)/build
TAIGA_SIM?=$(TAIGA_SIM_DIR)/taiga-sim
#DDR Pre-Initialization
LOAD_DDR_FROM_FILE = False
DDR_FILE = "\"path_to_DDR_init_file\""
DDR_FILE_STARTING_LOCATION = 0
DDR_FILE_NUM_BYTES = 0
#AXI DDR Parameters
DDR_SIZE_GB = 4
PAGE_SIZE_KB = 2
MAX_READ_REQ = 8
MAX_WRITE_REQ = $(MAX_READ_REQ)
MIN_RD_DELAY = 1
MAX_RD_DELAY = 1
MIN_WR_DELAY = 1
MAX_WR_DELAY = 1
DELAY_SEED = 867583
######################################################################
ddr_size_def = DDR_SIZE=\(long\)$(DDR_SIZE_GB)*\(long\)1073741824
page_size_def = PAGE_SIZE=\($(PAGE_SIZE_KB)*1024\)
max_inflight_read_requests = MAX_INFLIGHT_RD_REQ=$(MAX_READ_REQ)
max_inflight_write_requests = MAX_INFLIGHT_WD_REQ=$(MAX_WRITE_REQ)
mix_delay_read = MIN_DELAY_RD=$(MIN_RD_DELAY)
max_delay_read = MAX_DELAY_RD=$(MAX_RD_DELAY)
min_delay_write = MIN_DELAY_WR=$(MIN_WR_DELAY)
max_delay_write = MAX_DELAY_WR=$(MAX_WR_DELAY)
delay_seed = DELAY_SEED=$(DELAY_SEED)
ddr_init_file = DDR_INIT_FILE=$(DDR_FILE)
ddr_start_loc = DDR_FILE_STARTING_LOCATION=$(DDR_FILE_STARTING_LOCATION)
ddr_num_bytes = DDR_FILE_NUM_BYTES=$(DDR_FILE_NUM_BYTES)
CFLAGS = -g0 -O3 -std=c++11 -march=native -D$(ddr_size_def) -D$(page_size_def) -D$(max_inflight_read_requests) -D$(max_inflight_write_requests)\
-D$(mix_delay_read) -D$(max_delay_read) -D$(min_delay_write) -D$(max_delay_write) -D$(delay_seed)\
-D$(ddr_init_file) -D$(ddr_start_loc) -D$(ddr_num_bytes)
#Verilator
################################################################################
VERILATOR_LINT_IGNORE= -Wno-LITENDIAN -Wno-SYMRSVDWORD
ifeq ($(TRACE_ENABLE), True)
VERILATOR_CFLAGS = --trace --trace-structs --CFLAGS "$(CFLAGS) -D TRACE_ON"
else
VERILATOR_CFLAGS = --CFLAGS "$(CFLAGS)"
endif
VERILATOR_LINT_IGNORE= -Wno-LITENDIAN -Wno-SYMRSVDWORD
ifeq ($(LOAD_DDR_FROM_FILE), True)
VERILATOR_CFLAGS := $(VERILATOR_CFLAGS) -D LOAD_DDR_FROM_FILE"
endif
##################################################################################
#taiga_sim included as linter requires top-level to have no interfaces
.PHONY: lint
lint:
verilator -cc $(TAIGA_HW_SRCS) \
$(VERILATOR_DIR)/taiga_sim.sv \
--top-module taiga_sim \
--lint-only
.PHONY: lint-full
lint_full:
verilator -cc $(TAIGA_HW_SRCS) \
$(VERILATOR_DIR)/taiga_sim.sv \
--top-module taiga_sim \
--lint-only -Wall
#Build Taiga Sim
$(TAIGA_SIM): $(TAIGA_HW_SRCS) $(TAIGA_SIM_SRCS)
mkdir -p $(TAIGA_SIM_DIR)
verilator --cc --exe --Mdir $(TAIGA_SIM_DIR) -DENABLE_SIMULATION_ASSERTIONS --assert \
-o taiga-sim \
$(VERILATOR_LINT_IGNORE) $(VERILATOR_CFLAGS) \
$(TAIGA_INCLUDED_SIM_SRCS) \
$(TAIGA_HW_SRCS) $(VERILATOR_DIR)/taiga_sim.sv --top-module taiga_sim
$(MAKE) -C $(TAIGA_SIM_DIR) -f Vtaiga_sim.mk
.PHONY: clean-taiga-sim
clean-taiga-sim:
rm -rf $(TAIGA_SIM_DIR)

138
tools/taiga_compile_order
View file

@ -1,59 +1,59 @@
../core/taiga_config.sv
../core/riscv_types.sv
../core/taiga_types.sv
../l2_arbiter/l2_config_and_types.sv
../l2_arbiter/l2_interfaces.sv
../l2_arbiter/l2_external_interfaces.sv
../local_memory/local_memory_interface.sv
../local_memory/local_mem.sv
core/taiga_config.sv
core/riscv_types.sv
core/taiga_types.sv
l2_arbiter/l2_config_and_types.sv
l2_arbiter/l2_interfaces.sv
l2_arbiter/l2_external_interfaces.sv
local_memory/local_memory_interface.sv
local_memory/local_mem.sv
../core/interfaces.sv
../core/external_interfaces.sv
core/interfaces.sv
core/external_interfaces.sv
../core/csr_types.sv
../core/csr_regs.sv
../core/gc_unit.sv
core/csr_types.sv
core/csr_regs.sv
core/gc_unit.sv
../core/branch_comparator.sv
../core/branch_unit.sv
core/branch_comparator.sv
core/branch_unit.sv
../core/barrel_shifter.sv
../core/alu_unit.sv
core/barrel_shifter.sv
core/alu_unit.sv
../core/axi_master.sv
../core/avalon_master.sv
../core/wishbone_master.sv
core/axi_master.sv
core/avalon_master.sv
core/wishbone_master.sv
../core/axi_to_arb.sv
core/axi_to_arb.sv
../core/one_hot_occupancy.sv
../core/binary_occupancy.sv
../core/taiga_fifo.sv
../core/shift_counter.sv
core/one_hot_occupancy.sv
core/binary_occupancy.sv
core/taiga_fifo.sv
core/shift_counter.sv
../core/set_clr_reg_with_rst.sv
core/set_clr_reg_with_rst.sv
../core/intel/intel_byte_enable_ram.sv
../core/xilinx/xilinx_byte_enable_ram.sv
../core/byte_en_BRAM.sv
core/intel/intel_byte_enable_ram.sv
core/xilinx/xilinx_byte_enable_ram.sv
core/byte_en_BRAM.sv
../core/one_hot_to_integer.sv
core/one_hot_to_integer.sv
../core/cycler.sv
core/cycler.sv
../core/tag_bank.sv
../core/dbram.sv
../core/ddata_bank.sv
../core/dtag_banks.sv
../core/amo_alu.sv
../core/dcache.sv
../core/load_store_queue.sv
../core/load_store_unit.sv
core/tag_bank.sv
core/dbram.sv
core/ddata_bank.sv
core/dtag_banks.sv
core/amo_alu.sv
core/dcache.sv
core/load_store_queue.sv
core/load_store_unit.sv
../core/ibram.sv
../core/itag_banks.sv
../core/icache.sv
core/ibram.sv
core/itag_banks.sv
core/icache.sv
@ -61,43 +61,43 @@
../core/div_algorithms/div_radix2.sv
../core/clz.sv
../core/div_algorithms/div_quick_clz.sv
../core/div_algorithms/div_algorithm.sv
../core/div_unit.sv
core/div_algorithms/div_radix2.sv
core/clz.sv
core/div_algorithms/div_quick_clz.sv
core/div_algorithms/div_algorithm.sv
core/div_unit.sv
../core/lut_ram.sv
../core/tlb_lut_ram.sv
../core/mmu.sv
core/lut_ram.sv
core/tlb_lut_ram.sv
core/mmu.sv
../core/mul_unit.sv
core/mul_unit.sv
../core/l1_arbiter.sv
../core/ras.sv
../core/branch_predictor_ram.sv
../core/branch_predictor.sv
../core/fetch.sv
core/l1_arbiter.sv
core/ras.sv
core/branch_predictor_ram.sv
core/branch_predictor.sv
core/fetch.sv
../core/illegal_instruction_checker.sv
../core/decode_and_issue.sv
core/illegal_instruction_checker.sv
core/decode_and_issue.sv
../core/regfile_bank_sel.sv
../core/register_file.sv
../core/register_file_and_writeback.sv
core/regfile_bank_sel.sv
core/register_file.sv
core/register_file_and_writeback.sv
../core/placer_randomizer.sv
core/placer_randomizer.sv
../l2_arbiter/l2_fifo.sv
../l2_arbiter/l2_reservation_logic.sv
../l2_arbiter/l2_round_robin.sv
../l2_arbiter/l2_arbiter.sv
l2_arbiter/l2_fifo.sv
l2_arbiter/l2_reservation_logic.sv
l2_arbiter/l2_round_robin.sv
l2_arbiter/l2_arbiter.sv
../core/toggle_memory.sv
../core/instruction_metadata_and_id_management.sv
core/toggle_memory.sv
core/instruction_metadata_and_id_management.sv
../core/taiga.sv
core/taiga.sv