mirror of
https://github.com/openhwgroup/cva5.git
synced 2025-04-22 13:07:33 -04:00
parameterized number of read ports on regfile
This commit is contained in:
Eric Matthews
parent
60a463a39f
commit
a287a3bb08
9 changed files with 122 additions and 148 deletions
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@ -36,9 +36,7 @@ module decode_and_issue (
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input logic [31:0] decode_instruction,
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output issue_packet_t issue,
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input logic [31:0] rs1_data,
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input logic [31:0] rs2_data,
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input id_t rs2_id,
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input logic [31:0] rs_data [REGFILE_READ_PORTS],
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output alu_inputs_t alu_inputs,
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output load_store_inputs_t ls_inputs,
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@ -56,10 +54,9 @@ module decode_and_issue (
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output logic gc_flush_required,
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//ID Management
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input logic rs1_inuse,
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input logic rs2_inuse,
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input logic rs1_id_inuse,
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input logic rs2_id_inuse,
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input logic rs_inuse [REGFILE_READ_PORTS],
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input id_t rs_id [REGFILE_READ_PORTS],
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input logic rs_id_inuse [REGFILE_READ_PORTS],
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output logic instruction_issued,
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output logic illegal_instruction,
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@ -159,8 +156,8 @@ module decode_and_issue (
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issue.instruction <= decode_instruction;
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issue.fn3 <= fn3;
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issue.opcode <= opcode;
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issue.rs1_addr <= rs1_addr;
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issue.rs2_addr <= rs2_addr;
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issue.rs_addr[RS1] <= rs1_addr;
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issue.rs_addr[RS2] <= rs2_addr;
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issue.rd_addr <= rd_addr;
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issue.id <= decode_id;
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issue.uses_rs1 <= uses_rs1;
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@ -200,8 +197,8 @@ module decode_and_issue (
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//Issue Determination
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assign issue_valid = issue.stage_valid & ~gc_issue_hold & ~gc_fetch_flush;
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assign rs1_conflict = rs1_inuse & rs1_id_inuse & issue.uses_rs1;
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assign rs2_conflict = rs2_inuse & rs2_id_inuse & issue.uses_rs2;
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assign rs1_conflict = rs_inuse[RS1] & rs_id_inuse[RS1] & issue.uses_rs1;
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assign rs2_conflict = rs_inuse[RS2] & rs_id_inuse[RS2] & issue.uses_rs2;
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assign operands_ready = ~rs1_conflict & ~rs2_conflict;
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@ -295,13 +292,13 @@ module decode_and_issue (
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assign alu_inputs.shifter_path = alu_shifter_path;
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assign alu_inputs.slt_path = alu_slt_path;
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assign alu_rs1_data = rs1_use_regfile ? rs1_data : pre_alu_rs1_r;
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assign alu_rs2_data = rs2_use_regfile ? rs2_data : pre_alu_rs2_r;
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assign alu_rs1_data = rs1_use_regfile ? rs_data[RS1] : pre_alu_rs1_r;
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assign alu_rs2_data = rs2_use_regfile ? rs_data[RS2] : pre_alu_rs2_r;
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assign alu_inputs.in1 = {(rs1_data[XLEN-1] & ~issue.fn3[0]), alu_rs1_data};//(fn3[0] is SLTU_fn3);
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assign alu_inputs.in1 = {(rs_data[RS1][XLEN-1] & ~issue.fn3[0]), alu_rs1_data};//(fn3[0] is SLTU_fn3);
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assign alu_inputs.in2 = {(alu_rs2_data[XLEN-1] & ~issue.fn3[0]), alu_rs2_data};
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assign alu_inputs.shifter_in = rs1_data;
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assign alu_inputs.shift_amount = issue.opcode[5] ? rs2_data[4:0] : issue.rs2_addr;
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assign alu_inputs.shifter_in = rs_data[RS1];
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assign alu_inputs.shift_amount = issue.opcode[5] ? rs_data[RS2][4:0] : issue.rs_addr[RS2];
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assign alu_issued = issue_to[ALU_UNIT_WB_ID];
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@ -348,10 +345,10 @@ module decode_and_issue (
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assign ls_inputs.load = is_load_r;
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assign ls_inputs.store = is_store_r;
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assign ls_inputs.fn3 = amo_op ? LS_W_fn3 : issue.fn3;
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assign ls_inputs.rs1 = rs1_data;
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assign ls_inputs.rs2 = rs2_data;
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assign ls_inputs.rs1 = rs_data[RS1];
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assign ls_inputs.rs2 = rs_data[RS2];
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assign ls_inputs.forwarded_store = 0;//rs2_conflict;
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assign ls_inputs.store_forward_id = rs2_id;
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assign ls_inputs.store_forward_id = rs_id[RS2];
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////////////////////////////////////////////////////
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//Branch unit inputs
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@ -411,8 +408,8 @@ module decode_and_issue (
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assign branch_inputs.issue_pc = issue.pc;
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assign branch_inputs.issue_pc_valid = issue.stage_valid;
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assign branch_inputs.rs1 = rs1_data;
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assign branch_inputs.rs2 = rs2_data;
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assign branch_inputs.rs1 = rs_data[RS1];
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assign branch_inputs.rs2 = rs_data[RS2];
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////////////////////////////////////////////////////
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@ -453,15 +450,15 @@ module decode_and_issue (
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assign gc_inputs.is_fence = is_fence;
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assign gc_inputs.is_i_fence = ENABLE_M_MODE & issue_to[GC_UNIT_ID] & is_ifence_r;
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assign gc_inputs.rs1 = rs1_data;
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assign gc_inputs.rs2 = rs2_data;
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assign gc_inputs.rs1 = rs_data[RS1];
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assign gc_inputs.rs2 = rs_data[RS2];
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assign gc_flush_required = ENABLE_M_MODE && issue_to[GC_UNIT_ID] && potential_flush;
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////////////////////////////////////////////////////
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//Mul unit inputs
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generate if (USE_MUL) begin
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assign mul_inputs.rs1 = rs1_data;
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assign mul_inputs.rs2 = rs2_data;
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assign mul_inputs.rs1 = rs_data[RS1];
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assign mul_inputs.rs2 = rs_data[RS2];
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assign mul_inputs.op = issue.fn3[1:0];
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end endgenerate
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@ -482,11 +479,11 @@ module decode_and_issue (
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end
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end
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assign current_op_resuses_rs1_rs2 = (prev_div_rs1_addr == issue.rs1_addr) && (prev_div_rs2_addr == issue.rs2_addr);
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assign current_op_resuses_rs1_rs2 = (prev_div_rs1_addr == issue.rs_addr[RS1]) && (prev_div_rs2_addr == issue.rs_addr[RS2]);
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assign set_prev_div_result_valid = unit_needed_issue_stage[DIV_UNIT_WB_ID];
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//If current div operation overwrites an input register OR any other instruction overwrites the last div operations input registers
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assign clear_prev_div_result_valid = issue.uses_rd & ((issue.rd_addr == (unit_needed_issue_stage[DIV_UNIT_WB_ID] ? issue.rs1_addr : prev_div_rs1_addr)) || (issue.rd_addr == (unit_needed_issue_stage[DIV_UNIT_WB_ID] ? issue.rs2_addr : prev_div_rs2_addr)));
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assign clear_prev_div_result_valid = issue.uses_rd & ((issue.rd_addr == (unit_needed_issue_stage[DIV_UNIT_WB_ID] ? issue.rs_addr[RS1] : prev_div_rs1_addr)) || (issue.rd_addr == (unit_needed_issue_stage[DIV_UNIT_WB_ID] ? issue.rs_addr[RS2] : prev_div_rs2_addr)));
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set_clr_reg_with_rst #(.SET_OVER_CLR(0), .WIDTH(1), .RST_VALUE(0)) prev_div_result_valid_m (
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.clk, .rst,
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@ -495,8 +492,8 @@ module decode_and_issue (
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.result(prev_div_result_valid)
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);
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assign div_inputs.rs1 = rs1_data;
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assign div_inputs.rs2 = rs2_data;
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assign div_inputs.rs1 = rs_data[RS1];
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assign div_inputs.rs2 = rs_data[RS2];
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assign div_inputs.op = issue.fn3[1:0];
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assign div_inputs.reuse_result = prev_div_result_valid & current_op_resuses_rs1_rs2;
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end endgenerate
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@ -48,10 +48,8 @@ module id_management
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//Issue stage
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input issue_packet_t issue,
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input logic instruction_issued,
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input id_t rs1_id,
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input id_t rs2_id,
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output logic rs1_id_inuse,
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output logic rs2_id_inuse,
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input id_t rs_id[REGFILE_READ_PORTS],
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output logic rs_id_inuse[REGFILE_READ_PORTS],
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//ID freeing
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input logic store_complete,
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@ -81,23 +79,19 @@ module id_management
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logic decoded_issued_status;
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logic issued_status;
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logic issued_status_rs1;
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logic issued_status_rs2;
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logic branch_complete_status;
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logic branch_complete_status_rs1;
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logic branch_complete_status_rs2;
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logic store_complete_status;
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logic store_complete_status_rs1;
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logic store_complete_status_rs2;
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logic system_op_or_exception_complete_status;
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logic exception_with_rd_complete_status_rs1;
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logic exception_with_rd_complete_status_rs2;
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logic [COMMIT_PORTS-1:0] retired_status;
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logic [COMMIT_PORTS-1:0] retired_status_rs1;
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logic [COMMIT_PORTS-1:0] retired_status_rs2;
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logic issued_status_rs [REGFILE_READ_PORTS];
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logic branch_complete_status;
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logic store_complete_status;
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logic system_op_or_exception_complete_status;
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logic exception_with_rd_complete_status_rs [REGFILE_READ_PORTS];
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logic [COMMIT_PORTS-1:0] retired_status;
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logic [COMMIT_PORTS-1:0] retired_status_rs [REGFILE_READ_PORTS];
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logic [$clog2(MAX_COMPLETE_COUNT)-1:0] complete_count;
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genvar i;
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////////////////////////////////////////////////////
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//Implementation
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@ -171,20 +165,15 @@ module id_management
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.read_id(pc_id_i),
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.read_data(issued_status)
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);
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toggle_memory issued_toggle_mem_rs1 (
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.clk, .rst,
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.toggle(instruction_issued & issue.uses_rd),
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.toggle_id(issue.id),
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.read_id(rs1_id),
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.read_data(issued_status_rs1)
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);
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toggle_memory issued_toggle_mem_rs2 (
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.clk, .rst,
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.toggle(instruction_issued & issue.uses_rd),
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.toggle_id(issue.id),
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.read_id(rs2_id),
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.read_data(issued_status_rs2)
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);
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generate for (i = 0; i < REGFILE_READ_PORTS; i++) begin
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toggle_memory issued_toggle_mem_rs (
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.clk, .rst,
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.toggle(instruction_issued & issue.uses_rd),
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.toggle_id(issue.id),
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.read_id(rs_id[i]),
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.read_data(issued_status_rs[i])
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);
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end endgenerate
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toggle_memory branch_toggle_mem (
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.clk, .rst,
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@ -209,22 +198,19 @@ module id_management
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.read_id(pc_id_i),
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.read_data(system_op_or_exception_complete_status)
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);
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toggle_memory exception_complete_toggle_mem_rs1 (
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.clk, .rst,
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.toggle(exception_with_rd_complete),
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.toggle_id(system_op_or_exception_id),
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.read_id(rs1_id),
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.read_data(exception_with_rd_complete_status_rs1)
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);
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toggle_memory xception_complete_toggle_mem_rs2 (
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.clk, .rst,
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.toggle(exception_with_rd_complete),
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.toggle_id(system_op_or_exception_id),
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.read_id(rs2_id),
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.read_data(exception_with_rd_complete_status_rs2)
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);
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generate for (i = 0; i < REGFILE_READ_PORTS; i++) begin
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toggle_memory exception_complete_toggle_mem_rs (
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.clk, .rst,
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.toggle(exception_with_rd_complete),
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.toggle_id(system_op_or_exception_id),
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.read_id(rs_id[i]),
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.read_data(exception_with_rd_complete_status_rs[i])
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);
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end endgenerate
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//One memory per commit port
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genvar i;
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genvar j;
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generate for (i = 0; i < COMMIT_PORTS; i++) begin
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toggle_memory retired_toggle_mem (
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.clk, .rst,
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@ -233,20 +219,15 @@ module id_management
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.read_id(pc_id_i),
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.read_data(retired_status[i])
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);
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toggle_memory retired_toggle_mem_rs1 (
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.clk, .rst,
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.toggle(retired[i]),
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.toggle_id(ids_retiring[i]),
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.read_id(rs1_id),
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.read_data(retired_status_rs1[i])
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);
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toggle_memory retired_toggle_mem_rs2 (
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.clk, .rst,
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.toggle(retired[i]),
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.toggle_id(ids_retiring[i]),
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.read_id(rs2_id),
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.read_data(retired_status_rs2[i])
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);
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for (j = 0; j < REGFILE_READ_PORTS; j++) begin
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toggle_memory retired_toggle_mem_rs (
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.clk, .rst,
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.toggle(retired[i]),
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.toggle_id(ids_retiring[i]),
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.read_id(rs_id[j]),
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.read_data(retired_status_rs[j][i])
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);
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end
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end endgenerate
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//Computed one cycle in advance using pc_id_i
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@ -263,17 +244,15 @@ module id_management
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//rs1/rs2 conflicts don't check branch or store memories as the only
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//IDs stored in the rs to ID table are instructions that write to the register file
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assign rs1_id_inuse = (
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issued_status_rs1 ^
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exception_with_rd_complete_status_rs1 ^
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(^retired_status_rs1)
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);
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assign rs2_id_inuse = (
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issued_status_rs2 ^
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exception_with_rd_complete_status_rs2 ^
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(^retired_status_rs2)
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);
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always_comb begin
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for (int i = 0; i < REGFILE_READ_PORTS; i++) begin
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rs_id_inuse[i] = (
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issued_status_rs[i] ^
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exception_with_rd_complete_status_rs[i] ^
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(^retired_status_rs[i])
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);
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end
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end
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always_ff @ (posedge clk) begin
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if (rst)
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@ -46,10 +46,8 @@ module instruction_metadata
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//Issue stage
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input issue_packet_t issue,
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input logic instruction_issued,
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output id_t rs1_id,
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output id_t rs2_id,
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output logic rs1_inuse,
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output logic rs2_inuse,
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output id_t rs_id [REGFILE_READ_PORTS],
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output logic rs_inuse [REGFILE_READ_PORTS],
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//Branch Predictor
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input branch_metadata_t branch_metadata_if,
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@ -113,16 +111,12 @@ module instruction_metadata
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assign branch_metadata_ex = branch_metadata_table[branch_id];
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//Issue
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logic [4:0] rs1_id_rd_addr;
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logic [4:0] rs2_id_rd_addr;
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assign rs1_id = rd_to_id_table[issue.rs1_addr];
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assign rs2_id = rd_to_id_table[issue.rs2_addr];
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assign rs1_id_rd_addr = instruction_table[rs1_id][11:7];
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assign rs2_id_rd_addr = instruction_table[rs2_id][11:7];
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assign rs1_inuse = (issue.rs1_addr == rs1_id_rd_addr);
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assign rs2_inuse = (issue.rs2_addr == rs2_id_rd_addr);
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always_comb begin
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for (int i = 0; i < REGFILE_READ_PORTS; i++) begin
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rs_id[i] = rd_to_id_table[issue.rs_addr[i]];
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rs_inuse[i] = (issue.rs_addr[i] == instruction_table[rs_id[i]][11:7]);//11:7 is rd_addr
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end
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end
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//Writeback support
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always_comb begin
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@ -24,22 +24,24 @@ module register_file
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import taiga_config::*;
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import riscv_types::*;
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import taiga_types::*;
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#(
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parameter NUM_READ_PORTS = 2
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)
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(
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input logic clk,
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input logic rst,
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//Issue interface
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input issue_packet_t issue,
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//Writeback
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input logic [4:0] rd_addr,
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input logic [31:0] new_data,
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input logic commit,
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output logic [31:0] rs1_data,
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output logic [31:0] rs2_data
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//Issue
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input rs_addr_t [NUM_READ_PORTS-1:0] read_addr,
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output logic [31:0] data [NUM_READ_PORTS]
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);
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logic [31:0] register_file [32];
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genvar i;
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////////////////////////////////////////////////////
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//Implementation
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@ -52,8 +54,10 @@ module register_file
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if (commit)
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register_file[rd_addr] <= new_data;
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end
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assign rs1_data = register_file[issue.rs1_addr];
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assign rs2_data = register_file[issue.rs2_addr];
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always_comb begin
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foreach(read_addr[i])
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data[i] = register_file[read_addr[i]];
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end
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////////////////////////////////////////////////////
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//Assertions
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@ -31,9 +31,7 @@ module register_file_and_writeback
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//Issue interface
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input issue_packet_t issue,
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input logic alu_issued,
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output logic [31:0] rs1_data,
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output logic [31:0] rs2_data,
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output logic [31:0] rs_data [REGFILE_READ_PORTS],
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//ID Metadata
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output id_t ids_retiring [COMMIT_PORTS],
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output logic retired [COMMIT_PORTS],
|
||||
|
|
@ -63,10 +61,11 @@ module register_file_and_writeback
|
|||
logic [XLEN-1:0] unit_rd [NUM_WB_UNITS];
|
||||
//Per-ID muxes for commit buffer
|
||||
logic [$clog2(NUM_WB_UNITS)-1:0] retiring_unit_select [COMMIT_PORTS];
|
||||
logic [31:0] rs1_data_set [COMMIT_PORTS];
|
||||
logic [31:0] rs2_data_set [COMMIT_PORTS];
|
||||
logic [31:0] retiring_data [COMMIT_PORTS];
|
||||
|
||||
typedef logic [31:0] rs_data_set_t [REGFILE_READ_PORTS];
|
||||
rs_data_set_t rs_data_set [COMMIT_PORTS];
|
||||
|
||||
genvar i;
|
||||
////////////////////////////////////////////////////
|
||||
//Implementation
|
||||
|
|
@ -110,14 +109,13 @@ module register_file_and_writeback
|
|||
//Implemented in seperate module as there is not universal tool support for inferring
|
||||
//arrays of memory blocks.
|
||||
generate for (i = 0; i < COMMIT_PORTS; i++) begin
|
||||
register_file register_file_blocks (
|
||||
register_file #(.NUM_READ_PORTS(REGFILE_READ_PORTS)) register_file_blocks (
|
||||
.clk, .rst,
|
||||
.issue,
|
||||
.rd_addr(retired_rd_addr[i]),
|
||||
.new_data(retiring_data[i]),
|
||||
.commit(retired[i] & (|retired_rd_addr[i])),
|
||||
.rs1_data(rs1_data_set[i]),
|
||||
.rs2_data(rs2_data_set[i])
|
||||
.read_addr(issue.rs_addr),
|
||||
.data(rs_data_set[i])
|
||||
);
|
||||
end endgenerate
|
||||
|
||||
|
|
@ -134,7 +132,7 @@ module register_file_and_writeback
|
|||
|
||||
regfile_bank_sel regfile_lvt (
|
||||
.clk, .rst,
|
||||
.rs1_addr(issue.rs1_addr), .rs2_addr(issue.rs2_addr),
|
||||
.rs1_addr(issue.rs_addr[RS1]), .rs2_addr(issue.rs_addr[RS2]),
|
||||
.rs1_sel,
|
||||
.rs2_sel,
|
||||
.rd_addr(retired_rd_addr),
|
||||
|
|
@ -143,8 +141,8 @@ module register_file_and_writeback
|
|||
|
||||
////////////////////////////////////////////////////
|
||||
//Register File Muxing
|
||||
assign rs1_data = rs1_data_set[rs1_sel];
|
||||
assign rs2_data = rs2_data_set[rs2_sel];
|
||||
assign rs_data[RS1] = rs_data_set[rs1_sel][RS1];
|
||||
assign rs_data[RS2] = rs_data_set[rs2_sel][RS2];
|
||||
|
||||
////////////////////////////////////////////////////
|
||||
//End of Implementation
|
||||
|
|
|
|||
|
|
@ -27,6 +27,8 @@ package riscv_types;
|
|||
parameter PAGE_ADDR_W = 12;
|
||||
parameter ECODE_W = 5;
|
||||
|
||||
typedef logic [4:0] rs_addr_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic [6:0] fn7;
|
||||
logic [4:0] rs2_addr;
|
||||
|
|
|
|||
|
|
@ -58,8 +58,8 @@ module taiga (
|
|||
ras_interface ras();
|
||||
|
||||
issue_packet_t issue;
|
||||
logic [31:0] rs1_data;
|
||||
logic [31:0] rs2_data;
|
||||
logic [31:0] rs_data [REGFILE_READ_PORTS];
|
||||
|
||||
|
||||
alu_inputs_t alu_inputs;
|
||||
load_store_inputs_t ls_inputs;
|
||||
|
|
@ -100,12 +100,9 @@ module taiga (
|
|||
logic [31:0] decode_pc;
|
||||
logic [31:0] decode_instruction;
|
||||
//Issue stage
|
||||
id_t rs1_id;
|
||||
id_t rs2_id;
|
||||
logic rs1_inuse;
|
||||
logic rs2_inuse;
|
||||
logic rs1_id_inuse;
|
||||
logic rs2_id_inuse;
|
||||
id_t rs_id [REGFILE_READ_PORTS];
|
||||
logic rs_inuse [REGFILE_READ_PORTS];
|
||||
logic rs_id_inuse [REGFILE_READ_PORTS];
|
||||
//Branch predictor
|
||||
branch_metadata_t branch_metadata_if;
|
||||
branch_metadata_t branch_metadata_ex;
|
||||
|
|
|
|||
|
|
@ -158,18 +158,23 @@ package taiga_config;
|
|||
//Branch Predictor Options
|
||||
parameter USE_BRANCH_PREDICTOR = 1;
|
||||
parameter BRANCH_PREDICTOR_WAYS = 2;
|
||||
parameter BRANCH_TABLE_ENTRIES = 512;//min 512
|
||||
parameter BRANCH_TABLE_ENTRIES = 512; //min 512
|
||||
parameter RAS_DEPTH = 8;
|
||||
|
||||
|
||||
////////////////////////////////////////////////////
|
||||
//ID limit
|
||||
//MAX_IDS restricted to a power of 2
|
||||
parameter MAX_IDS = 64;
|
||||
parameter MAX_IDS = 8; //8 sufficient for rv32im configs
|
||||
|
||||
////////////////////////////////////////////////////
|
||||
//Number of commit ports
|
||||
parameter COMMIT_PORTS = 3;
|
||||
parameter COMMIT_PORTS = 2; //min 2
|
||||
parameter REGFILE_READ_PORTS = 2; //min 2, for RS1 and RS2
|
||||
typedef enum logic {
|
||||
RS1 = 0,
|
||||
RS2 = 1
|
||||
} rs1_index_t;
|
||||
|
||||
////////////////////////////////////////////////////
|
||||
//Trace Options
|
||||
|
|
|
|||
|
|
@ -30,7 +30,6 @@ package taiga_types;
|
|||
localparam LOG2_COMMIT_PORTS = $clog2(COMMIT_PORTS);
|
||||
|
||||
typedef logic[$clog2(MAX_IDS)-1:0] id_t;
|
||||
|
||||
typedef logic[WB_UNITS_WIDTH-1:0] unit_id_t;
|
||||
typedef logic[1:0] branch_predictor_metadata_t;
|
||||
|
||||
|
|
@ -87,8 +86,7 @@ package taiga_types;
|
|||
logic [2:0] fn3;
|
||||
logic [6:0] opcode;
|
||||
|
||||
logic [4:0] rs1_addr;
|
||||
logic [4:0] rs2_addr;
|
||||
rs_addr_t [REGFILE_READ_PORTS-1:0] rs_addr;//packed style instead of unpacked due to tool limitations
|
||||
logic [4:0] rd_addr;
|
||||
|
||||
logic uses_rs1;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue