mirror of
https://github.com/openhwgroup/cva5.git
synced 2025-04-22 13:07:33 -04:00
Split write-back muxes into seperate instances
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
This commit is contained in:
Eric Matthews
parent
ebcddd904a
commit
b275bd9691
2 changed files with 74 additions and 83 deletions
59
core/cva5.sv
59
core/cva5.sv
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@ -83,8 +83,13 @@ module cva5
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//Writeback Port Assignment
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//
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localparam int unsigned NUM_WB_UNITS_GROUP_1 = 1;//ALU
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localparam int unsigned ALU_UNIT_WB1_ID = 32'd0;
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localparam int unsigned NUM_WB_UNITS_GROUP_2 = 1 + int'(CONFIG.INCLUDE_CSRS) + int'(CONFIG.INCLUDE_MUL) + int'(CONFIG.INCLUDE_DIV);//LS
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localparam int unsigned NUM_WB_UNITS = NUM_WB_UNITS_GROUP_1 + NUM_WB_UNITS_GROUP_2;
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localparam int unsigned LS_UNIT_WB2_ID = 32'd0;
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localparam int unsigned CSR_UNIT_WB2_ID = LS_UNIT_WB2_ID + int'(CONFIG.INCLUDE_CSRS);
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localparam int unsigned MUL_UNIT_WB2_ID = CSR_UNIT_WB2_ID + int'(CONFIG.INCLUDE_MUL);
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localparam int unsigned DIV_UNIT_WB2_ID = MUL_UNIT_WB2_ID + int'(CONFIG.INCLUDE_DIV);
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////////////////////////////////////////////////////
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//Connecting Signals
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@ -119,7 +124,8 @@ module cva5
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exception_packet_t ls_exception;
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logic ls_exception_is_store;
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unit_writeback_interface unit_wb [NUM_WB_UNITS]();
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unit_writeback_interface unit_wb1 [NUM_WB_UNITS_GROUP_1]();
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unit_writeback_interface unit_wb2 [NUM_WB_UNITS_GROUP_2]();
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mmu_interface immu();
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mmu_interface dmmu();
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@ -408,7 +414,7 @@ module cva5
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.rst (rst),
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.alu_inputs (alu_inputs),
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.issue (unit_issue[UNIT_IDS.ALU]),
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.wb (unit_wb[UNIT_IDS.ALU])
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.wb (unit_wb1[ALU_UNIT_WB1_ID])
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);
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load_store_unit #(.CONFIG(CONFIG))
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@ -435,7 +441,7 @@ module cva5
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.retire_port_valid(retire_port_valid),
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.exception (exception[LS_EXCEPTION]),
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.load_store_status(load_store_status),
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.wb (unit_wb[UNIT_IDS.LS])
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.wb (unit_wb2[LS_UNIT_WB2_ID])
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);
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generate if (CONFIG.INCLUDE_S_MODE) begin : gen_dtlb_dmmu
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@ -473,7 +479,7 @@ module cva5
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.rst(rst),
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.csr_inputs (csr_inputs),
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.issue (unit_issue[UNIT_IDS.CSR]),
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.wb (unit_wb[UNIT_IDS.CSR]),
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.wb (unit_wb2[CSR_UNIT_WB2_ID]),
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.current_privilege(current_privilege),
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.interrupt_taken(interrupt_taken),
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.interrupt_pending(interrupt_pending),
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@ -525,7 +531,7 @@ module cva5
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.rst (rst),
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.mul_inputs (mul_inputs),
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.issue (unit_issue[UNIT_IDS.MUL]),
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.wb (unit_wb[UNIT_IDS.MUL])
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.wb (unit_wb2[MUL_UNIT_WB2_ID])
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);
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end endgenerate
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@ -535,7 +541,7 @@ module cva5
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.rst (rst),
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.div_inputs (div_inputs),
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.issue (unit_issue[UNIT_IDS.DIV]),
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.wb (unit_wb[UNIT_IDS.DIV])
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.wb (unit_wb2[DIV_UNIT_WB2_ID])
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);
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end endgenerate
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@ -543,19 +549,44 @@ module cva5
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//Writeback
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//First writeback port: ALU
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//Second writeback port: LS, CSR, [MUL], [DIV]
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localparam int unsigned NUM_UNITS_PER_PORT [CONFIG.NUM_WB_GROUPS] = '{NUM_WB_UNITS_GROUP_1, NUM_WB_UNITS_GROUP_2};
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writeback #(
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.CONFIG (CONFIG),
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.NUM_UNITS (NUM_UNITS_PER_PORT),
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.NUM_WB_UNITS (NUM_WB_UNITS)
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.NUM_WB_UNITS (NUM_WB_UNITS_GROUP_1)
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)
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writeback_block (
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writeback_block1 (
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.clk (clk),
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.rst (rst),
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.wb_packet (wb_packet),
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.unit_wb (unit_wb),
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.wb_snoop (wb_snoop)
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.wb_packet (wb_packet[0]),
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.unit_wb (unit_wb1)
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);
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writeback #(
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.CONFIG (CONFIG),
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.NUM_WB_UNITS (NUM_WB_UNITS_GROUP_2)
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)
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writeback_block2 (
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.clk (clk),
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.rst (rst),
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.wb_packet (wb_packet[1]),
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.unit_wb (unit_wb2)
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);
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////////////////////////////////////////////////////
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//Store Forwarding Support
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//TODO: support additional writeback groups
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//currently limited to one writeback group with the
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//assumption that writeback group zero has single-cycle
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//operation
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always_ff @ (posedge clk) begin
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if (rst)
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wb_snoop.valid <= 0;
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else
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wb_snoop.valid <= wb_packet[1].valid;
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end
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always_ff @ (posedge clk) begin
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wb_snoop.data <= wb_packet[1].data;
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wb_snoop.id <= wb_packet[1].id;
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end
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////////////////////////////////////////////////////
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//End of Implementation
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@ -28,7 +28,6 @@ module writeback
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# (
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parameter cpu_config_t CONFIG = EXAMPLE_CONFIG,
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parameter int unsigned NUM_UNITS [CONFIG.NUM_WB_GROUPS] = '{1, 4},
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parameter int unsigned NUM_WB_UNITS = 5
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)
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@ -38,90 +37,51 @@ module writeback
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//Unit writeback
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unit_writeback_interface.wb unit_wb[NUM_WB_UNITS],
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//WB output
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output wb_packet_t wb_packet [CONFIG.NUM_WB_GROUPS],
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//Snoop interface (LS unit)
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output wb_packet_t wb_snoop
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output wb_packet_t wb_packet
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);
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//Writeback
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logic [NUM_WB_UNITS-1:0] unit_ack [CONFIG.NUM_WB_GROUPS];
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logic [NUM_WB_UNITS-1:0] unit_ack;
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//aliases for write-back-interface signals
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id_t [NUM_WB_UNITS-1:0] unit_instruction_id [CONFIG.NUM_WB_GROUPS];
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phys_addr_t [NUM_WB_UNITS-1:0] unit_phys_addr [CONFIG.NUM_WB_GROUPS];
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logic [NUM_WB_UNITS-1:0] unit_done [CONFIG.NUM_WB_GROUPS];
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id_t [NUM_WB_UNITS-1:0] unit_instruction_id;
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phys_addr_t [NUM_WB_UNITS-1:0] unit_phys_addr;
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logic [NUM_WB_UNITS-1:0] unit_done;
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typedef logic [XLEN-1:0] unit_rd_t [NUM_WB_UNITS];
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unit_rd_t unit_rd [CONFIG.NUM_WB_GROUPS];
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logic [XLEN-1:0] unit_rd [NUM_WB_UNITS];
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localparam int unsigned LOG2_NUM_WB_UNITS = NUM_WB_UNITS == 1 ? 1 : $clog2(NUM_WB_UNITS);
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//Per-ID muxes for commit buffer
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logic [$clog2(NUM_WB_UNITS)-1:0] unit_sel [CONFIG.NUM_WB_GROUPS];
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logic [LOG2_NUM_WB_UNITS-1:0] unit_sel;
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typedef int unsigned unit_count_t [CONFIG.NUM_WB_GROUPS];
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function unit_count_t get_cumulative_unit_count();
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unit_count_t counts;
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int unsigned cumulative_count = 0;
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for (int i = 0; i < CONFIG.NUM_WB_GROUPS; i++) begin
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counts[i] = cumulative_count;
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cumulative_count += NUM_UNITS[i];
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end
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return counts;
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endfunction
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localparam unit_count_t CUMULATIVE_NUM_UNITS = get_cumulative_unit_count();
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genvar i, j;
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genvar i;
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////////////////////////////////////////////////////
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//Implementation
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//Re-assigning interface inputs to array types so that they can be dynamically indexed
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generate
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for (i = 0; i < CONFIG.NUM_WB_GROUPS; i++) begin : gen_wb_group_unpacking
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for (j = 0; j < NUM_UNITS[i]; j++) begin : gen_wb_unit_unpacking
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assign unit_instruction_id[i][j] = unit_wb[CUMULATIVE_NUM_UNITS[i] + j].id;
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assign unit_phys_addr[i][j] = unit_wb[CUMULATIVE_NUM_UNITS[i] + j].phys_addr;
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assign unit_done[i][j] = unit_wb[CUMULATIVE_NUM_UNITS[i] + j].done;
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assign unit_wb[CUMULATIVE_NUM_UNITS[i] + j].ack = unit_ack[i][j];
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assign unit_rd[i][j] = unit_wb[CUMULATIVE_NUM_UNITS[i] + j].rd;
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end
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end
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endgenerate
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generate for (i = 0; i < NUM_WB_UNITS; i++) begin : gen_wb_unit_unpacking
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assign unit_instruction_id[i] = unit_wb[i].id;
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assign unit_phys_addr[i] = unit_wb[i].phys_addr;
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assign unit_done[i] = unit_wb[i].done;
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assign unit_wb[i].ack = unit_ack[i];
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assign unit_rd[i] = unit_wb[i].rd;
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end endgenerate
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////////////////////////////////////////////////////
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//Unit select for register file
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//Iterating through all commit ports:
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// Search for complete units (in fixed unit order)
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// Assign to a commit port, mask that unit and commit port
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generate for (i = 0; i < CONFIG.NUM_WB_GROUPS; i++) begin : gen_wb_mux
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priority_encoder
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#(.WIDTH(NUM_UNITS[i]))
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unit_done_encoder
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(
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.priority_vector (unit_done[i][NUM_UNITS[i]-1 : 0]),
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.encoded_result (unit_sel[i][NUM_UNITS[i] == 1 ? 0 : ($clog2(NUM_UNITS[i])-1) : 0])
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);
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assign wb_packet[i].valid = |unit_done[i];
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assign wb_packet [i].id = unit_instruction_id[i][unit_sel[i]];
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assign wb_packet [i].phys_addr = unit_phys_addr[i][unit_sel[i]];
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assign wb_packet[i].data = unit_rd[i][unit_sel[i]];
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priority_encoder #(.WIDTH(NUM_WB_UNITS))
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unit_done_encoder
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(
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.priority_vector (unit_done),
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.encoded_result (unit_sel[LOG2_NUM_WB_UNITS -1 : 0])
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);
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assign wb_packet.valid = |unit_done;
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assign wb_packet.id = unit_instruction_id[unit_sel];
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assign wb_packet.phys_addr = unit_phys_addr[unit_sel];
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assign wb_packet.data = unit_rd[unit_sel];
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assign unit_ack[i] = NUM_WB_UNITS'(wb_packet[i].valid) << unit_sel[i];
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end endgenerate
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////////////////////////////////////////////////////
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//Store Forwarding Support
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//TODO: support additional writeback groups
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//currently limited to one writeback group with the
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//assumption that writeback group zero has single-cycle
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//operation
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always_ff @ (posedge clk) begin
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if (rst)
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wb_snoop.valid <= 0;
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else
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wb_snoop.valid <= wb_packet[1].valid;
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end
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always_ff @ (posedge clk) begin
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wb_snoop.data <= wb_packet[1].data;
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wb_snoop.id <= wb_packet[1].id;
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end
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assign unit_ack = NUM_WB_UNITS'(wb_packet.valid) << unit_sel;
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////////////////////////////////////////////////////
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//End of Implementation
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@ -130,4 +90,4 @@ module writeback
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////////////////////////////////////////////////////
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//Assertions
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endmodule
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endmodule
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