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https://github.com/openhwgroup/cva5.git
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Added LiteX support
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
This commit is contained in:
Eric Matthews
parent
2290527612
commit
b2e425abed
3 changed files with 473 additions and 1 deletions
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@ -42,7 +42,7 @@ module wishbone_master
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always_ff @ (posedge clk) begin
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if (ls.new_request) begin
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wishbone.adr <= ls.addr[29:0];
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wishbone.adr <= ls.addr[31:2];
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wishbone.sel <= ls.we ? ls.be : '1;
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wishbone.we <= ls.we;
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wishbone.dat_w <= ls.data_in;
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120
examples/litex/l1_to_wishbone.sv
Normal file
120
examples/litex/l1_to_wishbone.sv
Normal file
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@ -0,0 +1,120 @@
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/*
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* Copyright © 2022 Eric Matthews, Lesley Shannon
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* Initial code developed under the supervision of Dr. Lesley Shannon,
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* Reconfigurable Computing Lab, Simon Fraser University.
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*
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* Author(s):
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* Eric Matthews <ematthew@sfu.ca>
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*/
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module l1_to_wishbone
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import cva5_config::*;
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import riscv_types::*;
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import cva5_types::*;
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import l2_config_and_types::*;
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(
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input logic clk,
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input logic rst,
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l2_requester_interface.slave cpu,
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wishbone_interface.master wishbone
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);
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localparam MAX_REQUESTS = 32;
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fifo_interface #(.DATA_WIDTH($bits(l2_request_t))) request_fifo ();
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fifo_interface #(.DATA_WIDTH(32)) data_fifo ();
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l2_request_t request_in;
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l2_request_t request;
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logic request_complete;
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////////////////////////////////////////////////////
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//Implementation
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assign cpu.request_full = request_fifo.full;
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assign cpu.data_full = data_fifo.full;
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//Repack input attributes
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assign request_in.addr = cpu.addr;
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assign request_in.be = cpu.be;
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assign request_in.rnw = cpu.rnw;
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assign request_in.is_amo = cpu.is_amo;
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assign request_in.amo_type_or_burst_size = cpu.amo_type_or_burst_size;
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assign request_in.sub_id = cpu.sub_id;
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assign request_fifo.push = cpu.request_push;
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assign request_fifo.potential_push = cpu.request_push;
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assign request_fifo.pop = request_complete;
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assign request_fifo.data_in = request_in;
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assign request = request_fifo.data_out;
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assign data_fifo.push = cpu.wr_data_push;
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assign data_fifo.potential_push = cpu.wr_data_push;
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assign data_fifo.pop = wishbone.we & wishbone.ack;
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assign data_fifo.data_in = cpu.wr_data;
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cva5_fifo #(.DATA_WIDTH($bits(l2_request_t)), .FIFO_DEPTH(MAX_REQUESTS))
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request_fifo_block (
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.clk (clk),
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.rst (rst),
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.fifo (request_fifo)
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);
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cva5_fifo #(.DATA_WIDTH(32), .FIFO_DEPTH(MAX_REQUESTS))
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data_fifo_block (
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.clk (clk),
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.rst (rst),
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.fifo (data_fifo)
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);
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////////////////////////////////////////////////////
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//Wishbone
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logic [4:0] burst_size;
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logic [4:0] burst_count;
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assign wishbone.cti = 0;
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assign wishbone.bte = 0;
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always_ff @ (posedge clk) begin
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if (rst | request_fifo.pop)
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burst_count <= 0;
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else
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burst_count <= burst_count + 5'(wishbone.ack);
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end
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assign burst_size = request.amo_type_or_burst_size;
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assign request_complete = wishbone.ack & (burst_count == burst_size);
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assign wishbone.adr[29:5] = request.addr[29:5];
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assign wishbone.adr[4:0] = (request.addr[4:0] & ~burst_size) | (burst_count & burst_size);
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assign wishbone.sel = request.rnw ? '1 : request.be;
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assign wishbone.we = ~request.rnw;
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assign wishbone.dat_w = data_fifo.data_out;
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assign wishbone.stb = request_fifo.valid;
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assign wishbone.cyc = request_fifo.valid;
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////////////////////////////////////////////////////
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//Return Path
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//L1 always acks data, no need for rd_data_ack
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always_ff @ (posedge clk) begin
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cpu.rd_data <= wishbone.dat_r;
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cpu.rd_data_valid <= request.rnw & wishbone.ack;
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cpu.rd_sub_id <= request.sub_id;
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end
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endmodule
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352
examples/litex/litex_wrapper.sv
Executable file
352
examples/litex/litex_wrapper.sv
Executable file
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@ -0,0 +1,352 @@
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/*
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* Copyright © 2022 Eric Matthews, Lesley Shannon
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* Initial code developed under the supervision of Dr. Lesley Shannon,
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* Reconfigurable Computing Lab, Simon Fraser University.
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*
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* Author(s):
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* Eric Matthews <ematthew@sfu.ca>
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*/
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module litex_wrapper
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import cva5_config::*;
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import cva5_types::*;
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import l2_config_and_types::*;
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#(
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parameter LITEX_VARIANT = 0,
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parameter bit [31:0] RESET_VEC = 0,
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parameter bit [31:0] NON_CACHABLE_L = 32'h80000000,
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parameter bit [31:0] NON_CACHABLE_H =32'hFFFFFFFF
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)
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(
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input logic clk,
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input logic rst,
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input logic [15:0] litex_interrupt,
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output logic [29:0] ibus_adr,
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output logic [31:0] ibus_dat_w,
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output logic [3:0] ibus_sel,
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output logic ibus_cyc,
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output logic ibus_stb,
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output logic ibus_we,
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output logic ibus_cti,
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output logic ibus_bte,
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input logic [31:0] ibus_dat_r,
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input logic ibus_ack,
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input logic ibus_err,
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output logic [29:0] dbus_adr,
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output logic [31:0] dbus_dat_w,
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output logic [3:0] dbus_sel,
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output logic dbus_cyc,
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output logic dbus_stb,
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output logic dbus_we,
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output logic dbus_cti,
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output logic dbus_bte,
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input logic [31:0] dbus_dat_r,
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input logic dbus_ack,
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input logic dbus_err,
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output logic [29:0] idbus_adr,
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output logic [31:0] idbus_dat_w,
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output logic [3:0] idbus_sel,
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output logic idbus_cyc,
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output logic idbus_stb,
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output logic idbus_we,
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output logic idbus_cti,
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output logic idbus_bte,
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input logic [31:0] idbus_dat_r,
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input logic idbus_ack,
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input logic idbus_err
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);
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localparam cpu_config_t MINIMAL_CONFIG = '{
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//ISA options
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INCLUDE_M_MODE : 0,
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INCLUDE_S_MODE : 0,
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INCLUDE_U_MODE : 0,
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INCLUDE_MUL : 0,
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INCLUDE_DIV : 0,
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INCLUDE_IFENCE : 0,
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INCLUDE_CSRS : 0,
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INCLUDE_AMO : 0,
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//CSR constants
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CSRS : '{
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MACHINE_IMPLEMENTATION_ID : 0,
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CPU_ID : 0,
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RESET_VEC : RESET_VEC,
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RESET_MTVEC : 32'h00000000,
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NON_STANDARD_OPTIONS : '{
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COUNTER_W : 33,
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MCYCLE_WRITEABLE : 0,
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MINSTR_WRITEABLE : 0,
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MTVEC_WRITEABLE : 0,
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INCLUDE_MSCRATCH : 0,
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INCLUDE_MCAUSE : 0,
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INCLUDE_MTVAL : 0
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}
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},
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//Memory Options
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SQ_DEPTH : 2,
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INCLUDE_ICACHE : 0,
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ICACHE_ADDR : '{
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L: 32'h40000000,
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H: 32'h4FFFFFFF
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},
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ICACHE : '{
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LINES : 512,
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LINE_W : 4,
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WAYS : 2,
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USE_EXTERNAL_INVALIDATIONS : 0,
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USE_NON_CACHEABLE : 0,
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NON_CACHEABLE : '{
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L: 32'h00000000,
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H: 32'h00000000
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}
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},
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ITLB : '{
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WAYS : 2,
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DEPTH : 64
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},
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INCLUDE_DCACHE : 0,
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DCACHE_ADDR : '{
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L: 32'h40000000,
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H: 32'h4FFFFFFF
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},
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DCACHE : '{
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LINES : 512,
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LINE_W : 4,
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WAYS : 2,
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USE_EXTERNAL_INVALIDATIONS : 0,
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USE_NON_CACHEABLE : 0,
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NON_CACHEABLE : '{
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L: 32'h00000000,
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H: 32'h00000000
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}
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},
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DTLB : '{
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WAYS : 2,
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DEPTH : 64
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},
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INCLUDE_ILOCAL_MEM : 0,
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ILOCAL_MEM_ADDR : '{
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L : 32'h80000000,
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H : 32'h8FFFFFFF
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},
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INCLUDE_DLOCAL_MEM : 0,
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DLOCAL_MEM_ADDR : '{
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L : 32'h80000000,
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H : 32'h8FFFFFFF
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},
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INCLUDE_IBUS : 1,
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IBUS_ADDR : '{
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L : 32'h00000000,
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H : 32'hFFFFFFFF
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},
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INCLUDE_PERIPHERAL_BUS : 1,
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PERIPHERAL_BUS_ADDR : '{
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L : 32'h00000000,
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H : 32'hFFFFFFFF
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},
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PERIPHERAL_BUS_TYPE : WISHBONE_BUS,
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//Branch Predictor Options
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INCLUDE_BRANCH_PREDICTOR : 0,
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BP : '{
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WAYS : 2,
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ENTRIES : 512,
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RAS_ENTRIES : 8
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},
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//Writeback Options
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NUM_WB_GROUPS : 2
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};
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localparam cpu_config_t STANDARD_CONFIG = '{
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//ISA options
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INCLUDE_M_MODE : 1,
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INCLUDE_S_MODE : 0,
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INCLUDE_U_MODE : 0,
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INCLUDE_MUL : 1,
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INCLUDE_DIV : 1,
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INCLUDE_IFENCE : 0,
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INCLUDE_CSRS : 1,
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INCLUDE_AMO : 0,
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//CSR constants
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CSRS : '{
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MACHINE_IMPLEMENTATION_ID : 0,
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CPU_ID : 0,
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RESET_VEC : RESET_VEC,
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RESET_MTVEC : 32'h00000000,
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NON_STANDARD_OPTIONS : '{
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COUNTER_W : 33,
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MCYCLE_WRITEABLE : 0,
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MINSTR_WRITEABLE : 0,
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MTVEC_WRITEABLE : 1,
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INCLUDE_MSCRATCH : 0,
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INCLUDE_MCAUSE : 1,
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INCLUDE_MTVAL : 1
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}
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},
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//Memory Options
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SQ_DEPTH : 4,
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INCLUDE_ICACHE : 1,
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ICACHE_ADDR : '{
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L : 32'h00000000,
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H : 32'hFFFFFFFF
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},
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ICACHE : '{
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LINES : 512,
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LINE_W : 4,
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WAYS : 2,
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USE_EXTERNAL_INVALIDATIONS : 0,
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USE_NON_CACHEABLE : 0,
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NON_CACHEABLE : '{
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L: NON_CACHABLE_L,
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H: NON_CACHABLE_H
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}
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},
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ITLB : '{
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WAYS : 2,
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DEPTH : 64
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},
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INCLUDE_DCACHE : 1,
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DCACHE_ADDR : '{
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L : 32'h00000000,
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H : 32'hFFFFFFFF
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},
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DCACHE : '{
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LINES : 512,
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LINE_W : 4,
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WAYS : 2,
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USE_EXTERNAL_INVALIDATIONS : 0,
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USE_NON_CACHEABLE : 1,
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NON_CACHEABLE : '{
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L: NON_CACHABLE_L,
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H: NON_CACHABLE_H
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}
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},
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DTLB : '{
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WAYS : 2,
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DEPTH : 64
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},
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INCLUDE_ILOCAL_MEM : 0,
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ILOCAL_MEM_ADDR : '{
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L : 32'h80000000,
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H : 32'h8FFFFFFF
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},
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INCLUDE_DLOCAL_MEM : 0,
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DLOCAL_MEM_ADDR : '{
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L : 32'h80000000,
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H : 32'h8FFFFFFF
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},
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INCLUDE_IBUS : 0,
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IBUS_ADDR : '{
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L : 32'h00000000,
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H : 32'hFFFFFFFF
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},
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INCLUDE_PERIPHERAL_BUS : 0,
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PERIPHERAL_BUS_ADDR : '{
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L : 32'h00000000,
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H : 32'hFFFFFFFF
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},
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PERIPHERAL_BUS_TYPE : WISHBONE_BUS,
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//Branch Predictor Options
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INCLUDE_BRANCH_PREDICTOR : 1,
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BP : '{
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WAYS : 2,
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ENTRIES : 512,
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RAS_ENTRIES : 8
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},
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//Writeback Options
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NUM_WB_GROUPS : 2
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};
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function cpu_config_t config_select (input integer variant);
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case (variant)
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0 : config_select = MINIMAL_CONFIG;
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1 : config_select = STANDARD_CONFIG;
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default : config_select = STANDARD_CONFIG;
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endcase
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endfunction
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localparam cpu_config_t LITEX_CONFIG = config_select(LITEX_VARIANT);
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//Unused interfaces
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axi_interface m_axi();
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avalon_interface m_avalon();
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local_memory_interface instruction_bram();
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local_memory_interface data_bram();
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trace_outputs_t tr;
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interrupt_t s_interrupt;
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//L2 to Wishbone
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l2_requester_interface l2();
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//Wishbone interfaces
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wishbone_interface dwishbone();
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wishbone_interface iwishbone();
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wishbone_interface idwishbone();
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//Timer and External interrupts
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interrupt_t m_interrupt;
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assign m_interrupt.software = 0;
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assign m_interrupt.timer = litex_interrupt[1];
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assign m_interrupt.external = litex_interrupt[0];
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cva5 #(.CONFIG(LITEX_CONFIG)) cpu(.*);
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generate if (LITEX_VARIANT != 0) begin : l1_arb_gen
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l1_to_wishbone arb(.*, .cpu(l2), .wishbone(idwishbone));
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assign idbus_adr = idwishbone.adr;
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assign idbus_dat_w = idwishbone.dat_w;
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assign idbus_sel = idwishbone.sel;
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assign idbus_cyc = idwishbone.cyc;
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assign idbus_stb = idwishbone.stb;
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assign idbus_we = idwishbone.we;
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assign idbus_cti = idwishbone.cti;
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assign idbus_bte = idwishbone.bte;
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assign idwishbone.dat_r = idbus_dat_r;
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assign idwishbone.ack = idbus_ack;
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assign idwishbone.err = idbus_err;
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end else begin
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assign ibus_adr = iwishbone.adr;
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assign ibus_dat_w = iwishbone.dat_w;
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assign ibus_sel = iwishbone.sel;
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assign ibus_cyc = iwishbone.cyc;
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assign ibus_stb = iwishbone.stb;
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assign ibus_we = iwishbone.we;
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assign ibus_cti = iwishbone.cti;
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assign ibus_bte = iwishbone.bte;
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assign iwishbone.dat_r = ibus_dat_r;
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assign iwishbone.ack = ibus_ack;
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assign iwishbone.err = ibus_err;
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assign dbus_adr = dwishbone.adr;
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assign dbus_dat_w = dwishbone.dat_w;
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assign dbus_sel = dwishbone.sel;
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assign dbus_cyc = dwishbone.cyc;
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assign dbus_stb = dwishbone.stb;
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assign dbus_we = dwishbone.we;
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assign dbus_cti = dwishbone.cti;
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||||
assign dbus_bte = dwishbone.bte;
|
||||
assign dwishbone.dat_r = dbus_dat_r;
|
||||
assign dwishbone.ack = dbus_ack;
|
||||
assign dwishbone.err = dbus_err;
|
||||
end endgenerate
|
||||
|
||||
|
||||
endmodule
|
||||
Loading…
Add table
Add a link
Reference in a new issue