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branch fix and conversion to writeback id bank
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e3ee58c74f
commit
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1 changed files with 11 additions and 24 deletions
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@ -82,6 +82,8 @@ module branch_unit(
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logic is_call;
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logic is_return;
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logic [31:0] rd_bank [MAX_INFLIGHT_COUNT-1:0];
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instruction_id_t id;
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//implementation
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////////////////////////////////////////////////////
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@ -166,35 +168,23 @@ module branch_unit(
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assign ras.push = is_call;
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assign ras.pop = is_return;
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assign ras.new_addr = rd_ex;
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assign ras.new_addr = njump_pc;
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end
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endgenerate
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//WB Output
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////////////////////////////////////////////////////
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//if the destination reg is zero, the result is not "written back" to the register file.
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//Output bank
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assign new_jal_jalr_dec_with_rd = branch_ex.new_request_dec & branch_inputs.uses_rd;
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always_ff @(posedge clk) begin
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if (branch_ex.possible_issue & branch_inputs.uses_rd) begin
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rd_ex <= pc_plus_4;
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end
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end
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always_ff @ (posedge clk) begin
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if (new_jal_jalr_dec_with_rd)
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rd_bank[branch_ex.instruction_id] <= pc_plus_4;
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end
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assign branch_ex.ready = ~done | (done & branch_wb.accepted);
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assign branch_wb.rd = rd_ex;
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assign branch_ex.ready = 1;
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assign branch_wb.rd = rd_bank[branch_wb.writeback_instruction_id];
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always_ff @(posedge clk) begin
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if (rst) begin
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done <= 0;
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end else if (branch_ex.new_request_dec & branch_inputs.uses_rd) begin
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done <= 1;
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end else if (branch_wb.accepted) begin
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done <= 0;
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end
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end
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assign branch_wb.done_next_cycle = branch_ex.new_request_dec & branch_inputs.uses_rd;
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assign branch_wb.done_next_cycle = new_jal_jalr_dec_with_rd;
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assign branch_wb.instruction_id = branch_ex.instruction_id;
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////////////////////////////////////////////////////
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@ -203,9 +193,6 @@ module branch_unit(
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////////////////////////////////////////////////////
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//Assertions
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always_ff @ (posedge clk) begin
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assert (~branch_wb.accepted | (branch_wb.accepted & done)) else $error("Spurious ack for Branch Unit");
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end
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////////////////////////////////////////////////////
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//Trace Interface
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