github-mirrors/cva5
1
0
Fork 0
mirror of https://github.com/openhwgroup/cva5.git synced 2025-04-20 03:57:18 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

cleanup naming of retire signals

Browse source 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
This commit is contained in:
Eric Matthews 2023-02-25 14:58:07 -05:00
parent a2b7400b80
commit b8ee58c515
10 changed files with 39 additions and 35 deletions
Download patch file Download diff file Expand all files Collapse all files

5
core/csr_unit.sv
View file

@ -76,8 +76,9 @@ module csr_unit
output logic [31:0] epc,
//Retire
input retire_packet_t retire,
input retire_packet_t wb_retire,
input id_t retire_ids [RETIRE_PORTS],
input logic [LOG2_RETIRE_PORTS : 0] retire_count,
//External
input interrupt_t s_interrupt,
@ -681,7 +682,7 @@ endgenerate
minst_ret_input_next[CONFIG.CSRS.NON_STANDARD_OPTIONS.COUNTER_W-1:32] = updated_csr[CONFIG.CSRS.NON_STANDARD_OPTIONS.COUNTER_W-33:0];
end
assign minst_ret_inc = {(LOG2_RETIRE_PORTS+1){~(CONFIG.CSRS.NON_STANDARD_OPTIONS.MINSTR_WRITEABLE & (mwrite_en(MINSTRET) | mwrite_en(MINSTRETH)))}} & retire.count;
assign minst_ret_inc = {(LOG2_RETIRE_PORTS+1){~(CONFIG.CSRS.NON_STANDARD_OPTIONS.MINSTR_WRITEABLE & (mwrite_en(MINSTRET) | mwrite_en(MINSTRETH)))}} & retire_count;
always_ff @(posedge clk) begin
if (rst)

13
core/cva5.sv
View file

@ -163,11 +163,12 @@ module cva5
logic [$clog2(CONFIG.NUM_WB_GROUPS)-1:0] decode_rs_wb_group [REGFILE_READ_PORTS];
//ID freeing
retire_packet_t retire;
retire_packet_t wb_retire;
retire_packet_t store_retire;
id_t retire_ids [RETIRE_PORTS];
id_t retire_ids_next [RETIRE_PORTS];
logic retire_port_valid [RETIRE_PORTS];
logic [LOG2_RETIRE_PORTS : 0] retire_count;
//Writeback
wb_packet_t wb_packet [CONFIG.NUM_WB_GROUPS];
phys_addr_t wb_phys_addr [CONFIG.NUM_WB_GROUPS];
@ -251,11 +252,12 @@ module cva5
.instruction_issued_with_rd (instruction_issued_with_rd),
.wb_packet (wb_packet),
.wb_phys_addr (wb_phys_addr),
.retire (retire),
.wb_retire (wb_retire),
.store_retire (store_retire),
.retire_ids (retire_ids),
.retire_ids_next (retire_ids_next),
.retire_port_valid(retire_port_valid),
.retire_count (retire_count),
.post_issue_count(post_issue_count),
.oldest_pc (oldest_pc),
.current_exception_unit (current_exception_unit)
@ -349,7 +351,7 @@ module cva5
.decode (decode_rename_interface),
.issue (issue), //packet
.instruction_issued_with_rd (instruction_issued_with_rd),
.retire (retire) //packet
.wb_retire (wb_retire)
);
////////////////////////////////////////////////////
@ -538,8 +540,9 @@ module cva5
.mret(mret),
.sret(sret),
.epc(epc),
.retire(retire),
.wb_retire (wb_retire),
.retire_ids(retire_ids),
.retire_count (retire_count),
.s_interrupt(s_interrupt),
.m_interrupt(m_interrupt)
);
@ -567,7 +570,7 @@ module cva5
.mret(mret),
.sret(sret),
.epc(epc),
.retire (retire),
.wb_retire (wb_retire),
.retire_ids (retire_ids),
.retire_ids_next (retire_ids_next),
.interrupt_taken(interrupt_taken),

3
core/cva5_types.sv
View file

@ -133,9 +133,8 @@ package cva5_types;
} wb_packet_t;
typedef struct packed{
id_t id;
logic valid;
id_t phys_id;
logic [LOG2_RETIRE_PORTS : 0] count;
} retire_packet_t;
typedef struct packed {

2
core/gc_unit.sv
View file

@ -64,7 +64,7 @@ module gc_unit
input logic [31:0] epc,
//Retire
input retire_packet_t retire,
input retire_packet_t wb_retire,
input id_t retire_ids [RETIRE_PORTS],
input id_t retire_ids_next [RETIRE_PORTS],
input logic [$clog2(NUM_EXCEPTION_SOURCES)-1:0] current_exception_unit,

29
core/instruction_metadata_and_id_management.sv
View file

@ -67,11 +67,12 @@ module instruction_metadata_and_id_management
output phys_addr_t wb_phys_addr [CONFIG.NUM_WB_GROUPS],
//Retirer
output retire_packet_t retire,
output retire_packet_t wb_retire,
output retire_packet_t store_retire,
output id_t retire_ids [RETIRE_PORTS],
output id_t retire_ids_next [RETIRE_PORTS],
output logic retire_port_valid [RETIRE_PORTS],
output logic [LOG2_RETIRE_PORTS : 0] retire_count,
//CSR
output logic [LOG2_MAX_IDS:0] post_issue_count,
@ -103,11 +104,11 @@ module instruction_metadata_and_id_management
logic [LOG2_MAX_IDS:0] post_issue_count_next;
logic [LOG2_MAX_IDS:0] inflight_count;
retire_packet_t retire_next;
retire_packet_t wb_retire_next;
retire_packet_t store_retire_next;
logic retire_port_valid_next [RETIRE_PORTS];
logic [LOG2_RETIRE_PORTS : 0] retire_count_next;
genvar i;
////////////////////////////////////////////////////
//Implementation
@ -202,7 +203,7 @@ module instruction_metadata_and_id_management
if (rst)
retire_ids_next[i] <= LOG2_MAX_IDS'(i);
else
retire_ids_next[i] <= retire_ids_next[i] + LOG2_MAX_IDS'(retire_next.count);
retire_ids_next[i] <= retire_ids_next[i] + LOG2_MAX_IDS'(retire_count_next);
end
always_ff @ (posedge clk) begin
@ -230,7 +231,7 @@ module instruction_metadata_and_id_management
pre_issue_count <= pre_issue_count_next;
end
assign post_issue_count_next = post_issue_count + ID_COUNTER_W'(instruction_issued) - ID_COUNTER_W'(retire_next.count);
assign post_issue_count_next = post_issue_count + ID_COUNTER_W'(instruction_issued) - ID_COUNTER_W'(retire_count_next);
always_ff @ (posedge clk) begin
if (rst)
post_issue_count <= 0;
@ -334,20 +335,21 @@ module instruction_metadata_and_id_management
.encoded_result (retire_with_rd_sel)
);
assign retire_next.phys_id = retire_ids_next[retire_with_rd_sel];
assign retire_next.valid = retire_with_rd_found;
assign wb_retire_next.id = retire_ids_next[retire_with_rd_sel];
assign wb_retire_next.valid = retire_with_rd_found;
always_comb begin
retire_next.count = 0;
retire_count_next = 0;
for (int i = 0; i < RETIRE_PORTS; i++) begin
retire_next.count += retire_port_valid_next[i];
retire_count_next += retire_port_valid_next[i];
end
end
always_ff @ (posedge clk) begin
retire.valid <= retire_next.valid;
retire.phys_id <= retire_next.phys_id;
retire.count <= gc.writeback_supress ? '0 : retire_next.count;
wb_retire.valid <= wb_retire_next.valid;
wb_retire.id <= wb_retire_next.id;
retire_count <= gc.writeback_supress ? '0 : retire_count_next;
for (int i = 0; i < RETIRE_PORTS; i++)
retire_port_valid[i] <= retire_port_valid_next[i] & ~gc.writeback_supress;
end
@ -358,9 +360,8 @@ module instruction_metadata_and_id_management
.encoded_result (retire_with_store_sel)
);
assign store_retire_next.phys_id = retire_ids_next[retire_with_store_sel];
assign store_retire_next.id = retire_ids_next[retire_with_store_sel];
assign store_retire_next.valid = retire_with_store_found;
assign store_retire_next.count = 1;
always_ff @ (posedge clk) begin
store_retire <= store_retire_next;

10
core/renamer.sv
View file

@ -44,7 +44,7 @@ module renamer
input logic instruction_issued_with_rd,
//Retire response
input retire_packet_t retire
input retire_packet_t wb_retire
);
//////////////////////////////////////////
typedef struct packed{
@ -91,7 +91,7 @@ module renamer
);
//During post reset init, initialize FIFO with free list (registers 32-63)
assign free_list.potential_push = (gc.init_clear & ~clear_index[5]) | (retire.valid);
assign free_list.potential_push = (gc.init_clear & ~clear_index[5]) | (wb_retire.valid);
assign free_list.push = free_list.potential_push;
assign free_list.data_in = gc.init_clear ? {1'b1, clear_index[4:0]} : (gc.writeback_supress ? inuse_table_output.spec_phys_addr : inuse_table_output.previous_phys_addr);
@ -110,7 +110,7 @@ module renamer
inuse_table (
.clk (clk),
.waddr (issue.id),
.raddr (retire.phys_id),
.raddr (wb_retire.id),
.ram_write (instruction_issued_with_rd),
.new_ram_data (inuse_table_input),
.ram_data_out (inuse_table_output)
@ -135,12 +135,12 @@ module renamer
rs_addr_t spec_table_write_index;
rs_addr_t spec_table_write_index_mux [4];
assign spec_table_update = rename_valid | rollback | gc.init_clear | (retire.valid & gc.writeback_supress);
assign spec_table_update = rename_valid | rollback | gc.init_clear | (wb_retire.valid & gc.writeback_supress);
logic [1:0] spec_table_sel;
one_hot_to_integer #(.C_WIDTH(4)) spec_table_sel_one_hot_to_int (
.one_hot ({gc.init_clear, rollback, (retire.valid & gc.writeback_supress), 1'b0}),
.one_hot ({gc.init_clear, rollback, (wb_retire.valid & gc.writeback_supress), 1'b0}),
.int_out (spec_table_sel)
);

4
core/store_queue.sv
View file

@ -174,7 +174,7 @@ module store_queue
store_retire_table_lutram (
.clk(clk),
.waddr(sq.data_in.id),
.raddr(store_retire.phys_id),
.raddr(store_retire.id),
.ram_write(sq.push),
.new_ram_data(retire_table_in),
.ram_data_out(retire_table_out)
@ -187,7 +187,7 @@ module store_queue
non_forwarded_port (
.clk(clk),
.waddr(sq.data_in.id),
.raddr(store_retire.phys_id),
.raddr(store_retire.id),
.ram_write(sq.push),
.new_ram_data(sq.data_in.data),
.ram_data_out(wb_data[0])

2
examples/nexys/nexys_sim.sv
View file

@ -443,7 +443,7 @@ module cva5_sim
.end_collection (end_collection),
.stats (stats),
.instruction_mix_stats (instruction_mix_stats),
.retire (cpu.retire)
.retire_count (cpu.retire_count)
);
////////////////////////////////////////////////////

4
test_benches/sim_stats.sv
View file

@ -36,7 +36,7 @@ module sim_stats
input logic end_collection,
input logic stats [NUM_OF_STATS],
input logic [NUM_INSTRUCTION_MIX_STATS-1:0] instruction_mix_stats [RETIRE_PORTS],
input retire_packet_t retire
input logic [LOG2_RETIRE_PORTS:0] retire_count
);
int log_file;
logic en;
@ -169,7 +169,7 @@ module sim_stats
instruction_mix_stat_count[i] <=0;
end
if (en) begin
instructions_retired <= instructions_retired + 64'(retire.count);
instructions_retired <= instructions_retired + 64'(retire_count);
cycle_count <= cycle_count + 1;
foreach (stat_count[i])
stat_count[i] <= stat_count[i] + 64'(stats[i]);

2
test_benches/verilator/cva5_sim.sv
View file

@ -578,7 +578,7 @@ module cva5_sim
.end_collection (end_collection),
.stats (stats),
.instruction_mix_stats (instruction_mix_stats),
.retire (cpu.retire)
.retire_count (cpu.retire_count)
);
////////////////////////////////////////////////////