Added L2 arbiter to verilator test platform

core/amo_alu.sv

@@ -39,6 +39,7 @@ module amo_alu(
 
     assign rs1_smaller_than_rs2 = rs1_ext < rs2_ext;
 
+    /* verilator lint_off CASEINCOMPLETE */
     always_comb begin
         unique case (amo_alu_inputs.op)// <--unique as not all codes are in use
             AMO_SWAP : result = amo_alu_inputs.rs2;
@@ -52,6 +53,6 @@ module amo_alu(
             AMO_MAXU : result = rs1_smaller_than_rs2 ? amo_alu_inputs.rs2 : amo_alu_inputs.rs1_load;
         endcase
     end
-
+    /* verilator lint_on CASEINCOMPLETE */
 
 endmodule

core/axi_to_arb.sv

@@ -35,12 +35,12 @@ module axi_to_arb
         input logic  axi_arready,
         output logic axi_arvalid,
         output logic[31:0] axi_araddr,
-        output logic[3:0] axi_arlen,
+        output logic[7:0] axi_arlen,
         output logic[2:0] axi_arsize,
         output logic[1:0] axi_arburst,
         output logic[2:0] axi_arprot,
         output logic[3:0] axi_arcache,
-        output logic[4:0] axi_arid,
+        output logic[5:0] axi_arid,
 
         //read data channel
         output logic axi_rready,
@@ -48,7 +48,7 @@ module axi_to_arb
         input logic[31:0] axi_rdata,
         input logic[1:0] axi_rresp,
         input logic axi_rlast,
-        input logic[4:0] axi_rid,
+        input logic[5:0] axi_rid,
 
         //write addr channel
         input logic axi_awready,
@@ -130,7 +130,7 @@ module axi_to_arb
     always_ff @ (posedge clk) begin
         if (rst)
             read_count <= 0;
-        else if (axi_rvalid && (axi_rid == l2.id))
+        else if (axi_rvalid && (axi_rid == 6'(l2.id)))
             read_count <= read_count + 1;
     end
 
@@ -143,7 +143,7 @@ module axi_to_arb
     //TODO:  assumption that all data caches have same line size, would have to update wrt the burst size to be safe if they have different line lengths
     //also update araddr
     always_ff @ (posedge clk) begin
-        if (axi_rvalid && (read_count == l2.addr[DCACHE_SUB_LINE_ADDR_W:0]))
+        if (axi_rvalid && (read_count == l2.addr[DCACHE_SUB_LINE_ADDR_W-1:0]))
             amo_result_r <= amo_result;
     end
 
@@ -152,7 +152,7 @@ module axi_to_arb
             amo_write_ready <= 0;
         else if (pop)
             amo_write_ready <= 0;
-        else if (l2.is_amo && axi_rvalid && read_count == l2.addr[DCACHE_SUB_LINE_ADDR_W:0])
+        else if (l2.is_amo && axi_rvalid && read_count == l2.addr[DCACHE_SUB_LINE_ADDR_W-1:0])
             amo_write_ready <= 1;
     end
     //End AMO
@@ -160,25 +160,25 @@ module axi_to_arb
     assign burst_count = l2.amo_type_or_burst_size;
 
     //read constants
-    assign axi_arlen = burst_count; //
+    assign axi_arlen = 8'(burst_count); //
     assign axi_arburst = 2'b01;// INCR
     assign axi_rready = 1; //always ready to receive data
     assign axi_arsize = 3'b010;//4 bytes
     assign axi_arcache = 4'b0011; //bufferable cacheable memory
-    assign axi_arport = '0;
-    assign axi_arid = l2.id;
+    assign axi_arprot = '0;
+    assign axi_arid = 6'(l2.id);
 
     assign axi_araddr ={l2.addr[29:DCACHE_SUB_LINE_ADDR_W],  {DCACHE_SUB_LINE_ADDR_W{1'b0}}, 2'b00};
 
     assign write_reference_burst_count = read_modify_write ? 0 : burst_count;
 
     //write constants
-    assign axi_awlen = write_reference_burst_count;
+    assign axi_awlen = 8'(write_reference_burst_count);
     assign axi_awburst = 2'b01;// INCR
     assign axi_awsize = 3'b010;//4 bytes
     assign axi_bready = 1;
     assign axi_awcache = 4'b0011;//bufferable cacheable memory
-    assign axi_awport = '0;
+    assign axi_awprot = '0;
 
     assign axi_awaddr ={l2.addr, 2'b00};
 
@@ -257,7 +257,7 @@ module axi_to_arb
 
     //read response
     assign l2.rd_data = axi_rdata;
-    assign l2.rd_id = axi_rid;
+    assign l2.rd_id = axi_rid[L2_ID_W-1:0];
     assign l2.rd_data_valid = axi_rvalid;
 
 endmodule

l2_arbiter/l2_fifo.sv

@@ -70,8 +70,8 @@ module l2_fifo  #(parameter DATA_WIDTH = 32, parameter FIFO_DEPTH = 4, parameter
                         write_index <= '0;
                     end            
                     else begin
-                        read_index <= read_index + fifo.pop;
-                        write_index <= write_index + fifo.push;
+                        read_index <= read_index + $clog2(FIFO_DEPTH)'(fifo.pop);
+                        write_index <= write_index + $clog2(FIFO_DEPTH)'(fifo.push);
                     end
                 end
 
@@ -88,16 +88,16 @@ module l2_fifo  #(parameter DATA_WIDTH = 32, parameter FIFO_DEPTH = 4, parameter
                         count_v[0] <= 1;
                         for (int i = 1; i <= FIFO_DEPTH; i++) count_v[i] <= 0;
                     end
-                    else if (fifo.push & ~fifo.pop)
-                        count_v <= {count_v[FIFO_DEPTH-1:0], 1'b0};
-                    else if (~fifo.push & fifo.pop)
-                        count_v <= {1'b0, count_v[FIFO_DEPTH:1]};
-                end                    
-                
+                    else if (fifo.push & ~fifo.pop) begin
+                        count_v[FIFO_DEPTH:1] <= count_v[FIFO_DEPTH-1:0];
+                        count_v[0] <= 1'b0;
+                    end else if (~fifo.push & fifo.pop) begin
+                        count_v[FIFO_DEPTH] <= 1'b0;
+                        count_v[FIFO_DEPTH-1:0] <= count_v[FIFO_DEPTH:1];
+                    end
+                end
             end
         end
     endgenerate
 
 endmodule
-
-

l2_arbiter/l2_round_robin.sv

@@ -52,10 +52,10 @@ module l2_round_robin
             //ex: state 0, highest priority to L2_NUM_PORTS-1
             always_comb begin
                 for (int i = 0; i < L2_NUM_PORTS; i++) begin
-                    muxes[i] = i;
+                    muxes[i] = $clog2(L2_NUM_PORTS)'(i);
                     for (int j = 0; j < L2_NUM_PORTS; j++) begin
                         if (arb.requests[(i+j) % L2_NUM_PORTS])
-                            muxes[i] = (i+j) % L2_NUM_PORTS;
+                            muxes[i] = $clog2(L2_NUM_PORTS)'((i+j) % L2_NUM_PORTS);
                     end
                 end
             end

test_benches/verilator/taiga_local_mem.sv

@@ -32,6 +32,48 @@ module taiga_local_mem # (
         input logic clk,
         input logic rst,
 
+        //DDR AXI
+        output logic [31:0]ddr_axi_araddr,
+        output logic [1:0]ddr_axi_arburst,
+        output logic [3:0]ddr_axi_arcache,
+        output logic [5:0]ddr_axi_arid,
+        output logic [7:0]ddr_axi_arlen,
+        output logic [0:0]ddr_axi_arlock,
+        output logic [2:0]ddr_axi_arprot,
+        output logic [3:0]ddr_axi_arqos,
+        output logic ddr_axi_arready,
+        output logic [3:0]ddr_axi_arregion,
+        output logic [2:0]ddr_axi_arsize,
+        input logic ddr_axi_arvalid,
+        output logic [31:0]ddr_axi_awaddr,
+        output logic [1:0]ddr_axi_awburst,
+        output logic [3:0]ddr_axi_awcache,
+        output logic [5:0]ddr_axi_awid,
+        output logic [7:0]ddr_axi_awlen,
+        output logic [0:0]ddr_axi_awlock,
+        output logic [2:0]ddr_axi_awprot,
+        output logic [3:0]ddr_axi_awqos,
+        input logic ddr_axi_awready,
+        output logic [3:0]ddr_axi_awregion,
+        output logic [2:0]ddr_axi_awsize,
+        output logic ddr_axi_awvalid,
+        output logic [5:0]ddr_axi_bid,
+        output logic ddr_axi_bready,
+        input logic [1:0]ddr_axi_bresp,
+        input logic ddr_axi_bvalid,
+        input logic [31:0]ddr_axi_rdata,
+        input logic [5:0]ddr_axi_rid,
+        input logic ddr_axi_rlast,
+        output logic ddr_axi_rready,
+        input logic [1:0]ddr_axi_rresp,
+        input logic ddr_axi_rvalid,
+        output logic [31:0]ddr_axi_wdata,
+        output logic ddr_axi_wlast,
+        input logic ddr_axi_wready,
+        output logic [3:0]ddr_axi_wstrb,
+        output logic ddr_axi_wvalid,
+        output logic [5:0]ddr_axi_wid,
+
         //        //AXI bus
         //        output logic [31:0]bus_axi_araddr,
         //        output logic [1:0]bus_axi_arburst,
@@ -95,36 +137,8 @@ module taiga_local_mem # (
         output logic instruction_issued,
         output logic taiga_events [0:$bits(taiga_trace_events_t)-1],
         output logic [31:0] instruction_pc_dec,
-        output logic [31:0] instruction_data_dec,
-
-        //L2
-        //l2 request
-        output logic [29:0] addr,
-        output logic [3:0] be,
-        output logic rnw,
-        output logic is_amo,
-        output logic [4:0] amo_type_or_burst_size,
-        output logic [L2_SUB_ID_W-1:0] sub_id,
-
-        output logic request_push,
-        input logic request_full,
-
-        input logic [31:2] inv_addr,
-        input logic inv_valid,
-        output logic inv_ack,
-
-        input logic con_result,
-        input logic con_valid,
-
-        output logic [31:0] wr_data,
-        output logic wr_data_push,
-        input logic data_full,
-
-        input logic [31:0] rd_data,
-        input logic [L2_SUB_ID_W-1:0] rd_sub_id,
-        input logic rd_data_valid,
-        output logic rd_data_ack
-        );
+        output logic [31:0] instruction_data_dec
+    );
 
     logic [3:0] WRITE_COUNTER_MAX;
     logic [3:0] READ_COUNTER_MAX;
@@ -182,6 +196,7 @@ module taiga_local_mem # (
     assign interrupt = 0;
 
     axi_interface m_axi();
+    axi_interface ddr_axi();
     avalon_interface m_avalon();
     wishbone_interface m_wishbone();
 
@@ -190,6 +205,8 @@ module taiga_local_mem # (
     l2_requester_interface l2[L2_NUM_PORTS-1:0]();
     l2_memory_interface mem();
 
+    local_memory_interface instruction_bram();
+    local_memory_interface data_bram();
 
     //    assign m_axi.arready = bus_axi_arready;
     //    assign bus_axi_arvalid = m_axi.arvalid;
@@ -220,11 +237,13 @@ module taiga_local_mem # (
     //    assign m_axi.bvalid = bus_axi_bvalid;
     //    assign m_axi.bresp = bus_axi_bresp;
 
+    assign l2[1].request_push = 0;
+    assign l2[1].wr_data_push = 0;
+    assign l2[1].inv_ack = l2[1].inv_valid;
+    assign l2[1].rd_data_ack = l2[1].rd_data_valid;
 
-
-    local_memory_interface instruction_bram();
-    local_memory_interface data_bram();
-
+    axi_to_arb l2_to_mem (.*, .l2(mem));
+    l2_arbiter l2_arb (.*, .request(l2));
 
     assign instruction_bram_addr = instruction_bram.addr;
     assign instruction_bram_en = instruction_bram.en;
@@ -238,22 +257,6 @@ module taiga_local_mem # (
     assign data_bram_data_in = data_bram.data_in;
     assign data_bram.data_out = data_bram_data_out;
 
-    // byte_en_BRAM #(MEM_LINES, MEMORY_FILE, 1) inst_data_ram (
-    //         .clk(clk),
-    //         .addr_a(instruction_bram.addr[$clog2(MEM_LINES)- 1:0]),
-    //         .en_a(instruction_bram.en),
-    //         .be_a(instruction_bram.be),
-    //         .data_in_a(instruction_bram.data_in),
-    //         .data_out_a(instruction_bram.data_out),
-
-    //         .addr_b(data_bram.addr[$clog2(MEM_LINES)- 1:0]),
-    //         .en_b(data_bram.en),
-    //         .be_b(data_bram.be),
-    //         .data_in_b(data_bram.data_in),
-    //         .data_out_b(data_bram.data_out)
-    //     );
-
-
     taiga cpu(.*, .l2(l2[0]));
 
     //read channel
@@ -351,6 +354,44 @@ module taiga_local_mem # (
     end
 
 
+
+    ////////////////////////////////////////////////////
+    //DDR AXI interface
+    assign ddr_axi.araddr = ddr_axi_araddr;
+    assign ddr_axi.arburst = ddr_axi_arburst;
+    assign ddr_axi.arcache = ddr_axi_arcache;
+    assign ddr_axi.arid = ddr_axi_arid;
+    assign ddr_axi.arlen = ddr_axi_arlen;
+    assign ddr_axi_arready = ddr_axi.arready;
+    assign ddr_axi.arsize = ddr_axi_arsize;
+    assign ddr_axi.arvalid = ddr_axi_arvalid;
+
+    assign ddr_axi.awaddr = ddr_axi_awaddr;
+    assign ddr_axi.awburst = ddr_axi_awburst;
+    assign ddr_axi.awcache = ddr_axi_awcache;
+    assign ddr_axi.awid = ddr_axi_awid;
+    assign ddr_axi.awlen = ddr_axi_awlen;
+    assign ddr_axi.awready = ddr_axi_awready;
+    assign ddr_axi.awvalid = ddr_axi_awvalid;
+
+    assign ddr_axi.bid = ddr_axi_bid;
+    assign ddr_axi_bready = ddr_axi.bready;
+    assign ddr_axi.bresp = ddr_axi_bresp;
+    assign ddr_axi.bvalid = ddr_axi_bvalid;
+
+    assign ddr_axi.rdata = ddr_axi_rdata;
+    assign ddr_axi.rid = ddr_axi_rid;
+    assign ddr_axi.rlast = ddr_axi_rlast;
+    assign ddr_axi_rready = ddr_axi.rready;
+    assign ddr_axi.rresp = ddr_axi_rresp;
+    assign ddr_axi.rvalid = ddr_axi_rvalid;
+
+    assign ddr_axi_wdata = ddr_axi.wdata;
+    assign ddr_axi_wlast = ddr_axi.wlast;
+    assign ddr_axi.wready = ddr_axi_wready;
+    assign ddr_axi_wstrb = ddr_axi.wstrb;
+    assign ddr_axi_wvalid = ddr_axi.wvalid;
+
     ////////////////////////////////////////////////////
     //Trace Interface
     assign instruction_pc_dec = tr.instruction_pc_dec;

tools/taiga_compile_order

@@ -103,5 +103,11 @@
 ../core/write_back.sv  
 
 ../core/placer_randomizer.sv
-../core/taiga.sv  
+
+../l2_arbiter/l2_fifo.sv
+../l2_arbiter/l2_reservation_logic.sv
+../l2_arbiter/l2_round_robin.sv
+../l2_arbiter/l2_arbiter.sv
+
+../core/taiga.sv