minor changes

core/decode_and_issue.sv

@@ -266,14 +266,15 @@ module decode_and_issue
     logic sub_instruction;
 
     always_comb begin
-        if (opcode_trim inside {LUI_T, AUIPC_T, JAL_T, JALR_T})
-            alu_op = ALU_CONSTANT;
-        else if (fn3 inside {SLTU_fn3, SLT_fn3})
-            alu_op = ALU_SLT;
-        else if (fn3 inside {SLL_fn3, SRA_fn3})
-            alu_op = ALU_SHIFT;
-        else
-            alu_op = ALU_ADD_SUB;
+        case (opcode_trim) inside
+            LUI_T, AUIPC_T, JAL_T, JALR_T : alu_op = ALU_CONSTANT;
+            default : 
+            case (fn3) inside
+                SLTU_fn3, SLT_fn3 : alu_op = ALU_SLT;
+                SLL_fn3, SRA_fn3 : alu_op = ALU_SHIFT;
+                default : alu_op = ALU_ADD_SUB;
+            endcase
+        endcase
     end
 
     always_comb begin
@@ -406,12 +407,11 @@ module decode_and_issue
 
 
     always_comb begin
-        if (~opcode[3] & opcode[2])
-            pc_offset = 21'(signed'(jalr_imm));
-        else if (opcode[3])
-            pc_offset = 21'(signed'({jal_imm, 1'b0}));
-        else
-            pc_offset = 21'(signed'({br_imm, 1'b0}));
+        case (opcode[3:2])
+            2'b11 : pc_offset = 21'(signed'({jal_imm, 1'b0}));
+            2'b01 : pc_offset = 21'(signed'(jalr_imm));
+            default : pc_offset = 21'(signed'({br_imm, 1'b0}));
+        endcase
     end
 
     logic jalr;

core/interfaces.sv

@@ -99,21 +99,6 @@ interface ras_interface;
     modport fetch (input addr, output pop, push, new_addr, branch_fetched);
 endinterface
 
-interface csr_exception_interface;
-    import riscv_types::*;
-
-    logic valid;
-    exception_code_t code;
-    logic [31:0] pc;
-    logic [31:0] addr;
-
-    logic illegal_instruction; //invalid CSR, invalid CSR op, or priviledge
-    logic[31:0] csr_pc;
-
-    modport csr (input valid, code, pc, addr, output illegal_instruction, csr_pc);
-    modport econtrol (output valid, code, pc, addr, input illegal_instruction, csr_pc);
-
-endinterface
 
 interface exception_interface;
     import riscv_types::*;
@@ -123,12 +108,11 @@ interface exception_interface;
     logic ack;
     
     exception_code_t code;
-    logic [31:0] pc;
-    logic [31:0] addr;
     id_t id;
-
-    modport econtrol (output valid, code, pc, addr, id, input ack);
-    modport unit (input valid, code, pc, addr, id, output ack);
+    logic [31:0] tval;
+    
+    modport unit (output valid, code, id, tval, input ack);
+    modport econtrol (input valid, code, id, tval, output ack);
 endinterface
 
 interface fifo_interface #(parameter DATA_WIDTH = 42);//#(parameter type data_type = logic[31:0]);
@@ -250,7 +234,7 @@ interface ls_sub_unit_interface #(parameter bit [31:0] BASE_ADDR = 32'h00000000,
     //Based on the lower and upper address ranges,
     //find the number of bits needed to uniquely identify this memory range.
     //Assumption: address range is aligned to its size
-    function int unsigned bit_range ();
+    function automatic int unsigned bit_range ();
         int unsigned i = 0;
         for(; i < 32; i++) begin
             if (BASE_ADDR[i] == UPPER_BOUND[i])
@@ -284,7 +268,7 @@ interface fetch_sub_unit_interface #(parameter bit [31:0] BASE_ADDR = 32'h000000
     //Based on the lower and upper address ranges,
     //find the number of bits needed to uniquely identify this memory range.
     //Assumption: address range is aligned to its size
-    function int unsigned bit_range ();
+    function automatic int unsigned bit_range ();
         int unsigned i = 0;
         for(; i < 32; i++) begin
             if (BASE_ADDR[i] == UPPER_BOUND[i])

core/taiga_config.sv

@@ -89,9 +89,11 @@ package taiga_config;
         bit INCLUDE_U_MODE;
         bit INCLUDE_MUL;
         bit INCLUDE_DIV;
-        bit INCLUDE_AMO; //Enable Atomic extension (cache operations only)
+        bit INCLUDE_AMO; //cache operations only
+        //CSR constants
         csr_config_t CSRS;
         //Memory Options
+        //Caches
         bit INCLUDE_ICACHE;
         cache_config_t ICACHE;
         memory_config_t ICACHE_ADDR;
@@ -100,10 +102,12 @@ package taiga_config;
         cache_config_t DCACHE;
         memory_config_t DCACHE_ADDR;
         tlb_config_t DTLB;
+        //Local memory
         bit INCLUDE_ILOCAL_MEM;
         memory_config_t ILOCAL_MEM_ADDR;
         bit INCLUDE_DLOCAL_MEM;
         memory_config_t DLOCAL_MEM_ADDR;
+        //Peripheral bus
         bit INCLUDE_PERIPHERAL_BUS;
         memory_config_t PERIPHERAL_BUS_ADDR;
         peripheral_bus_type_t PERIPHERAL_BUS_TYPE;
@@ -133,6 +137,7 @@ package taiga_config;
         INCLUDE_MUL : 1,
         INCLUDE_DIV : 1,
         INCLUDE_AMO : 0,
+        //CSR constants
         CSRS : '{
             MACHINE_IMPLEMENTATION_ID : 0,
             CPU_ID : 0,
@@ -193,6 +198,7 @@ package taiga_config;
             ENTRIES : 512,
             RAS_ENTRIES : 8
         },
+        //Writeback Options
         NUM_WB_GROUPS : 2
     };