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gettign rid of the deadcode in the dcache and handeling the way logic better

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msa417 2025-03-07 14:44:16 -08:00
parent d03087d377
commit c6867af6bf
1 changed files with 9 additions and 57 deletions
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66
core/execution_units/load_store_unit/dcache_inv.sv
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@ -185,19 +185,8 @@ module dcache_inv
logic stage1_tb_wval_r;
logic[CONFIG.DCACHE.WAYS-1:0] hit_ohot_r;
assign a_en = snoop_write | stage1_tb_write_r | ls.new_request ;// & ~inv_matches_stage1 )
assign a_wbe = ({CONFIG.DCACHE.WAYS{snoop_write}} & snoop_hit) | ({CONFIG.DCACHE.WAYS{stage1_tb_write_r}} & (stage1_type == CBO ? hit_ohot_r : (coming_to_read_after_snoop_reg == 1'b1 ? hit_ohot_r : replacement_way)));
logic[CONFIG.DCACHE.WAYS-1:0] rmw_refill_way;
always_ff @(posedge clk) begin
if (rst)
rmw_refill_way <= 0;
else if (current_state==RMW_FILLING & a_wbe!=0)
rmw_refill_way <= a_wbe;
else if (current_state!=RMW_FILLING)
rmw_refill_way <= 0;
end
assign a_en = snoop_write | stage1_tb_write_r | ls.new_request; // & ~inv_matches_stage1 )
assign a_wbe = ({CONFIG.DCACHE.WAYS{snoop_write}} & snoop_hit) | ({CONFIG.DCACHE.WAYS{stage1_tb_write_r}} & (stage1_type == CBO | (stage1_type == AMO_RMW & hit_r) ? hit_ohot_r : replacement_way));
always_comb begin
if (snoop_write)
@ -260,15 +249,10 @@ module dcache_inv
logic hit_r;
logic[CONFIG.DCACHE.WAYS-1:0] hit_ohot;
logic hit_state = 0;
always_comb begin
hit_ohot = '0;
// if(hit_state==2'd2)begin
// hit_ohot = hit_ohot_r;
// end else begin
for (int i = 0; i < CONFIG.DCACHE.WAYS; i++)
hit_ohot[i] = a_rdata[i].valid & (a_rdata[i].tag == stage1.addr[2+SCONFIG.SUB_LINE_ADDR_W+SCONFIG.LINE_ADDR_W+:SCONFIG.TAG_W]);
// end
for (int i = 0; i < CONFIG.DCACHE.WAYS; i++)
hit_ohot[i] = a_rdata[i].valid & (a_rdata[i].tag == stage1.addr[2+SCONFIG.SUB_LINE_ADDR_W+SCONFIG.LINE_ADDR_W+:SCONFIG.TAG_W]);
end
assign hit = |hit_ohot;
@ -276,26 +260,9 @@ module dcache_inv
if (stage0_advance_r) begin
hit_r <= hit;
hit_ohot_r <= hit_ohot;
end
// else if(hit_state==2'd1 && (stage1_tb_write_r & ~inv_matches_stage1))begin
// hit_r <= 0;
// hit_ohot_r <= a_wbe;
// end
// end else if((rmw_stage1_tb_write))begin
// hit_r <= 0;
// end
end
end
// always_ff @(posedge clk)begin
// if(rst)begin
// hit_state<=2'd0;
// end else if(stage0_advance_r) begin
// hit_state<=2'd0;
// end else if(rmw_retry)begin
// hit_state<=2'd1;
// end
// end
////////////////////////////////////////////////////
//Atomic read/modify/write state machine
//Separate from other logic because atomic requests will need to be retried on a snoop invalidation
@ -326,19 +293,9 @@ module dcache_inv
current_state <= next_state;
end
logic coming_to_read_after_snoop;
logic coming_to_read_after_snoop_reg;
always_ff @(posedge clk) begin
if (rst)
coming_to_read_after_snoop_reg <= 0;
else
coming_to_read_after_snoop_reg <= coming_to_read_after_snoop;
end
always_comb begin
unique case (current_state)
RMW_READ : begin
coming_to_read_after_snoop = coming_to_read_after_snoop_reg;
rmw_mem_request = 1;
rmw_mem_rnw = 1;
rmw_stage1_tb_write = mem.ack & ~stage1.uncacheable;
@ -349,7 +306,6 @@ module dcache_inv
next_state = mem.ack ? RMW_FILLING : RMW_READ;
end
RMW_WRITE : begin
coming_to_read_after_snoop = 0;
rmw_mem_request = ~rmw_retry;
rmw_mem_rnw = 0;
rmw_stage1_tb_write = 0;
@ -359,14 +315,12 @@ module dcache_inv
rmw_stage1_done = mem.ack;
if (mem.ack)
next_state = RMW_IDLE;
else if (rmw_retry)begin
else if (rmw_retry)
next_state = RMW_READ;
coming_to_read_after_snoop = 1;
end else
else
next_state = RMW_WRITE;
end
RMW_FILLING : begin
coming_to_read_after_snoop = 0;
rmw_mem_request = 0;
rmw_mem_rnw = 'x;
rmw_stage1_tb_write = 0;
@ -374,14 +328,12 @@ module dcache_inv
rmw_db_wdata = mem.rdata;
rmw_ls_data_valid = 0;
rmw_stage1_done = 0;
if (return_done)begin
if (return_done)
next_state = rmw_retry ? RMW_READ : RMW_WRITE;
coming_to_read_after_snoop = rmw_retry;
end else
else
next_state = RMW_FILLING;
end
RMW_IDLE : begin
coming_to_read_after_snoop = 0;
rmw_mem_request = 0;
rmw_mem_rnw = 'x;
rmw_stage1_tb_write = 0;