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resolved enum conflicts

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This commit is contained in:
Eric Matthews 2021-10-27 16:01:21 -07:00
parent 62ce33642f
commit c8121c5f79
5 changed files with 26 additions and 42 deletions
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18
core/amo_alu.sv
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@ -44,15 +44,15 @@ module amo_alu
/* verilator lint_off CASEINCOMPLETE */
always_comb begin
case (amo_alu_inputs.op)// <--unique as not all codes are in use
AMO_SWAP : result = amo_alu_inputs.rs2;
AMO_ADD : result = amo_alu_inputs.rs1_load + amo_alu_inputs.rs2;
AMO_XOR : result = amo_alu_inputs.rs1_load ^ amo_alu_inputs.rs2;
AMO_AND : result = amo_alu_inputs.rs1_load & amo_alu_inputs.rs2;
AMO_OR : result = amo_alu_inputs.rs1_load | amo_alu_inputs.rs2;
AMO_MIN : result = rs1_smaller_than_rs2 ? amo_alu_inputs.rs1_load : amo_alu_inputs.rs2;
AMO_MAX : result = rs1_smaller_than_rs2 ? amo_alu_inputs.rs2 : amo_alu_inputs.rs1_load;
AMO_MINU : result = rs1_smaller_than_rs2 ? amo_alu_inputs.rs1_load : amo_alu_inputs.rs2;
AMO_MAXU : result = rs1_smaller_than_rs2 ? amo_alu_inputs.rs2 : amo_alu_inputs.rs1_load;
AMO_SWAP_FN5 : result = amo_alu_inputs.rs2;
AMO_ADD_FN5 : result = amo_alu_inputs.rs1_load + amo_alu_inputs.rs2;
AMO_XOR_FN5 : result = amo_alu_inputs.rs1_load ^ amo_alu_inputs.rs2;
AMO_AND_FN5 : result = amo_alu_inputs.rs1_load & amo_alu_inputs.rs2;
AMO_OR_FN5 : result = amo_alu_inputs.rs1_load | amo_alu_inputs.rs2;
AMO_MIN_FN5 : result = rs1_smaller_than_rs2 ? amo_alu_inputs.rs1_load : amo_alu_inputs.rs2;
AMO_MAX_FN5 : result = rs1_smaller_than_rs2 ? amo_alu_inputs.rs2 : amo_alu_inputs.rs1_load;
AMO_MINU_FN5 : result = rs1_smaller_than_rs2 ? amo_alu_inputs.rs1_load : amo_alu_inputs.rs2;
AMO_MAXU_FN5 : result = rs1_smaller_than_rs2 ? amo_alu_inputs.rs2 : amo_alu_inputs.rs1_load;
endcase
end
/* verilator lint_on CASEINCOMPLETE */

2
core/axi_to_arb.sv
View file

@ -103,7 +103,7 @@ module axi_to_arb
//AMO read modify write support ****************************************************
assign read_modify_write = l2.is_amo && (l2.amo_type_or_burst_size != AMO_LR || l2.amo_type_or_burst_size != AMO_SC);
assign read_modify_write = l2.is_amo && (l2.amo_type_or_burst_size != AMO_LR_FN5 || l2.amo_type_or_burst_size != AMO_SC_FN5);
always_ff @ (posedge clk) begin
if (rst)

4
core/decode_and_issue.sv
View file

@ -329,8 +329,8 @@ module decode_and_issue
assign amo_op = CONFIG.INCLUDE_AMO ? (opcode_trim == AMO_T) : 1'b0;
assign amo_type = decode.instruction[31:27];
assign store_conditional = (amo_type == AMO_SC);
assign load_reserve = (amo_type == AMO_LR);
assign store_conditional = (amo_type == AMO_SC_FN5);
assign load_reserve = (amo_type == AMO_LR_FN5);
generate if (CONFIG.INCLUDE_AMO) begin
assign ls_inputs.amo.is_lr = load_reserve;

38
core/riscv_types.sv
View file

@ -38,22 +38,6 @@ package riscv_types;
logic [6:0] opcode;
} common_instruction_t;
typedef enum logic [6:0] {
LUI = 7'b0110111,
AUIPC = 7'b0010111,
JAL = 7'b1101111,
JALR = 7'b1100111,
BRANCH = 7'b1100011,
LOAD = 7'b0000011,
STORE = 7'b0100011,
ARITH_IMM = 7'b0010011,
ARITH = 7'b0110011,//includes mul/div
FENCE = 7'b0001111,
AMO = 7'b0101111,
SYSTEM = 7'b1110011
//end of RV32I
} opcodes_t;
typedef enum logic [4:0] {
LUI_T = 5'b01101,
AUIPC_T = 5'b00101,
@ -250,17 +234,17 @@ package riscv_types;
} interrupt_code_t;
typedef enum bit [4:0] {
AMO_LR = 5'b00010,
AMO_SC = 5'b00011,
AMO_SWAP = 5'b00001,
AMO_ADD = 5'b00000,
AMO_XOR = 5'b00100,
AMO_AND = 5'b01100,
AMO_OR = 5'b01000,
AMO_MIN = 5'b10000,
AMO_MAX = 5'b10100,
AMO_MINU = 5'b11000,
AMO_MAXU = 5'b11100
AMO_LR_FN5 = 5'b00010,
AMO_SC_FN5 = 5'b00011,
AMO_SWAP_FN5 = 5'b00001,
AMO_ADD_FN5 = 5'b00000,
AMO_XOR_FN5 = 5'b00100,
AMO_AND_FN5 = 5'b01100,
AMO_OR_FN5 = 5'b01000,
AMO_MIN_FN5 = 5'b10000,
AMO_MAX_FN5 = 5'b10100,
AMO_MINU_FN5 = 5'b11000,
AMO_MAXU_FN5 = 5'b11100
} amo_t;
//Assembly register definitions for simulation purposes

6
l2_arbiter/l2_arbiter.sv
View file

@ -192,9 +192,9 @@ module l2_arbiter
reserv_valid <= advance;
end
assign reserv_lr = (reserv_request.is_amo && reserv_request.amo_type_or_burst_size == AMO_LR);
assign reserv_sc = (reserv_request.is_amo && reserv_request.amo_type_or_burst_size == AMO_SC);
assign reserv_store = ~reserv_request.rnw | (reserv_request.is_amo && reserv_request.amo_type_or_burst_size != AMO_LR);
assign reserv_lr = (reserv_request.is_amo && reserv_request.amo_type_or_burst_size == AMO_LR_FN5);
assign reserv_sc = (reserv_request.is_amo && reserv_request.amo_type_or_burst_size == AMO_SC_FN5);
assign reserv_store = ~reserv_request.rnw | (reserv_request.is_amo && reserv_request.amo_type_or_burst_size != AMO_LR_FN5);
l2_reservation_logic reserv (.*,
.addr(reserv_request.addr),
.id(reserv_id),