zedboard example added

README.md

@@ -1,6 +1,20 @@
-Taiga
-================
+#Taiga
 
 Taiga is a 32-bit RISC-V processor designed for FPGAs supporting the Multiply/Divide and Atomic extensions (RV32IMA).  The processor is written in SystemVerilog and has been designed to be both highly extensible and highly configurable.
 
+The pipeline has been designed to support parallel, variable-latency execution units and to readily support the inclusion of new execution units.
+
+![Taiga Block Diagram](examples/zedboard/taiga_small.png)
+
+
+##License
+
 Taiga is licensed under the Apache License, Version 2.0 ( https://www.apache.org/licenses/LICENSE-2.0 )
+
+
+##Examples
+A zedboard configuration is provided under the examples directory along with tools for running stand-alone applications and providing application level simulation of the system.  (See the README in the zedboard directory for details.)
+
+
+##Publications
+E. Matthews and L. Shannon, "TAIGA: A new RISC-V soft-processor framework enabling high performance CPU architectural features," 2017 27th International Conference on Field Programmable Logic and Applications (FPL), Ghent, Belgium, 2017. [https://doi.org/10.23919/FPL.2017.8056766](https://doi.org/10.23919/FPL.2017.8056766)

core/avalon_master.vhd

@@ -1,24 +1,24 @@
-/*
- * Copyright © 2017 Eric Matthews,  Lesley Shannon
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * Initial code developed under the supervision of Dr. Lesley Shannon,
- * Reconfigurable Computing Lab, Simon Fraser University.
- *
- * Author(s):
- *             Eric Matthews <ematthew@sfu.ca>
- */
+--
+-- Copyright © 2017 Eric Matthews,  Lesley Shannon
+-- 
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+-- 
+-- http://www.apache.org/licenses/LICENSE-2.0
+-- 
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- 
+-- Initial code developed under the supervision of Dr. Lesley Shannon,
+-- Reconfigurable Computing Lab, Simon Fraser University.
+-- 
+-- Author(s):
+--             Eric Matthews <ematthew@sfu.ca>
+--
  
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;

core/decode.sv

@@ -279,13 +279,11 @@ module decode(
     //----------------------------------------------------------------------------------
     assign ls_ex.new_request_dec = issue[LS_UNIT_ID];
 
-    assign ls_offset = 32'(signed'(opcode[5] ? {ib.data_out.instruction[31:25], ib.data_out.instruction[11:7]} : ib.data_out.instruction[31:20]));
-
-    assign ls_inputs.virtual_address = rf_decode.rs1_data + ls_offset;//rf_decode.rs1_data;
+    assign ls_inputs.offset = opcode[5] ? {ib.data_out.instruction[31:25], ib.data_out.instruction[11:7]} : ib.data_out.instruction[31:20];
+    assign ls_inputs.virtual_address = rf_decode.rs1_data;
     assign ls_inputs.rs2 = rf_decode.rs2_data;
     assign ls_inputs.pc = ib.data_out.pc;
     assign ls_inputs.fn3 = ls_inputs.is_amo ? LS_W_fn3 : fn3;
-    //assign ls_inputs.imm = opcode[5] ? {ib.data_out.instruction[31:25], ib.data_out.instruction[11:7]} : ib.data_out.instruction[31:20];
     assign ls_inputs.amo = ib.data_out.instruction[31:27];
     assign ls_inputs.is_amo = (opcode == AMO);
     assign ls_inputs.load = (opcode == LOAD) || ((opcode == AMO) && (ls_inputs.amo != AMO_SC)); //LR and AMO_ops perform a read operation as well

core/fetch.sv

@@ -179,7 +179,7 @@ module fetch(
     assign fetch_sub[ICACHE_ID].stage2_addr = stage2_phys_address;
 
     //Memory interfaces
-    generate if (USE_SCRATCH_MEM)
+    generate if (USE_I_SCRATCH_MEM)
             ibram i_bram (.*, .fetch_sub(fetch_sub[BRAM_ID]));
         else
             assign  fetch_sub[BRAM_ID].ready = 1;

core/load_store_unit.sv

@@ -146,7 +146,7 @@ module load_store_unit (
     /*********************************
      * TLB interface
      *********************************/
-    assign virtual_address = stage1.virtual_address;// + 32'(signed'(stage1.imm)); <-- In decode/issue stage
+    assign virtual_address = stage1.virtual_address + 32'(signed'(stage1.offset));
 
     assign tlb.virtual_address = virtual_address;
     assign tlb.new_request = input_fifo.valid;
@@ -226,7 +226,7 @@ module load_store_unit (
      *  Unit Instantiation
      *********************************/
     //BRAM
-    generate if (USE_SCRATCH_MEM)
+    generate if (USE_D_SCRATCH_MEM)
             dbram d_bram (.clk(clk), .rst(rst), .ls_inputs(d_inputs), .ls(ls_sub[BRAM_ID]), .data_out(unit_data_array[BRAM_ID]), .*);
         else
             assign  ls_sub[BRAM_ID].ready = 1;

core/mul.sv

@@ -4,7 +4,7 @@
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
  * You may obtain a copy of the License at
- * 
+ *
  * http://www.apache.org/licenses/LICENSE-2.0
  *
  * Unless required by applicable law or agreed to in writing, software
@@ -19,7 +19,7 @@
  * Author(s):
  *             Eric Matthews <ematthew@sfu.ca>
  */
- 
+
 module mul
         #(
         parameter CYCLES = 4
@@ -27,9 +27,11 @@ module mul
         (
         input logic clk,
         input logic new_request,
-        input logic [1:0] op,
+        input logic lower,
+        input logic signa,
+        input logic signb,
         output logic done,
-        output logic [1:0] completed_op,
+        output logic completed_lower,
         input logic [31:0] A,
         input logic [31:0] B,
         output logic [63:0] P
@@ -39,24 +41,18 @@ module mul
     logic [32:0] B_r;
     logic [65:0] result [0:CYCLES-1];
     logic valid [0:CYCLES];
-    logic[1:0] mul_type [0:CYCLES];
+    logic mul_type [0:CYCLES];
 
-    logic unsigned_A_op;
-    logic unsigned_B_op;
-
-
-    assign unsigned_A_op = (op == 2'b11);
-    assign unsigned_B_op =op[1];
 
     always_ff @ (posedge clk) begin
-        A_r <= signed'({A[31] & ~unsigned_A_op, A});
-        B_r <= signed'({B[31] & ~unsigned_B_op,B});
+        A_r <= signed'({A[31] & signa, A});
+        B_r <= signed'({B[31] & signb, B});
         valid[0] <= new_request;
-        mul_type[0] <= op;
+        mul_type[0] <= lower;
         valid[1] <= valid[0];
         mul_type[1] <= mul_type[0];
-
         result[0] <= signed'(A_r) * signed'(B_r);
+
         for (int i = 0; i < CYCLES-1; i = i+1) begin
             result[i+1] <= result[i];
             valid[i+2] <= valid[i+1];
@@ -67,5 +63,5 @@ module mul
 
     assign P = result[CYCLES-1][63:0];
     assign done = valid[CYCLES];
-    assign completed_op = mul_type[CYCLES];
+    assign completed_lower = mul_type[CYCLES];
 endmodule

core/mul_unit.sv

@@ -4,7 +4,7 @@
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
  * You may obtain a copy of the License at
- * 
+ *
  * http://www.apache.org/licenses/LICENSE-2.0
  *
  * Unless required by applicable law or agreed to in writing, software
@@ -19,7 +19,7 @@
  * Author(s):
  *             Eric Matthews <ematthew@sfu.ca>
  */
- 
+
 import taiga_config::*;
 import taiga_types::*;
 
@@ -28,14 +28,10 @@ module mul_unit(
         input logic rst,
         func_unit_ex_interface.unit mul_ex,
         input mul_inputs_t mul_inputs,
-        unit_writeback_interface.unit mul_wb//writeback_unit_interface_dummy.unit mul_wb//
-
+        unit_writeback_interface.unit mul_wb
         );
 
-    parameter MUL_CYCLES = 1;
-    parameter FIFO_DEPTH = 2;
-
-    logic [$clog2(FIFO_DEPTH+1)-1:0] inflight_count;
+    logic [$clog2(MUL_OUTPUT_BUFFER_DEPTH+1)-1:0] inflight_count;
 
     struct packed{
         logic [31:0] upper;
@@ -43,8 +39,9 @@ module mul_unit(
     } mul_result;
 
     logic [31:0] result;
-    logic [1:0] mul_done_op;
-    logic mul_done;
+    logic mul_lower;
+    logic mul_done_lower;
+    logic signa, signb;
 
     fifo_interface #(.DATA_WIDTH(XLEN)) wb_fifo();
 
@@ -62,29 +59,27 @@ module mul_unit(
     always_ff @(posedge clk) begin
         if (rst)
             mul_ex.ready <= 1;
-        else if (mul_ex.new_request_dec && ~mul_wb.accepted && inflight_count == (FIFO_DEPTH-1))
+        else if (mul_ex.new_request_dec && ~mul_wb.accepted && inflight_count == (MUL_OUTPUT_BUFFER_DEPTH-1))
             mul_ex.ready <= 0;
         else if (mul_wb.accepted)
             mul_ex.ready <= 1;
     end
 
-    mul #(MUL_CYCLES) multiplier (.*, .A(mul_inputs.rs1), .B(mul_inputs.rs2),
-            .P(mul_result), .new_request(mul_ex.new_request_dec), .op(mul_inputs.op),
-            .done(mul_done), .completed_op(mul_done_op));
+    assign mul_lower = (mul_inputs.op[1:0] == 0);
 
-    always_comb begin
-        case (mul_done_op)
-            MUL_fn3[1:0] : result <= mul_result.lower;
-            MULH_fn3[1:0] : result <= mul_result.upper;
-            MULHSU_fn3[1:0] : result <= mul_result.upper;
-            MULHU_fn3[1:0] : result <= mul_result.upper;
-        endcase
-    end
+    assign signa = ~(mul_inputs.op[1:0] == 2'b11);
+    assign signb = ~mul_inputs.op[1];
+
+    mul #(MUL_CYCLES) multiplier (.*, .A(mul_inputs.rs1), .B(mul_inputs.rs2),
+            .P(mul_result), .new_request(mul_ex.new_request_dec), .signa(signa), .signb(signb), .lower(mul_lower),
+            .done(mul_done), .completed_lower(mul_done_lower));
+
+    assign result = mul_done_lower ? mul_result.lower : mul_result.upper;
 
     /*********************************
      *  Output FIFO
      *********************************/
-    lutram_fifo #(.DATA_WIDTH(XLEN), .FIFO_DEPTH(FIFO_DEPTH)) output_fifo (.fifo(wb_fifo), .*);
+    lutram_fifo #(.DATA_WIDTH(XLEN), .FIFO_DEPTH(MUL_OUTPUT_BUFFER_DEPTH)) output_fifo (.fifo(wb_fifo), .*);
 
     assign wb_fifo.data_in = result;
     assign wb_fifo.push = mul_done;

core/quickdiv.sv

@@ -4,7 +4,7 @@
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
  * You may obtain a copy of the License at
- * 
+ *
  * http://www.apache.org/licenses/LICENSE-2.0
  *
  * Unless required by applicable law or agreed to in writing, software
@@ -19,7 +19,7 @@
  * Author(s):
  *             Eric Matthews <ematthew@sfu.ca>
  */
- 
+
 module quickdiv
         #(
         parameter C_WIDTH = 32
@@ -52,24 +52,27 @@ module quickdiv
     logic [C_WIDTH-1:0] B1;
     logic [C_WIDTH-1:0] B2;
     logic [C_WIDTH-1:0] B_r;
+    logic [C_WIDTH:0] terminate_sub;
 
-    logic [$clog2(C_WIDTH)-1:0] R_MSB;
-    logic [$clog2(C_WIDTH)-1:0] B_MSB, B_MSB_r;
-    logic [$clog2(C_WIDTH)-1:0] MSB_delta;
+    localparam MSB_W = $clog2(C_WIDTH);
+    logic [MSB_W-1:0] R_MSB;
+    logic [MSB_W-1:0] B_MSB;
+    logic [MSB_W-1:0] MSB_delta;
+    logic [MSB_W-1:0] MSB_delta_r;
 
+    msb msb_r (.msb_input(running ? new_R : A), .msb(R_MSB));
+    msb msb_b (.msb_input(running ? B_r : B), .msb(B_MSB));
 
-    msb msb_r (.msb_input(R), .msb(R_MSB));
-    msb msb_b (.msb_input(B), .msb(B_MSB));
+    assign MSB_delta = R_MSB - B_MSB;
 
-    assign MSB_delta = R_MSB - B_MSB_r;
-
-    assign Q_bit1 = (1'b1 << MSB_delta);
+    assign Q_bit1 = 2**MSB_delta_r;
     assign Q_bit2 = {1'b0, Q_bit1[C_WIDTH-1:1]};
 
-    assign new_Q_bit = (A1[C_WIDTH] ? Q_bit2 : Q_bit1);
+    assign new_Q_bit = Q | (A1[C_WIDTH] ?  Q_bit2 : Q_bit1);
     assign new_R = A1[C_WIDTH] ? A2 : A1[C_WIDTH-1:0];
 
-    assign B1 = (B_r << MSB_delta);
+    assign B1 = (B_r << MSB_delta_r);
+
     assign B2 = {1'b0,B1[C_WIDTH-1:1]};
     assign A1 = R - B1;
     assign A2 = R - B2;
@@ -96,10 +99,12 @@ module quickdiv
         end
     end
 
-    assign terminate = (R < B_r);
+    //assign terminate_sub = {1'b0, R} - {1'b0, B_r};
+    //assign terminate =  terminate_sub[C_WIDTH];
+    assign terminate =  (R < B_r);
 
     always_ff @ (posedge clk) begin
-        B_MSB_r <= B_MSB;
+            MSB_delta_r <= MSB_delta;
     end
 
     always_ff @ (posedge clk) begin
@@ -108,10 +113,8 @@ module quickdiv
             R <= A;
             B_r <= B;
         end
-        else if (~terminate) begin
-            for (int i=0; i < 32; i++)
-                if(new_Q_bit[i])
-                    Q[i] <= 1;
+        else  if (~terminate) begin
+            Q <= new_Q_bit;
             R <= new_R;
         end
     end

core/register_file.sv

@@ -4,7 +4,7 @@
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
  * You may obtain a copy of the License at
- * 
+ *
  * http://www.apache.org/licenses/LICENSE-2.0
  *
  * Unless required by applicable law or agreed to in writing, software
@@ -19,7 +19,7 @@
  * Author(s):
  *             Eric Matthews <ematthew@sfu.ca>
  */
- 
+
 import taiga_config::*;
 import taiga_types::*;
 
@@ -38,9 +38,12 @@ module register_file(
     logic rs1_feedforward;
     logic rs2_feedforward;
 
-    //End of signal declarations
-    assign rs1_feedforward = (rf_decode.rs1_addr == rf_wb.rd_addr) && rf_wb.valid_write && (in_use_by[rf_wb.rd_addr] == rf_wb.id);
-    assign rs2_feedforward = (rf_decode.rs2_addr == rf_wb.rd_addr) && rf_wb.valid_write && (in_use_by[rf_wb.rd_addr] == rf_wb.id);
+    logic in_use_match;
+    //////////////////////////////////////////
+    assign in_use_match = (in_use_by[rf_wb.rd_addr] == rf_wb.id);
+
+    assign rs1_feedforward = (rf_decode.rs1_addr == rf_wb.rd_addr) && rf_wb.valid_write && in_use_match;
+    assign rs2_feedforward = (rf_decode.rs2_addr == rf_wb.rd_addr) && rf_wb.valid_write && in_use_match;
 
     //Assign zero to r0 and initialize all registers to zero
     initial begin
@@ -52,12 +55,12 @@ module register_file(
     end
 
     always_ff @ (posedge clk) begin
-        if (rf_wb.valid_write && rf_wb.rd_addr != 0 && (in_use_by[rf_wb.rd_addr] == rf_wb.id || inorder)) //inorder needed for case when multiple outstanding writes to this register (common pattern: load, store, load) where the first load hasn't completed by the second causes an exception.  Without inorder we wouldn't commit the first load
+        if (rf_wb.valid_write && rf_wb.rd_addr != 0 && (in_use_match || inorder)) //inorder needed for case when multiple outstanding writes to this register (common pattern: load, store, load) where the first load hasn't completed by the second causes an exception.  Without inorder we wouldn't commit the first load
             register[rf_wb.rd_addr] <= rf_wb.rd_data;
     end
 
     always_ff @ (posedge clk) begin
-        if (rf_decode.instruction_issued && rf_decode.future_rd_addr != 0 )
+        if (rf_decode.instruction_issued)
             in_use_by[rf_decode.future_rd_addr] <= rf_decode.id;
     end
 
@@ -69,7 +72,7 @@ module register_file(
                     inuse[i] <= 0;
                 else if (rf_decode.instruction_issued && rf_decode.future_rd_addr == i)
                     inuse[i] <= 1;
-                else if ( rf_wb.valid_write && (rf_wb.rd_addr == i) && (in_use_by[rf_wb.rd_addr] == rf_wb.id))//  || inorder <-- when exception has occurred
+                else if ( rf_wb.valid_write && (rf_wb.rd_addr == i) && in_use_match)//  || inorder <-- when exception has occurred
                     inuse[i] <= 0;
             end
         end

core/taiga_config.sv

@@ -58,12 +58,15 @@ package taiga_config;
     parameter LS_INPUT_BUFFER_DEPTH=4;
     parameter LS_OUTPUT_BUFFER_DEPTH=2;
 
+    parameter MUL_CYCLES = 1;
+    parameter MUL_OUTPUT_BUFFER_DEPTH=2;
+
     parameter DIV_INPUT_BUFFER_DEPTH=2;
     parameter DIV_OUTPUT_BUFFER_DEPTH=2;
 
-
     //Address space
-    parameter USE_SCRATCH_MEM = 1;
+    parameter USE_I_SCRATCH_MEM = 1;
+    parameter USE_D_SCRATCH_MEM = 1;
     parameter SCRATCH_ADDR_L = 32'h80000000;
     parameter SCRATCH_ADDR_H = 32'h8000FFFF;
     parameter SCRATCH_BIT_CHECK = 16;
@@ -80,7 +83,7 @@ package taiga_config;
     parameter C_M_AXI_ADDR_WIDTH = 32;
     parameter C_M_AXI_DATA_WIDTH = 32;
 
-    parameter USE_MMU = 1;
+    parameter USE_MMU = 0;
 
     //Caches
     //Size in bytes: (DCACHE_LINES * DCACHE_WAYS * DCACHE_LINE_W * 4)

core/taiga_types.sv

@@ -314,6 +314,7 @@ package taiga_types;
 
     typedef struct packed{
         logic [XLEN-1:0] virtual_address;
+        logic [11:0] offset;
         logic [XLEN-1:0] rs2;
         logic [2:0] fn3;
         logic [4:0] amo;

examples/zedboard/README.md

@@ -0,0 +1,98 @@
+Creating a Project for the Zedboard
+================
+
+
+    1. Select the zedboard as your board in Vivado and import standard board constraints
+    2. Add Taiga core and l2 arbiter sources to the project
+    3. Add the taiga_wrapper.sv from the zedboard directory
+    4. Add the Xilinx specific components which are generated through tcl scripts. From the Tcl Console run:
+        source <path to>/arm.tcl
+        source <path to/>system_peripherals.tcl
+
+System Configuration
+-----
+For this example system, the AXI bus interface is enabled for Taiga, and a UART is connected to the bus.  The memory interface is through the L2 arbiter to a High Performance Port on the ARM.
+
+![Taiga Block Diagram](system.png)
+
+
+
+Simulation
+-----------
+For application level simulation we have provided a top level system wrapper: taiga_tb.sv, a waveform conifuration file and a python script to convert riscv binaries into a input usable for the simulation.
+ 
+To simulate the system add all the sources in the simulation folder.  Set taiga_tb.sv as the top level entity and update the following two lines with paths to your benchmark simulation file and your uart output log file.  For testing purposes we have included a dhrystone.riscv.sim_init file that can be used to verify that the design has been correctly configured.
+
+    `define  MEMORY_FILE  "<path to sim_init file>"
+    `define  UART_LOG  "<output log>"
+
+Additionally, add the waveform config file to your project which includes many of the key control signals within Taiga and allows for the observation of program execution.  The testbench waveform is configured to show the dissasembly of the program as it executes to aid in debugging and unsderstanding of instruction flow within Taiga.
+
+![Sample Simulator Output](simulator_output_example.png)
+
+The simulation will run for a set amout of time units which can be modified by changing the 1200000 value below.
+
+    initial begin
+        simulator_clk = 0;
+        interrupt = '0;
+        simulator_resetn = 0;
+                
+        simulation_mem.load_program(`MEMORY_FILE, RESET_VEC);
+        
+        output_file = $fopen(`UART_LOG, "w");
+        if (output_file == 0) begin
+            $error ("couldn't open log file");
+            $finish;
+        end
+        do_reset();
+
+        #1200000;
+        $fclose(output_file);
+        $finish;
+    end
+
+Upon reaching finish, the simulator will flush the buffer to the output file and the uart log can be checked.  If the simulation is stopped early, the output_file will not show all/any writes to the UART.
+
+
+Building Software
+-----------
+To build stand-alone software you will need to build the risc-v gcc toolchain and riscv-tests:
+[https://github.com/riscv/riscv-tools](https://github.com/riscv/riscv-tools)
+
+
+Build the tools for a RV32IMA configuration.  To build new stand-alone applications the benchmarks in the riscv-tests can be used as a starting point.
+
+###Changes Required
+In order to build your own applications you will need to make a few small modifications to the setup in the riscv-tests/benchmarks directory.
+
+In the riscv-tests/benchmarks/Makefile, make sure XLEN is set to 32, and add -DHOST_DEBUG=0 to the RISCV_GCC_OPTS.
+
+In riscv-tests/benchmarks/common/crt.S the default stack size is 128KB which would well exceed a reasonable BRAM configuration.  To change the stack size change the the STKSHIFT define.  For 2KBs, set the value to 11.
+
+For UART support you will need to modify the riscv-tests/benchmarks/common/syscalls.c file, specifically, the putchar function.  Replace this function with one that sends a character to the UART.
+
+###Creating the simulation and BRAM init files
+To create the inputs for simulation, use the taiga_binary_converter.py (from the tools directory) on the resulting binaries to create inputs for simulation and BRAM initialization for hardware.
+
+The taiga_binary_converter.py script requires the following inputs:
+
+    python3 taiga_binary_converter.py <riscv-gcc-prefix> <base addr> <ram size in bytes> <input binary> <output BRAM init file> <output Simulation init file>
+
+Here is an example set of inputs for the script:
+
+    python3 taiga_binary_converter.py riscv32-unknown-elf- 0x80000000 65536 dhrystone.riscv  dhrystone.riscv.hw_init  dhrystone.riscv.sim_init
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

examples/zedboard/system_periperhals.tcl

@@ -0,0 +1,331 @@
+
+################################################################
+# This is a generated script based on design: design_2
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2017.3
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source design_2_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xc7z020clg484-1
+   set_property BOARD_PART em.avnet.com:zed:part0:0.9 [current_project]
+}
+
+
+# CHANGE DESIGN NAME HERE
+set design_name design_2
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
+   return $nRet
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+  set axi [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 axi ]
+  set_property -dict [ list \
+CONFIG.ADDR_WIDTH {32} \
+CONFIG.ARUSER_WIDTH {0} \
+CONFIG.AWUSER_WIDTH {0} \
+CONFIG.BUSER_WIDTH {0} \
+CONFIG.DATA_WIDTH {32} \
+CONFIG.FREQ_HZ {200000000} \
+CONFIG.HAS_BRESP {1} \
+CONFIG.HAS_BURST {1} \
+CONFIG.HAS_CACHE {1} \
+CONFIG.HAS_LOCK {1} \
+CONFIG.HAS_PROT {1} \
+CONFIG.HAS_QOS {1} \
+CONFIG.HAS_REGION {0} \
+CONFIG.HAS_RRESP {1} \
+CONFIG.HAS_WSTRB {1} \
+CONFIG.ID_WIDTH {6} \
+CONFIG.MAX_BURST_LENGTH {16} \
+CONFIG.NUM_READ_OUTSTANDING {8} \
+CONFIG.NUM_READ_THREADS {1} \
+CONFIG.NUM_WRITE_OUTSTANDING {8} \
+CONFIG.NUM_WRITE_THREADS {1} \
+CONFIG.PROTOCOL {AXI3} \
+CONFIG.READ_WRITE_MODE {READ_WRITE} \
+CONFIG.RUSER_BITS_PER_BYTE {0} \
+CONFIG.RUSER_WIDTH {0} \
+CONFIG.SUPPORTS_NARROW_BURST {1} \
+CONFIG.WUSER_BITS_PER_BYTE {0} \
+CONFIG.WUSER_WIDTH {0} \
+ ] $axi
+  set bus_axi [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 bus_axi ]
+  set_property -dict [ list \
+CONFIG.ADDR_WIDTH {13} \
+CONFIG.ARUSER_WIDTH {0} \
+CONFIG.AWUSER_WIDTH {0} \
+CONFIG.BUSER_WIDTH {0} \
+CONFIG.DATA_WIDTH {32} \
+CONFIG.FREQ_HZ {200000000} \
+CONFIG.HAS_BRESP {1} \
+CONFIG.HAS_BURST {0} \
+CONFIG.HAS_CACHE {0} \
+CONFIG.HAS_LOCK {0} \
+CONFIG.HAS_PROT {0} \
+CONFIG.HAS_QOS {0} \
+CONFIG.HAS_REGION {0} \
+CONFIG.HAS_RRESP {1} \
+CONFIG.HAS_WSTRB {1} \
+CONFIG.ID_WIDTH {0} \
+CONFIG.MAX_BURST_LENGTH {1} \
+CONFIG.NUM_READ_OUTSTANDING {1} \
+CONFIG.NUM_READ_THREADS {1} \
+CONFIG.NUM_WRITE_OUTSTANDING {1} \
+CONFIG.NUM_WRITE_THREADS {1} \
+CONFIG.PROTOCOL {AXI4LITE} \
+CONFIG.READ_WRITE_MODE {READ_WRITE} \
+CONFIG.RUSER_BITS_PER_BYTE {0} \
+CONFIG.RUSER_WIDTH {0} \
+CONFIG.SUPPORTS_NARROW_BURST {0} \
+CONFIG.WUSER_BITS_PER_BYTE {0} \
+CONFIG.WUSER_WIDTH {0} \
+ ] $bus_axi
+  set mem_axi [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 mem_axi ]
+  set_property -dict [ list \
+CONFIG.ADDR_WIDTH {32} \
+CONFIG.DATA_WIDTH {32} \
+CONFIG.FREQ_HZ {200000000} \
+CONFIG.PROTOCOL {AXI4} \
+ ] $mem_axi
+
+  # Create ports
+  set axi_clk [ create_bd_port -dir I -type clk axi_clk ]
+  set_property -dict [ list \
+CONFIG.ASSOCIATED_BUSIF {bus_axi:axi:mem_axi} \
+CONFIG.FREQ_HZ {200000000} \
+ ] $axi_clk
+  set processor_clk [ create_bd_port -dir O processor_clk ]
+  set processor_reset [ create_bd_port -dir O processor_reset ]
+  set resetn [ create_bd_port -dir I -type rst resetn ]
+  set sin [ create_bd_port -dir I sin ]
+  set sout [ create_bd_port -dir O sout ]
+
+  # Create instance: axi_interconnect_0, and set properties
+  set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
+  set_property -dict [ list \
+CONFIG.NUM_MI {1} \
+ ] $axi_interconnect_0
+
+  # Create instance: axi_uart16550_0, and set properties
+  set axi_uart16550_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uart16550:2.0 axi_uart16550_0 ]
+  set_property -dict [ list \
+CONFIG.C_EXTERNAL_XIN_CLK_HZ {25000000} \
+CONFIG.C_S_AXI_ACLK_FREQ_HZ {200000000} \
+ ] $axi_uart16550_0
+
+  # Need to retain value_src of defaults
+  set_property -dict [ list \
+CONFIG.C_EXTERNAL_XIN_CLK_HZ.VALUE_SRC {DEFAULT} \
+ ] $axi_uart16550_0
+
+  # Create instance: microblaze_0_axi_periph, and set properties
+  set microblaze_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 microblaze_0_axi_periph ]
+  set_property -dict [ list \
+CONFIG.NUM_MI {1} \
+ ] $microblaze_0_axi_periph
+
+  # Create instance: rst_clk_wiz_1_100M, and set properties
+  set rst_clk_wiz_1_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_clk_wiz_1_100M ]
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_ports bus_axi] [get_bd_intf_pins microblaze_0_axi_periph/S00_AXI]
+  connect_bd_intf_net -intf_net S00_AXI_2 [get_bd_intf_ports axi] [get_bd_intf_pins axi_interconnect_0/S00_AXI]
+  connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_ports mem_axi] [get_bd_intf_pins axi_interconnect_0/M00_AXI]
+  connect_bd_intf_net -intf_net microblaze_0_axi_periph_M00_AXI [get_bd_intf_pins axi_uart16550_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M00_AXI]
+
+  # Create port connections
+  connect_bd_net -net axi_uart16550_0_sout [get_bd_ports sout] [get_bd_pins axi_uart16550_0/sout]
+  connect_bd_net -net microblaze_0_Clk [get_bd_ports axi_clk] [get_bd_ports processor_clk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_uart16550_0/s_axi_aclk] [get_bd_pins microblaze_0_axi_periph/ACLK] [get_bd_pins microblaze_0_axi_periph/M00_ACLK] [get_bd_pins microblaze_0_axi_periph/S00_ACLK] [get_bd_pins rst_clk_wiz_1_100M/slowest_sync_clk]
+  connect_bd_net -net resetn_1 [get_bd_ports resetn] [get_bd_pins rst_clk_wiz_1_100M/ext_reset_in]
+  connect_bd_net -net rst_clk_wiz_1_100M_interconnect_aresetn [get_bd_pins microblaze_0_axi_periph/ARESETN] [get_bd_pins rst_clk_wiz_1_100M/interconnect_aresetn]
+  connect_bd_net -net rst_clk_wiz_1_100M_mb_reset [get_bd_ports processor_reset] [get_bd_pins rst_clk_wiz_1_100M/mb_reset]
+  connect_bd_net -net rst_clk_wiz_1_100M_peripheral_aresetn [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_uart16550_0/s_axi_aresetn] [get_bd_pins microblaze_0_axi_periph/M00_ARESETN] [get_bd_pins microblaze_0_axi_periph/S00_ARESETN] [get_bd_pins rst_clk_wiz_1_100M/peripheral_aresetn]
+  connect_bd_net -net sin_1 [get_bd_ports sin] [get_bd_pins axi_uart16550_0/sin]
+
+  # Create address segments
+  create_bd_addr_seg -range 0x10000000 -offset 0x80000000 [get_bd_addr_spaces axi] [get_bd_addr_segs mem_axi/Reg] SEG_M00_AXI_Reg
+  create_bd_addr_seg -range 0x00002000 -offset 0x00000000 [get_bd_addr_spaces bus_axi] [get_bd_addr_segs axi_uart16550_0/S_AXI/Reg] SEG_axi_uart16550_0_Reg
+
+  # Perform GUI Layout
+  regenerate_bd_layout -layout_string {
+   guistr: "# # String gsaved with Nlview 6.6.5b  2016-09-06 bk=1.3687 VDI=39 GEI=35 GUI=JA:1.6
+#  -string -flagsOSRD
+preplace port bus_axi -pg 1 -y 30 -defaultsOSRD
+preplace port processor_clk -pg 1 -y 500 -defaultsOSRD
+preplace port sin -pg 1 -y 440 -defaultsOSRD
+preplace port resetn -pg 1 -y 100 -defaultsOSRD
+preplace port axi -pg 1 -y 250 -defaultsOSRD
+preplace port sout -pg 1 -y 280 -defaultsOSRD
+preplace port processor_reset -pg 1 -y 460 -defaultsOSRD
+preplace port axi_clk -pg 1 -y 170 -defaultsOSRD
+preplace port mem_axi -pg 1 -y 310 -defaultsOSRD
+preplace inst microblaze_0_axi_periph -pg 1 -lvl 3 -y 90 -defaultsOSRD
+preplace inst axi_interconnect_0 -pg 1 -lvl 1 -y 310 -defaultsOSRD
+preplace inst rst_clk_wiz_1_100M -pg 1 -lvl 2 -y 80 -defaultsOSRD
+preplace inst axi_uart16550_0 -pg 1 -lvl 2 -y 270 -defaultsOSRD
+preplace netloc sin_1 1 0 3 NJ 440 NJ 440 1060
+preplace netloc microblaze_0_Clk 1 0 4 -40 -30 340J -30 1090 -30 1410
+preplace netloc axi_uart16550_0_sout 1 2 2 N 280 NJ
+preplace netloc microblaze_0_axi_periph_M00_AXI 1 1 3 350 -70 NJ -70 1400
+preplace netloc resetn_1 1 0 2 -30J 60 N
+preplace netloc rst_clk_wiz_1_100M_interconnect_aresetn 1 2 1 1080
+preplace netloc S00_AXI_1 1 0 3 -50J -10 NJ -10 1070J
+preplace netloc rst_clk_wiz_1_100M_peripheral_aresetn 1 0 3 -30 430 350 430 1100
+preplace netloc rst_clk_wiz_1_100M_mb_reset 1 2 2 1070 460 NJ
+preplace netloc axi_interconnect_0_M00_AXI 1 1 3 340J 350 NJ 350 1420J
+preplace netloc S00_AXI_2 1 0 1 N
+levelinfo -pg 1 -70 200 890 1260 1450 -top -110 -bot 1110
+",
+}
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+

examples/zedboard/taiga_wrapper.sv

@@ -0,0 +1,253 @@
+/*
+ * Copyright © 2017 Eric Matthews,  Lesley Shannon
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Initial code developed under the supervision of Dr. Lesley Shannon,
+ * Reconfigurable Computing Lab, Simon Fraser University.
+ *
+ * Author(s):
+ *             Eric Matthews <ematthew@sfu.ca>
+ */
+
+import taiga_config::*;
+import taiga_types::*;
+import l2_config_and_types::*;
+
+module taiga_wrapper (
+        input logic sys_clk,
+        input logic ext_reset,
+
+
+        inout [14:0]DDR_addr,
+        inout [2:0]DDR_ba,
+        inout DDR_cas_n,
+        inout DDR_ck_n,
+        inout DDR_ck_p,
+        inout DDR_cke,
+        inout DDR_cs_n,
+        inout [3:0]DDR_dm,
+        inout [31:0]DDR_dq,
+        inout [3:0]DDR_dqs_n,
+        inout [3:0]DDR_dqs_p,
+        inout DDR_odt,
+        inout DDR_ras_n,
+        inout DDR_reset_n,
+        inout DDR_we_n,
+        inout FIXED_IO_ddr_vrn,
+        inout FIXED_IO_ddr_vrp,
+        inout [53:0]FIXED_IO_mio,
+        inout FIXED_IO_ps_clk,
+        inout FIXED_IO_ps_porb,
+        inout FIXED_IO_ps_srstb,
+
+        input logic sin,
+        output logic sout
+
+        );
+
+    logic clk;
+    logic rst;
+    logic resetn;
+
+    axi_interface m_axi();
+    avalon_interface m_avalon();
+    l2_requester_interface l2[L2_NUM_PORTS-1:0]();
+    l2_memory_interface mem();
+
+    logic interrupt;
+
+    assign interrupt = 0;
+
+    //mem axi
+    logic [31:0]mem_axi_araddr;
+    logic [1:0]mem_axi_arburst;
+    logic [3:0]mem_axi_arcache;
+    logic [5:0]mem_axi_arid;
+    logic [7:0]mem_axi_arlen;
+    logic [0:0]mem_axi_arlock;
+    logic [2:0]mem_axi_arprot;
+    logic [3:0]mem_axi_arqos;
+    logic mem_axi_arready;
+    logic [3:0]mem_axi_arregion;
+    logic [2:0]mem_axi_arsize;
+    logic mem_axi_arvalid;
+    logic [31:0]mem_axi_awaddr;
+    logic [1:0]mem_axi_awburst;
+    logic [3:0]mem_axi_awcache;
+    logic [5:0]mem_axi_awid;
+    logic [7:0]mem_axi_awlen;
+    logic [0:0]mem_axi_awlock;
+    logic [2:0]mem_axi_awprot;
+    logic [3:0]mem_axi_awqos;
+    logic mem_axi_awready;
+    logic [3:0]mem_axi_awregion;
+    logic [2:0]mem_axi_awsize;
+    logic mem_axi_awvalid;
+    logic [5:0]mem_axi_bid;
+    logic mem_axi_bready;
+    logic [1:0]mem_axi_bresp;
+    logic mem_axi_bvalid;
+    logic [31:0]mem_axi_rdata;
+    logic [5:0]mem_axi_rid;
+    logic mem_axi_rlast;
+    logic mem_axi_rready;
+    logic [1:0]mem_axi_rresp;
+    logic mem_axi_rvalid;
+    logic [31:0]mem_axi_wdata;
+    logic mem_axi_wlast;
+    logic mem_axi_wready;
+    logic [3:0]mem_axi_wstrb;
+    logic mem_axi_wvalid;
+    logic [5:0] mem_axi_wid;
+
+    logic ACLK;
+    logic [31:0]bus_axi_araddr;
+    logic bus_axi_arready;
+    logic bus_axi_arvalid;
+    logic [31:0]bus_axi_awaddr;
+    logic bus_axi_awready;
+    logic bus_axi_awvalid;
+    logic bus_axi_bready;
+    logic [1:0]bus_axi_bresp;
+    logic bus_axi_bvalid;
+    logic [31:0]bus_axi_rdata;
+    logic bus_axi_rready;
+    logic [1:0]bus_axi_rresp;
+    logic bus_axi_rvalid;
+    logic [31:0]bus_axi_wdata;
+    logic bus_axi_wready;
+    logic [3:0]bus_axi_wstrb;
+    logic bus_axi_wvalid;
+
+    logic processor_reset;
+
+
+    //Arbiter AXI interface
+    logic axi_arready;
+    logic axi_arvalid;
+    logic[31:0] axi_araddr;
+    logic[3:0] axi_arlen;
+    logic[2:0] axi_arsize;
+    logic[1:0] axi_arburst;
+    logic[2:0] axi_arprot;
+    logic[3:0] axi_arcache;
+    logic[3:0] axi_arid;
+    logic [1:0]axi_arlock;
+    logic [3:0]axi_arqos;
+
+    //read data channel
+    logic axi_rready;
+    logic axi_rvalid;
+    logic[31:0] axi_rdata;
+    logic[1:0] axi_rresp;
+    logic axi_rlast;
+    logic[3:0] axi_rid;
+
+    //write addr channel
+    logic axi_awready;
+    logic axi_awvalid;
+    logic [31:0] axi_awaddr;
+    logic [7:0] axi_awlen;
+    logic [2:0] axi_awsize;
+    logic [1:0] axi_awburst;
+    logic [1:0]axi_awlock;
+    logic [3:0]axi_awqos;
+    logic [5:0]axi_awid;
+
+    logic[3:0] axi_awcache;
+    logic[2:0] axi_awprot;
+
+    //write data
+    logic axi_wready;
+    logic axi_wvalid;
+    logic [31:0] axi_wdata;
+    logic [3:0] axi_wstrb;
+    logic axi_wlast;
+    logic [5:0]axi_wid;
+
+
+    //write response
+    logic axi_bready;
+    logic axi_bvalid;
+    logic [1:0] axi_bresp;
+    logic [5:0]axi_bid;
+
+
+    logic axi_clk;
+    logic processor_clk;
+
+    assign axi_clk = clk;
+
+    assign rst = processor_reset;
+
+
+    assign m_axi.arready = bus_axi_arready;
+    assign bus_axi_arvalid = m_axi.arvalid;
+    assign bus_axi_araddr = m_axi.araddr[12:0];
+
+
+    //read data
+    assign bus_axi_rready = m_axi.rready;
+    assign m_axi.rvalid = bus_axi_rvalid;
+    assign m_axi.rdata = bus_axi_rdata;
+    assign m_axi.rresp = bus_axi_rresp;
+
+    //Write channel
+    //write address
+    assign m_axi.awready = bus_axi_awready;
+    assign bus_axi_awaddr = m_axi.awaddr[12:0];
+    assign bus_axi_awvalid = m_axi.awvalid;
+
+
+    //write data
+    assign m_axi.wready = bus_axi_wready;
+    assign bus_axi_wvalid = m_axi. wvalid;
+    assign bus_axi_wdata = m_axi.wdata;
+    assign bus_axi_wstrb = m_axi.wstrb;
+
+    //write response
+    assign bus_axi_bready = m_axi.bready;
+    assign m_axi.bvalid = bus_axi_bvalid;
+    assign m_axi.bresp = bus_axi_bresp;
+
+
+    bram_interface instruction_bram();
+    bram_interface data_bram();
+
+    taiga cpu(.*, .l2(l2[0]));
+
+    design_2 infra(.*);
+
+    l2_arbiter l2_arb (.*, .request(l2));
+
+    axi_to_arb l2_to_mem (.*, .l2(mem));
+
+    arm proc(.*);
+
+    byte_en_BRAM #(8192) inst_data_ram (
+            .clk(clk),
+            .addr_a(instruction_bram.addr[$clog2(8192)- 1:0]),
+            .en_a(instruction_bram.en),
+            .be_a(instruction_bram.be),
+            .data_in_a(instruction_bram.data_in),
+            .data_out_a(instruction_bram.data_out),
+
+            .addr_b(data_bram.addr[$clog2(8192)- 1:0]),
+            .en_b(data_bram.en),
+            .be_b(data_bram.be),
+            .data_in_b(data_bram.data_in),
+            .data_out_b(data_bram.data_out)
+        );
+
+endmodule

test_benches/axi_mem_sim.sv

@@ -0,0 +1,212 @@
+/*
+ * Copyright © 2017 Eric Matthews,  Lesley Shannon
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Initial code developed under the supervision of Dr. Lesley Shannon,
+ * Reconfigurable Computing Lab, Simon Fraser University.
+ *
+ * Author(s):
+ *             Eric Matthews <ematthew@sfu.ca>
+ */
+
+//No error checking for incorrect ordering of axi control signals from Master side of interface
+import tb_tools::*;
+import taiga_config::*;
+
+module axi_mem_sim
+        #(parameter string file_name = "")
+        (
+        input logic clk,
+        input logic rst,
+        axi_interface.slave axi,
+
+        input logic[31:0] if_pc,
+        input logic[31:0] dec_pc
+        );
+
+    typedef struct packed{
+        logic [31:0] araddr;
+        logic [7:0] arlen;
+        logic [2:0] arsize;
+        logic [1:0] arburst;
+        logic [3:0] arcache;
+        logic [5:0] arid;
+    } read_request;
+
+    typedef struct packed{
+        logic [31:0] awaddr;
+        logic [7:0] awlen;
+        logic [2:0] awsize;
+        logic [1:0] awburst;
+        logic [3:0] awcache;
+        logic [5:0] awid;
+    } write_request;
+
+    const int READ_QUEUE_DEPTH = 8;
+    const int WRITE_QUEUE_DEPTH = 4;
+    const int WRITE_DATA_QUEUE_DEPTH = 128;
+
+    integer write_queue_size;
+    integer read_data_queue_size;
+    logic[47:0] write_request_count;
+    logic[47:0] read_request_count;
+
+    int read_burst_count;
+    int processing_read_request;
+    int processing_write_request;
+
+    read_request read_queue[$];
+    write_request write_queue[$];
+    logic [31:0] write_data_queue[$];
+    logic [31:0] read_data_queue[$];
+
+    sim_mem ddr = new();
+
+    //For opcode inspection
+    string dec_opcode;
+    string if_opcode;
+    logic[0:64*8-1] if_inst_text;
+    logic[0:64*8-1] dec_inst_text;
+    /////////////////////
+
+    function void getReadData (bit[31:0] addr, bit[7:0] len);
+        for (int i = 0; i <= len; i=i+1) begin
+            read_data_queue.push_back(ddr.readw(addr[31:2]+i));
+        end
+    endfunction
+
+    //Simulation opcode support
+    assign if_opcode = ddr.readopcode(if_pc[31:2]);
+    assign dec_opcode = ddr.readopcode(dec_pc[31:2]);
+
+    genvar i;
+    generate
+        for(i=0; i<64; i=i+1) begin
+            always_comb begin
+                if_inst_text[8*i: 8*(i+1) -1]=if_opcode[i];
+                dec_inst_text[8*i: 8*(i+1) -1]=dec_opcode[i];
+            end
+        end
+    endgenerate
+    ///////////////////
+
+
+    initial begin
+        ddr.load_program(file_name, RESET_VEC);
+    end
+
+    //arready response
+    assign axi.arready = read_queue.size() < READ_QUEUE_DEPTH;
+
+    //Read request processing
+    always_ff @(posedge clk) begin
+        if (rst) begin
+            read_request_count <= 0;
+        end
+        else if(axi.arvalid & axi.arready) begin
+            read_queue.push_back(
+                    {axi.araddr, axi.arlen, axi.arsize, axi.arburst, axi.arcache, axi.arid}
+                );
+            getReadData(axi.araddr, axi.arlen);
+            read_request_count <=read_request_count+1;
+        end
+    end
+
+    //Write request processing
+    always_ff @(posedge clk) begin
+        if(axi.awvalid & axi.awready) begin
+            write_queue.push_back(
+                    {axi.awaddr, axi.awlen, axi.awsize, axi.awburst, axi.awcache, axi.awid}
+                );
+        end
+        write_queue_size <= write_queue.size();
+    end
+    assign axi.awready = write_queue.size() < WRITE_QUEUE_DEPTH;
+
+    assign axi.wready = write_data_queue.size() < WRITE_DATA_QUEUE_DEPTH;
+
+    //bresp
+    always_ff @(posedge clk) begin
+        if (rst) begin
+            axi.bvalid <= 0;
+        end
+        else if(axi.wvalid & axi.wlast) begin
+            axi.bresp <= 0;
+            axi.bvalid <=1;
+            axi.bid <= write_queue[0].awid;
+            write_queue.pop_front();
+        end
+        else if (axi.bready) begin
+            axi.bvalid <=0;
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        if (rst) begin
+            write_request_count <= 0;
+        end
+        else if(axi.wvalid) begin
+           write_request_count <= write_request_count + 1;
+        end
+    end
+
+    //Handle write data
+    always_ff @(posedge clk) begin
+        if (rst) begin
+        end
+        else if(axi.wvalid) begin
+            ddr.writew(write_queue.size > 0 ? write_queue[0].awaddr[31:2] : axi.awaddr[31:2], axi.wdata, axi.wstrb);
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        read_data_queue_size <= read_data_queue.size();
+    end
+
+    //Return data
+    always_ff @(posedge clk) begin
+        if(rst) begin
+            axi.rvalid <= 0;
+            axi.rlast <= 0;
+            read_burst_count <= 0;
+        end
+        else if(read_queue.size > 0) begin
+            if(axi.rready) begin
+                axi.rdata <= read_data_queue.pop_front();
+                axi.rvalid <= 1;
+                axi.rid <=  read_queue[0].arid;
+                if( read_queue[0].arlen == read_burst_count) begin
+                    axi.rlast <= 1;
+                    read_queue.pop_front();
+                    read_burst_count <= 0;
+                end
+                else begin
+                    read_burst_count <= read_burst_count + 1;
+                    axi.rlast <= 0;
+                end
+            end
+            else begin
+                axi.rvalid <= 0;
+                axi.rlast <= 0;
+            end
+        end
+        else begin
+            axi.rvalid <= 0;
+            axi.rlast <= 0;
+        end
+    end
+
+endmodule
+
+

test_benches/sim_mem.sv

@@ -0,0 +1,150 @@
+/*
+ * Copyright © 2017 Eric Matthews,  Lesley Shannon
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Initial code developed under the supervision of Dr. Lesley Shannon,
+ * Reconfigurable Computing Lab, Simon Fraser University.
+ *
+ * Author(s):
+ *             Eric Matthews <ematthew@sfu.ca>
+ */
+
+/*
+ * Copyright © 2017 Eric Matthews,  Lesley Shannon
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Initial code developed under the supervision of Dr. Lesley Shannon,
+ * Reconfigurable Computing Lab, Simon Fraser University.
+ *
+ * Author(s):
+ *             Eric Matthews <ematthew@sfu.ca>
+ */
+
+package tb_tools;
+
+class sim_mem;
+    local logic [31:0] ram [bit [29:0]];
+    local string opcodes [bit [29:0]];
+
+    function void load_program (string file_name, integer unsigned base_addr);
+        integer program_data;
+        integer line_number;
+        string string_line;
+        string program_asm;
+        string program_asm0; //string array for the following usage is not supported by Vivado
+        string program_asm1;
+        string program_asm2;
+        string program_asm3;
+        string program_asm4;
+        string program_asm5;
+        string program_asm6;
+        string program_asm7;
+
+        integer scan_result;
+        integer read_line_result;
+        integer unsigned program_addr;
+
+        integer program_file = $fopen(file_name, "r");
+        if (program_file == 0) begin
+            $error ("couldn't open file: %s", file_name);
+            $finish;
+        end
+
+        program_addr = base_addr;
+        read_line_result = $fgets (string_line, program_file);
+        line_number = 1;
+
+        while (read_line_result !== 0) begin
+            program_asm0 = " ";
+            program_asm1 = " ";
+            program_asm2 = " ";
+            program_asm3 = " ";
+            program_asm4 = " ";
+            program_asm5 = " ";
+            program_asm6 = " ";
+            program_asm7 = " ";
+
+            scan_result = $sscanf(string_line, "%x %s %s %s %s %s %s %s %s", program_data, program_asm0, program_asm1, program_asm2, program_asm3, program_asm4, program_asm5, program_asm6, program_asm7);
+
+            if (scan_result < 2) begin
+                $error ("data file incorrectly formatted on line: %d\n%s", line_number,string_line);
+                $finish;
+            end
+
+            if (scan_result == 2)
+                program_asm = {program_asm0, " "};
+            else if (scan_result == 3)
+                program_asm = {program_asm0, " ", program_asm1};
+            else if (scan_result == 4)
+                program_asm = {program_asm0, " ", program_asm1, " ", program_asm2};
+            else if (scan_result == 5)
+                program_asm = {program_asm0, " ", program_asm1, " ", program_asm2, " ", program_asm3};
+            else if (scan_result == 6)
+                program_asm = {program_asm0, " ", program_asm1, " ", program_asm2, " ", program_asm3, " ", program_asm4};
+            else if (scan_result == 7)
+                program_asm = {program_asm0, " ", program_asm1, " ", program_asm2, " ", program_asm3, " ", program_asm4, " ", program_asm5};
+            else if (scan_result == 8)
+                program_asm = {program_asm0, " ", program_asm1, " ", program_asm2, " ", program_asm3, " ", program_asm4, " ", program_asm5, " ", program_asm6};
+            else
+                program_asm = {program_asm0, " ", program_asm1, " ", program_asm2, " ", program_asm3, " ", program_asm4, " ", program_asm5, " ", program_asm6, " ", program_asm7};
+
+
+            this.ram[program_addr[31:2]]= program_data;
+            this.opcodes[program_addr[31:2]]= program_asm;
+
+            read_line_result = $fgets (string_line, program_file);
+            line_number = line_number + 1;
+            program_addr = program_addr + 4;
+
+        end
+
+        $fclose(program_file);
+    endfunction
+
+    function logic[31:0] readw (bit[31:0] addr);
+        readw = 32'hXXXXXXXX;
+        if (this.ram.exists(addr))
+            readw = this.ram[addr];
+    endfunction
+
+    function string readopcode (bit[31:0] addr);
+        readopcode = "not an instruction";
+        if (this.opcodes.exists(addr))
+            readopcode = this.opcodes[addr];
+    endfunction
+
+    function void writew (bit [31:0] addr, logic [31:0] data, logic[3:0] be);
+        if(be[0])
+            this.ram[addr][7:0] = data[7:0];
+        if(be[1])
+            this.ram[addr][15:8] = data[15:8];
+        if(be[2])
+            this.ram[addr][23:16] = data[23:16];
+        if(be[3])
+            this.ram[addr][31:24] = data[31:24];
+    endfunction
+endclass
+
+endpackage

test_benches/taiga_tb.sv

@@ -0,0 +1,328 @@
+/*
+ * Copyright © 2017 Eric Matthews,  Lesley Shannon
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Initial code developed under the supervision of Dr. Lesley Shannon,
+ * Reconfigurable Computing Lab, Simon Fraser University.
+ *
+ * Author(s):
+ *             Eric Matthews <ematthew@sfu.ca>
+ */
+
+`timescale 1ns/1ns
+
+import tb_tools::*;
+import taiga_config::*;
+import taiga_types::*;
+import l2_config_and_types::*;
+
+`define  MEMORY_FILE  "/home/ematthew/taiga/examples/zedboard/dhrystone.riscv.sim_init"
+`define  UART_LOG  "/home/ematthew/uart.log"
+
+module taiga_tb ( );
+
+    logic simulator_clk;
+    logic simulator_resetn;
+
+    //axi block diagram inputs
+    logic axi_clk;
+    logic resetn; 
+    logic sin;
+    
+    //AXI memory
+    logic [31:0]axi_araddr;
+    logic [1:0]axi_arburst;
+    logic [3:0]axi_arcache;
+    logic [5:0]axi_arid;
+    logic [7:0]axi_arlen;
+    logic [0:0]axi_arlock;
+    logic [2:0]axi_arprot;
+    logic [3:0]axi_arqos;
+    logic axi_arready;
+    logic [3:0]axi_arregion;
+    logic [2:0]axi_arsize;
+    logic axi_arvalid;
+    logic [31:0]axi_awaddr;
+    logic [1:0]axi_awburst;
+    logic [3:0]axi_awcache;
+    logic [5:0]axi_awid;
+    logic [7:0]axi_awlen;
+    logic [0:0]axi_awlock;
+    logic [2:0]axi_awprot;
+    logic [3:0]axi_awqos;
+    logic axi_awready;
+    logic [3:0]axi_awregion;
+    logic [2:0]axi_awsize;
+    logic axi_awvalid;
+    logic [5:0]axi_bid;
+    logic axi_bready;
+    logic [1:0]axi_bresp;
+    logic axi_bvalid;
+    logic [31:0]axi_rdata;
+    logic [5:0]axi_rid;
+    logic axi_rlast;
+    logic axi_rready;
+    logic [1:0]axi_rresp;
+    logic axi_rvalid;
+    logic [31:0]axi_wdata;
+    logic axi_wlast;
+    logic axi_wready;
+    logic [3:0]axi_wstrb;
+    logic axi_wvalid;
+    logic [5:0]axi_wid;
+
+
+    axi_interface ddr_axi();
+    
+    logic [31:0]mem_axi_araddr;
+    logic [1:0]mem_axi_arburst;
+    logic [3:0]mem_axi_arcache;
+    logic [5:0]mem_axi_arid;
+    logic [7:0]mem_axi_arlen;
+    logic [0:0]mem_axi_arlock;
+    logic [2:0]mem_axi_arprot;
+    logic [3:0]mem_axi_arqos;
+    logic mem_axi_arready;
+    logic [3:0]mem_axi_arregion;
+    logic [2:0]mem_axi_arsize;
+    logic mem_axi_arvalid;
+    logic [31:0]mem_axi_awaddr;
+    logic [1:0]mem_axi_awburst;
+    logic [3:0]mem_axi_awcache;
+    logic [5:0]mem_axi_awid;
+    logic [7:0]mem_axi_awlen;
+    logic [0:0]mem_axi_awlock;
+    logic [2:0]mem_axi_awprot;
+    logic [3:0]mem_axi_awqos;
+    logic mem_axi_awready;
+    logic [3:0]mem_axi_awregion;
+    logic [2:0]mem_axi_awsize;
+    logic mem_axi_awvalid;
+    logic [5:0]mem_axi_bid;
+    logic mem_axi_bready;
+    logic [1:0]mem_axi_bresp;
+    logic mem_axi_bvalid;
+    logic [31:0]mem_axi_rdata;
+    logic [5:0]mem_axi_rid;
+    logic mem_axi_rlast;
+    logic mem_axi_rready;
+    logic [1:0]mem_axi_rresp;
+    logic mem_axi_rvalid;
+    logic [31:0]mem_axi_wdata;
+    logic mem_axi_wlast;
+    logic mem_axi_wready;
+    logic [3:0]mem_axi_wstrb;
+    logic mem_axi_wvalid;
+        logic [5:0] mem_axi_wid;
+    
+    
+    //AXI bus
+    logic ACLK;
+    logic [12:0]bus_axi_araddr;
+    logic bus_axi_arready;
+    logic bus_axi_arvalid;
+    logic [12:0]bus_axi_awaddr;
+    logic bus_axi_awready;
+    logic bus_axi_awvalid;
+    logic bus_axi_bready;
+    logic [1:0]bus_axi_bresp;
+    logic bus_axi_bvalid;
+    logic [31:0]bus_axi_rdata;
+    logic bus_axi_rready;
+    logic [1:0]bus_axi_rresp;
+    logic bus_axi_rvalid;
+    logic [31:0]bus_axi_wdata;
+    logic bus_axi_wready;
+    logic [3:0]bus_axi_wstrb;
+    logic bus_axi_wvalid;
+  
+    //axi block diagram outputs
+    logic processor_reset;
+    logic processor_clk;
+    logic sout;
+    
+    logic clk;
+    logic rst;
+
+
+    //*****************************
+        
+    assign axi_clk = simulator_clk;
+    assign resetn = simulator_resetn;
+        
+    assign clk = simulator_clk;
+    assign rst = processor_reset;
+                
+    bram_interface instruction_bram();
+    bram_interface data_bram();
+    
+    axi_interface m_axi();
+    avalon_interface m_avalon();
+
+    l2_requester_interface l2[L2_NUM_PORTS-1:0]();
+    l2_memory_interface mem();
+        
+
+    logic interrupt;
+    
+    logic[31:0] dec_pc_debug;
+    logic[31:0] if2_pc_debug;
+    
+    integer output_file;
+    
+    assign l2[1].request_push = 0;
+    assign l2[1].wr_data_push = 0;
+    assign l2[1].inv_ack = l2[1].inv_valid;
+    assign l2[1].rd_data_ack = l2[1].rd_data_valid;
+    
+    sim_mem simulation_mem = new();
+
+    
+    //RAM Block
+    always_ff @(posedge processor_clk) begin
+      if (instruction_bram.en) begin
+        instruction_bram.data_out <= simulation_mem.readw(instruction_bram.addr);
+        simulation_mem.writew(instruction_bram.addr,instruction_bram.data_in, instruction_bram.be);
+      end
+    end
+    
+    always_ff @(posedge processor_clk) begin
+      if (data_bram.en) begin
+        data_bram.data_out <= simulation_mem.readw(data_bram.addr);
+        simulation_mem.writew(data_bram.addr,data_bram.data_in, data_bram.be);
+      end
+    end
+        
+    taiga uut (.*, .l2(l2[0]));
+    
+    design_2 infra(.*);
+
+    l2_arbiter l2_arb (.*, .request(l2));
+        
+    axi_to_arb l2_to_mem (.*, .l2(mem));
+    
+    axi_mem_sim #(`MEMORY_FILE) ddr_interface (.*, .axi(ddr_axi), .if_pc(if2_pc_debug), .dec_pc(dec_pc_debug));
+    
+    always
+        #1 simulator_clk = ~simulator_clk;
+    
+    initial begin
+        simulator_clk = 0;
+        interrupt = '0;
+        simulator_resetn = 0;
+                
+        simulation_mem.load_program(`MEMORY_FILE, RESET_VEC);
+        
+        output_file = $fopen(`UART_LOG, "w");
+        if (output_file == 0) begin
+            $error ("couldn't open log file");
+            $finish;
+        end
+        do_reset();
+
+        #1200000;
+        $fclose(output_file);
+        $finish;
+    end
+    
+    task do_reset;
+    begin
+        simulator_resetn = 1'b0;
+        #500 simulator_resetn = 1'b1;
+    end
+    endtask
+    
+    
+    assign m_axi.arready = bus_axi_arready;
+    assign bus_axi_arvalid = m_axi.arvalid;
+    assign bus_axi_araddr = m_axi.araddr[12:0];
+    
+
+    //read data
+    assign bus_axi_rready = m_axi.rready;
+    assign m_axi.rvalid = bus_axi_rvalid;
+    assign m_axi.rdata = bus_axi_rdata;
+    assign m_axi.rresp = bus_axi_rresp;
+
+    //Write channel
+    //write address
+    assign m_axi.awready = bus_axi_awready;
+    assign bus_axi_awaddr = m_axi.awaddr[12:0];
+    assign bus_axi_awvalid = m_axi.awvalid;
+    
+
+    //write data
+    assign m_axi.wready = bus_axi_wready;   
+    assign bus_axi_wvalid = m_axi. wvalid;
+    assign bus_axi_wdata = m_axi.wdata;
+    assign bus_axi_wstrb = m_axi.wstrb;
+    
+    //write response
+    assign bus_axi_bready = m_axi.bready;
+    assign m_axi.bvalid = bus_axi_bvalid;
+    assign m_axi.bresp = bus_axi_bresp;
+    
+    
+    
+    
+    
+    
+    
+    assign ddr_axi.araddr = mem_axi_araddr;
+    assign ddr_axi.arburst = mem_axi_arburst;
+    assign ddr_axi.arcache = mem_axi_arcache;
+    assign ddr_axi.arid = mem_axi_arid;
+    assign ddr_axi.arlen = mem_axi_arlen;
+    assign mem_axi_arready = ddr_axi.arready;
+    assign ddr_axi.arsize = mem_axi_arsize;
+    assign ddr_axi.arvalid = mem_axi_arvalid;
+    
+    assign ddr_axi.awaddr = mem_axi_awaddr;
+    assign ddr_axi.awburst = mem_axi_awburst;
+    assign ddr_axi.awcache = mem_axi_awcache;
+    assign ddr_axi.awid = mem_axi_awid;
+    assign ddr_axi.awlen = mem_axi_awlen;
+    assign mem_axi_awready = ddr_axi.awready;
+    assign ddr_axi.awvalid = mem_axi_awvalid;
+    
+    assign mem_axi_bid = ddr_axi.bid;
+    assign ddr_axi.bready = mem_axi_bready;
+    assign mem_axi_bresp = ddr_axi.bresp;
+    assign mem_axi_bvalid = ddr_axi.bvalid;
+    
+    assign mem_axi_rdata = ddr_axi.rdata;
+    assign mem_axi_rid = ddr_axi.rid;
+    assign mem_axi_rlast = ddr_axi.rlast;
+    assign ddr_axi.rready = mem_axi_rready;
+    assign mem_axi_rresp = ddr_axi.rresp;
+    assign mem_axi_rvalid = ddr_axi.rvalid;
+    
+    assign ddr_axi.wdata = mem_axi_wdata;
+    assign ddr_axi.wlast = mem_axi_wlast;
+    assign mem_axi_wready = ddr_axi.wready;
+    assign ddr_axi.wstrb = mem_axi_wstrb;
+    assign ddr_axi.wvalid = mem_axi_wvalid;
+
+
+    //Capture writes to UART
+    always_ff @(posedge processor_clk) begin
+      if (m_axi.wvalid && bus_axi_wready && m_axi.awaddr[13:0] == 4096) begin
+            $fwrite(output_file, "%c",m_axi.wdata[7:0]);
+      end
+    end
+    
+    
+    assign sin = 0;
+
+endmodule

test_benches/taiga_tb.wcfg

@@ -0,0 +1,719 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="taiga_tb_behav.wdb" id="1">
+         <top_modules>
+            <top_module name="glbl" />
+            <top_module name="l2_config_and_types" />
+            <top_module name="taiga_config" />
+            <top_module name="taiga_tb" />
+            <top_module name="taiga_types" />
+            <top_module name="tb_tools" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <zoom_setting>
+      <ZoomStartTime time="0fs"></ZoomStartTime>
+      <ZoomEndTime time="123200000001fs"></ZoomEndTime>
+      <Cursor1Time time="600000000fs"></Cursor1Time>
+   </zoom_setting>
+   <column_width_setting>
+      <NameColumnWidth column_width="233"></NameColumnWidth>
+      <ValueColumnWidth column_width="94"></ValueColumnWidth>
+   </column_width_setting>
+   <WVObjectSize size="170" />
+   <wvobject type="logic" fp_name="/taiga_tb/clk">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/rst">
+      <obj_property name="ElementShortName">rst</obj_property>
+      <obj_property name="ObjectShortName">rst</obj_property>
+   </wvobject>
+   <wvobject fp_name="divider7358" type="divider">
+      <obj_property name="label">Fetch</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/fetch_block/next_pc">
+      <obj_property name="ElementShortName">next_pc[31:0]</obj_property>
+      <obj_property name="ObjectShortName">next_pc[31:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/fetch_block/if_pc">
+      <obj_property name="ElementShortName">if_pc[31:0]</obj_property>
+      <obj_property name="ObjectShortName">if_pc[31:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/bt_block/predicted_pc">
+      <obj_property name="ElementShortName">predicted_pc[31:0]</obj_property>
+      <obj_property name="ObjectShortName">predicted_pc[31:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/bt/use_prediction">
+      <obj_property name="ElementShortName">use_prediction</obj_property>
+      <obj_property name="ObjectShortName">use_prediction</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/bt/use_ras">
+      <obj_property name="ElementShortName">use_ras</obj_property>
+      <obj_property name="ObjectShortName">use_ras</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/ras_block/ras/push">
+      <obj_property name="ElementShortName">push</obj_property>
+      <obj_property name="ObjectShortName">push</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/ras_block/ras/pop">
+      <obj_property name="ElementShortName">pop</obj_property>
+      <obj_property name="ObjectShortName">pop</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/ras_block/ras/new_addr">
+      <obj_property name="ElementShortName">new_addr[31:0]</obj_property>
+      <obj_property name="ObjectShortName">new_addr[31:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/ras_block/ras/addr">
+      <obj_property name="ElementShortName">addr[31:0]</obj_property>
+      <obj_property name="ObjectShortName">addr[31:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/ras_block/ras/valid">
+      <obj_property name="ElementShortName">valid</obj_property>
+      <obj_property name="ObjectShortName">valid</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/ras_block/read_index">
+      <obj_property name="ElementShortName">read_index[2:0]</obj_property>
+      <obj_property name="ObjectShortName">read_index[2:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/ras_block/write_index">
+      <obj_property name="ElementShortName">write_index[2:0]</obj_property>
+      <obj_property name="ObjectShortName">write_index[2:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/ddr_interface/if_inst_text">
+      <obj_property name="ElementShortName">if_inst_text[0:511]</obj_property>
+      <obj_property name="ObjectShortName">if_inst_text[0:511]</obj_property>
+      <obj_property name="Radix">ASCIIRADIX</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/fetch_block/cache_access">
+      <obj_property name="ElementShortName">cache_access</obj_property>
+      <obj_property name="ObjectShortName">cache_access</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/fetch_block/bram_access">
+      <obj_property name="ElementShortName">bram_access</obj_property>
+      <obj_property name="ObjectShortName">bram_access</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/fetch_block/mem_ready">
+      <obj_property name="ElementShortName">mem_ready</obj_property>
+      <obj_property name="ObjectShortName">mem_ready</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/fetch_block/new_mem_request">
+      <obj_property name="ElementShortName">new_mem_request</obj_property>
+      <obj_property name="ObjectShortName">new_mem_request</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/fetch_block/bt/flush">
+      <obj_property name="ElementShortName">flush</obj_property>
+      <obj_property name="ObjectShortName">flush</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/fetch_block/delayed_flush">
+      <obj_property name="ElementShortName">delayed_flush</obj_property>
+      <obj_property name="ObjectShortName">delayed_flush</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/fetch_block/exception">
+      <obj_property name="ElementShortName">exception</obj_property>
+      <obj_property name="ObjectShortName">exception</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/fetch_block/mem_valid">
+      <obj_property name="ElementShortName">mem_valid</obj_property>
+      <obj_property name="ObjectShortName">mem_valid</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/fetch_block/stage2_valid">
+      <obj_property name="ElementShortName">stage2_valid</obj_property>
+      <obj_property name="ObjectShortName">stage2_valid</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/fetch_block/pc_valid">
+      <obj_property name="ElementShortName">pc_valid</obj_property>
+      <obj_property name="ObjectShortName">pc_valid</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/bt/use_prediction">
+      <obj_property name="ElementShortName">use_prediction</obj_property>
+      <obj_property name="ObjectShortName">use_prediction</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/ib/full">
+      <obj_property name="ElementShortName">full</obj_property>
+      <obj_property name="ObjectShortName">full</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/ib/early_full">
+      <obj_property name="ElementShortName">early_full</obj_property>
+      <obj_property name="ObjectShortName">early_full</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/ib/data_in">
+      <obj_property name="ElementShortName">data_in</obj_property>
+      <obj_property name="ObjectShortName">data_in</obj_property>
+   </wvobject>
+   <wvobject fp_name="divider7368" type="divider">
+      <obj_property name="label">I Cache</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/fetch_block/\fetch_sub[1] /stage1_addr">
+      <obj_property name="ElementShortName">stage1_addr[31:0]</obj_property>
+      <obj_property name="ObjectShortName">stage1_addr[31:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/fetch_block/\fetch_sub[1] /stage2_addr">
+      <obj_property name="ElementShortName">stage2_addr[31:0]</obj_property>
+      <obj_property name="ObjectShortName">stage2_addr[31:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/fetch_block/\fetch_sub[1] /data_out">
+      <obj_property name="ElementShortName">data_out[31:0]</obj_property>
+      <obj_property name="ObjectShortName">data_out[31:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/fetch_block/\fetch_sub[1] /data_valid">
+      <obj_property name="ElementShortName">data_valid</obj_property>
+      <obj_property name="ObjectShortName">data_valid</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/fetch_block/new_issue">
+      <obj_property name="ElementShortName">new_issue</obj_property>
+      <obj_property name="ObjectShortName">new_issue</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/fetch_block/\fetch_sub[1] /ready">
+      <obj_property name="ElementShortName">ready</obj_property>
+      <obj_property name="ObjectShortName">ready</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/fetch_block/\fetch_sub[1] /new_request">
+      <obj_property name="ElementShortName">new_request</obj_property>
+      <obj_property name="ObjectShortName">new_request</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/fetch_block/l1_response/data_valid">
+      <obj_property name="ElementShortName">data_valid</obj_property>
+      <obj_property name="ObjectShortName">data_valid</obj_property>
+   </wvobject>
+   <wvobject fp_name="divider7359" type="divider">
+      <obj_property name="label">Decode/Issue</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/clk">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/dec_pc">
+      <obj_property name="ElementShortName">dec_pc[31:0]</obj_property>
+      <obj_property name="ObjectShortName">dec_pc[31:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/ddr_interface/dec_inst_text">
+      <obj_property name="ElementShortName">dec_inst_text[0:511]</obj_property>
+      <obj_property name="ObjectShortName">dec_inst_text[0:511]</obj_property>
+      <obj_property name="Radix">ASCIIRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/decode_block/ib/data_out.instruction">
+      <obj_property name="ElementShortName">.instruction[31:0]</obj_property>
+      <obj_property name="ObjectShortName">.instruction[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/instruction_complete">
+      <obj_property name="ElementShortName">instruction_complete</obj_property>
+      <obj_property name="ObjectShortName">instruction_complete</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/decode_block/issue_valid">
+      <obj_property name="ElementShortName">issue_valid</obj_property>
+      <obj_property name="ObjectShortName">issue_valid</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/decode_block/operands_ready">
+      <obj_property name="ElementShortName">operands_ready</obj_property>
+      <obj_property name="ObjectShortName">operands_ready</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/decode_block/advance">
+      <obj_property name="ElementShortName">advance</obj_property>
+      <obj_property name="ObjectShortName">advance</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/write_back_mux/inorder">
+      <obj_property name="ElementShortName">inorder</obj_property>
+      <obj_property name="ObjectShortName">inorder</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/bt/flush">
+      <obj_property name="ElementShortName">flush</obj_property>
+      <obj_property name="ObjectShortName">flush</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/register_file_block/rs1_feedforward">
+      <obj_property name="ElementShortName">rs1_feedforward</obj_property>
+      <obj_property name="ObjectShortName">rs1_feedforward</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/register_file_block/rs2_feedforward">
+      <obj_property name="ElementShortName">rs2_feedforward</obj_property>
+      <obj_property name="ObjectShortName">rs2_feedforward</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/decode_block/uses_rs1">
+      <obj_property name="ElementShortName">uses_rs1</obj_property>
+      <obj_property name="ObjectShortName">uses_rs1</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/decode_block/uses_rs2">
+      <obj_property name="ElementShortName">uses_rs2</obj_property>
+      <obj_property name="ObjectShortName">uses_rs2</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/decode_block/uses_rd">
+      <obj_property name="ElementShortName">uses_rd</obj_property>
+      <obj_property name="ObjectShortName">uses_rd</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/decode_block/future_rd_addr">
+      <obj_property name="ElementShortName">future_rd_addr[4:0]</obj_property>
+      <obj_property name="ObjectShortName">future_rd_addr[4:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/bt_block/miss_predict_br">
+      <obj_property name="ElementShortName">miss_predict_br[31:0]</obj_property>
+      <obj_property name="ObjectShortName">miss_predict_br[31:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/bt_block/miss_predict_ret">
+      <obj_property name="ElementShortName">miss_predict_ret[31:0]</obj_property>
+      <obj_property name="ObjectShortName">miss_predict_ret[31:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="divider3002" type="divider">
+      <obj_property name="label">Register File</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/register_file_block/register">
+      <obj_property name="ElementShortName">register[0:31][31:0]</obj_property>
+      <obj_property name="ObjectShortName">register[0:31][31:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/register_file_block/inuse">
+      <obj_property name="ElementShortName">inuse[0:31]</obj_property>
+      <obj_property name="ObjectShortName">inuse[0:31]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/register_file_block/in_use_by">
+      <obj_property name="ElementShortName">in_use_by[0:31][1:0]</obj_property>
+      <obj_property name="ObjectShortName">in_use_by[0:31][1:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/write_back_mux/early_done">
+      <obj_property name="ElementShortName">early_done[5:0]</obj_property>
+      <obj_property name="ObjectShortName">early_done[5:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="divider3001" type="divider">
+      <obj_property name="label">WB &amp; Inst queue</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/inst_queue/shift_reg">
+      <obj_property name="ElementShortName">shift_reg[3:0][9:0]</obj_property>
+      <obj_property name="ObjectShortName">shift_reg[3:0][9:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/write_back_mux/unit_id">
+      <obj_property name="ElementShortName">unit_id[2:0]</obj_property>
+      <obj_property name="ObjectShortName">unit_id[2:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/write_back_mux/iq_index">
+      <obj_property name="ElementShortName">iq_index[1:0]</obj_property>
+      <obj_property name="ObjectShortName">iq_index[1:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="divider3000" type="divider">
+      <obj_property name="label">LS Unit</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/clk">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/load_store_unit_block/ls_inputs">
+      <obj_property name="ElementShortName">ls_inputs</obj_property>
+      <obj_property name="ObjectShortName">ls_inputs</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/load_store_unit_block/stage1">
+      <obj_property name="ElementShortName">stage1</obj_property>
+      <obj_property name="ObjectShortName">stage1</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/load_store_unit_block/d_inputs">
+      <obj_property name="ElementShortName">d_inputs</obj_property>
+      <obj_property name="ObjectShortName">d_inputs</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/load_store_unit_block/issue_request">
+      <obj_property name="ElementShortName">issue_request</obj_property>
+      <obj_property name="ObjectShortName">issue_request</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/load_store_unit_block/load_complete">
+      <obj_property name="ElementShortName">load_complete</obj_property>
+      <obj_property name="ObjectShortName">load_complete</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/load_store_unit_block/bus_access">
+      <obj_property name="ElementShortName">bus_access</obj_property>
+      <obj_property name="ObjectShortName">bus_access</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/load_store_unit_block/bram_access">
+      <obj_property name="ElementShortName">bram_access</obj_property>
+      <obj_property name="ObjectShortName">bram_access</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/load_store_unit_block/cache_access">
+      <obj_property name="ElementShortName">cache_access</obj_property>
+      <obj_property name="ObjectShortName">cache_access</obj_property>
+   </wvobject>
+   <wvobject fp_name="divider2999" type="divider">
+      <obj_property name="label">DCache</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/clk">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/load_store_unit_block/\ls_sub[2] /data_valid">
+      <obj_property name="ElementShortName">data_valid</obj_property>
+      <obj_property name="ObjectShortName">data_valid</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/load_store_unit_block/\ls_sub[2] /ready">
+      <obj_property name="ElementShortName">ready</obj_property>
+      <obj_property name="ObjectShortName">ready</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/load_store_unit_block/\ls_sub[2] /new_request">
+      <obj_property name="ElementShortName">new_request</obj_property>
+      <obj_property name="ObjectShortName">new_request</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/load_store_unit_block/\genblk3.data_cache /l1_request/ack">
+      <obj_property name="ElementShortName">ack</obj_property>
+      <obj_property name="ObjectShortName">ack</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/load_store_unit_block/\ls_sub[2] /ack">
+      <obj_property name="ElementShortName">ack</obj_property>
+      <obj_property name="ObjectShortName">ack</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/load_store_unit_block/\genblk3.data_cache /word_count">
+      <obj_property name="ElementShortName">word_count[2:0]</obj_property>
+      <obj_property name="ObjectShortName">word_count[2:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/load_store_unit_block/final_load_data">
+      <obj_property name="ElementShortName">final_load_data[31:0]</obj_property>
+      <obj_property name="ObjectShortName">final_load_data[31:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/load_store_unit_block/wb_fifo/full">
+      <obj_property name="ElementShortName">full</obj_property>
+      <obj_property name="ObjectShortName">full</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/load_store_unit_block/load_attributes/data_out">
+      <obj_property name="ElementShortName">data_out[6:0]</obj_property>
+      <obj_property name="ObjectShortName">data_out[6:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/load_store_unit_block/load_attributes/valid">
+      <obj_property name="ElementShortName">valid</obj_property>
+      <obj_property name="ObjectShortName">valid</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/load_store_unit_block/\genblk3.data_cache /l1_request/addr">
+      <obj_property name="ElementShortName">addr[31:0]</obj_property>
+      <obj_property name="ObjectShortName">addr[31:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/\genblk1.arb /l2/requester/request.addr">
+      <obj_property name="ElementShortName">.addr[29:0]</obj_property>
+      <obj_property name="ObjectShortName">.addr[29:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/load_store_unit_block/\genblk3.data_cache /l1_request/data">
+      <obj_property name="ElementShortName">data[31:0]</obj_property>
+      <obj_property name="ObjectShortName">data[31:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/load_store_unit_block/\genblk3.data_cache /l1_request/rnw">
+      <obj_property name="ElementShortName">rnw</obj_property>
+      <obj_property name="ObjectShortName">rnw</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/load_store_unit_block/\genblk3.data_cache /l1_request/be">
+      <obj_property name="ElementShortName">be[3:0]</obj_property>
+      <obj_property name="ObjectShortName">be[3:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/load_store_unit_block/\genblk3.data_cache /l1_request/size">
+      <obj_property name="ElementShortName">size[4:0]</obj_property>
+      <obj_property name="ObjectShortName">size[4:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/load_store_unit_block/\genblk3.data_cache /l1_request/is_amo">
+      <obj_property name="ElementShortName">is_amo</obj_property>
+      <obj_property name="ObjectShortName">is_amo</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/uut/load_store_unit_block/\genblk3.data_cache /l1_request/amo">
+      <obj_property name="ElementShortName">amo[4:0]</obj_property>
+      <obj_property name="ObjectShortName">amo[4:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/load_store_unit_block/\genblk3.data_cache /l1_request/request">
+      <obj_property name="ElementShortName">request</obj_property>
+      <obj_property name="ObjectShortName">request</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/uut/load_store_unit_block/\genblk3.data_cache /l1_request/ack">
+      <obj_property name="ElementShortName">ack</obj_property>
+      <obj_property name="ObjectShortName">ack</obj_property>
+   </wvobject>
+   <wvobject fp_name="divider2998" type="divider">
+      <obj_property name="label">L2</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/l2_arb/\request[0] /request">
+      <obj_property name="ElementShortName">request</obj_property>
+      <obj_property name="ObjectShortName">request</obj_property>
+      <obj_property name="isExpanded"></obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_arb/\request[0] /request_push">
+      <obj_property name="ElementShortName">request_push</obj_property>
+      <obj_property name="ObjectShortName">request_push</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/l2_arb/requests">
+      <obj_property name="ElementShortName">requests[1:0]</obj_property>
+      <obj_property name="ObjectShortName">requests[1:0]</obj_property>
+      <obj_property name="isExpanded"></obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_arb/\request[0] /request_push">
+      <obj_property name="ElementShortName">request_push</obj_property>
+      <obj_property name="ObjectShortName">request_push</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/l2_arb/\genblk1[0].input_fifo /\genblk1.genblk1.write_index ">
+      <obj_property name="ElementShortName">\genblk1.genblk1.write_index [1:0]</obj_property>
+      <obj_property name="ObjectShortName">\genblk1.genblk1.write_index [1:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/l2_arb/\genblk1[0].input_fifo /\genblk1.genblk1.read_index ">
+      <obj_property name="ElementShortName">\genblk1.genblk1.read_index [1:0]</obj_property>
+      <obj_property name="ObjectShortName">\genblk1.genblk1.read_index [1:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/l2_arb/\genblk1[0].input_fifo /\genblk1.genblk1.lut_ram ">
+      <obj_property name="ElementShortName">\genblk1.genblk1.lut_ram [3:0][42:0]</obj_property>
+      <obj_property name="ObjectShortName">\genblk1.genblk1.lut_ram [3:0][42:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/l2_arb/arb/requests">
+      <obj_property name="ElementShortName">requests[1:0]</obj_property>
+      <obj_property name="ObjectShortName">requests[1:0]</obj_property>
+      <obj_property name="isExpanded"></obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/l2_arb/arb/grantee_i">
+      <obj_property name="ElementShortName">grantee_i[0:0]</obj_property>
+      <obj_property name="ObjectShortName">grantee_i[0:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/l2_arb/arb/grantee_v">
+      <obj_property name="ElementShortName">grantee_v[1:0]</obj_property>
+      <obj_property name="ObjectShortName">grantee_v[1:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_arb/arb/grantee_valid">
+      <obj_property name="ElementShortName">grantee_valid</obj_property>
+      <obj_property name="ObjectShortName">grantee_valid</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_arb/arb/strobe">
+      <obj_property name="ElementShortName">strobe</obj_property>
+      <obj_property name="ObjectShortName">strobe</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_arb/\input_fifos[0] /pop">
+      <obj_property name="ElementShortName">pop</obj_property>
+      <obj_property name="ObjectShortName">pop</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_arb/\request[0] /request_full">
+      <obj_property name="ElementShortName">request_full</obj_property>
+      <obj_property name="ObjectShortName">request_full</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_arb/advance">
+      <obj_property name="ElementShortName">advance</obj_property>
+      <obj_property name="ObjectShortName">advance</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/l2_arb/\request[0] /inv_addr">
+      <obj_property name="ElementShortName">inv_addr[31:2]</obj_property>
+      <obj_property name="ObjectShortName">inv_addr[31:2]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_arb/\request[0] /inv_valid">
+      <obj_property name="ElementShortName">inv_valid</obj_property>
+      <obj_property name="ObjectShortName">inv_valid</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_arb/\request[0] /inv_ack">
+      <obj_property name="ElementShortName">inv_ack</obj_property>
+      <obj_property name="ObjectShortName">inv_ack</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_arb/\request[0] /con_result">
+      <obj_property name="ElementShortName">con_result</obj_property>
+      <obj_property name="ObjectShortName">con_result</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_arb/\request[0] /con_valid">
+      <obj_property name="ElementShortName">con_valid</obj_property>
+      <obj_property name="ObjectShortName">con_valid</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/l2_arb/\request[0] /wr_data">
+      <obj_property name="ElementShortName">wr_data[31:0]</obj_property>
+      <obj_property name="ObjectShortName">wr_data[31:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_arb/\request[0] /wr_data_push">
+      <obj_property name="ElementShortName">wr_data_push</obj_property>
+      <obj_property name="ObjectShortName">wr_data_push</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_arb/\request[0] /data_full">
+      <obj_property name="ElementShortName">data_full</obj_property>
+      <obj_property name="ObjectShortName">data_full</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/l2_arb/\request[0] /rd_data">
+      <obj_property name="ElementShortName">rd_data[31:0]</obj_property>
+      <obj_property name="ObjectShortName">rd_data[31:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/l2_arb/\request[0] /rd_sub_id">
+      <obj_property name="ElementShortName">rd_sub_id[1:0]</obj_property>
+      <obj_property name="ObjectShortName">rd_sub_id[1:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_arb/\request[0] /rd_data_valid">
+      <obj_property name="ElementShortName">rd_data_valid</obj_property>
+      <obj_property name="ObjectShortName">rd_data_valid</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_arb/\request[0] /rd_data_ack">
+      <obj_property name="ElementShortName">rd_data_ack</obj_property>
+      <obj_property name="ObjectShortName">rd_data_ack</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/l2_arb/mem/request">
+      <obj_property name="ElementShortName">request</obj_property>
+      <obj_property name="ObjectShortName">request</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_arb/mem/request_pop">
+      <obj_property name="ElementShortName">request_pop</obj_property>
+      <obj_property name="ObjectShortName">request_pop</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_arb/mem/request_valid">
+      <obj_property name="ElementShortName">request_valid</obj_property>
+      <obj_property name="ObjectShortName">request_valid</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_arb/mem/abort">
+      <obj_property name="ElementShortName">abort</obj_property>
+      <obj_property name="ObjectShortName">abort</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/l2_arb/mem/wr_data">
+      <obj_property name="ElementShortName">wr_data[31:0]</obj_property>
+      <obj_property name="ObjectShortName">wr_data[31:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_arb/mem/wr_data_valid">
+      <obj_property name="ElementShortName">wr_data_valid</obj_property>
+      <obj_property name="ObjectShortName">wr_data_valid</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_arb/mem/wr_data_read">
+      <obj_property name="ElementShortName">wr_data_read</obj_property>
+      <obj_property name="ObjectShortName">wr_data_read</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/l2_arb/mem/rd_data">
+      <obj_property name="ElementShortName">rd_data[31:0]</obj_property>
+      <obj_property name="ObjectShortName">rd_data[31:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/l2_arb/mem/rd_id">
+      <obj_property name="ElementShortName">rd_id[2:0]</obj_property>
+      <obj_property name="ObjectShortName">rd_id[2:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_arb/mem/rd_data_valid">
+      <obj_property name="ElementShortName">rd_data_valid</obj_property>
+      <obj_property name="ObjectShortName">rd_data_valid</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_arb/reserv_valid">
+      <obj_property name="ElementShortName">reserv_valid</obj_property>
+      <obj_property name="ObjectShortName">reserv_valid</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/l2_arb/reserv_request">
+      <obj_property name="ElementShortName">reserv_request</obj_property>
+      <obj_property name="ObjectShortName">reserv_request</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/l2_arb/reserv_id">
+      <obj_property name="ElementShortName">reserv_id[0:0]</obj_property>
+      <obj_property name="ObjectShortName">reserv_id[0:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/l2_arb/reserv_id_v">
+      <obj_property name="ElementShortName">reserv_id_v[1:0]</obj_property>
+      <obj_property name="ObjectShortName">reserv_id_v[1:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/l2_arb/new_attr">
+      <obj_property name="ElementShortName">new_attr</obj_property>
+      <obj_property name="ObjectShortName">new_attr</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/l2_arb/data_attributes_fifo/\genblk1.genblk1.lut_ram ">
+      <obj_property name="ElementShortName">\genblk1.genblk1.lut_ram [15:0][6:0]</obj_property>
+      <obj_property name="ObjectShortName">\genblk1.genblk1.lut_ram [15:0][6:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/l2_arb/data_attributes_fifo/\genblk1.genblk1.read_index ">
+      <obj_property name="ElementShortName">\genblk1.genblk1.read_index [3:0]</obj_property>
+      <obj_property name="ObjectShortName">\genblk1.genblk1.read_index [3:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/l2_arb/data_attributes_fifo/\genblk1.genblk1.write_index ">
+      <obj_property name="ElementShortName">\genblk1.genblk1.write_index [3:0]</obj_property>
+      <obj_property name="ObjectShortName">\genblk1.genblk1.write_index [3:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/l2_arb/current_attr">
+      <obj_property name="ElementShortName">current_attr</obj_property>
+      <obj_property name="ObjectShortName">current_attr</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_arb/data_attributes/valid">
+      <obj_property name="ElementShortName">valid</obj_property>
+      <obj_property name="ObjectShortName">valid</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_arb/data_attributes/push">
+      <obj_property name="ElementShortName">push</obj_property>
+      <obj_property name="ObjectShortName">push</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_arb/data_attributes/pop">
+      <obj_property name="ElementShortName">pop</obj_property>
+      <obj_property name="ObjectShortName">pop</obj_property>
+   </wvobject>
+   <wvobject fp_name="divider2818" type="divider">
+      <obj_property name="label">Mem AXI</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/clk">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/l2_to_mem/axi_araddr">
+      <obj_property name="ElementShortName">axi_araddr[31:0]</obj_property>
+      <obj_property name="ObjectShortName">axi_araddr[31:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_to_mem/axi_arready">
+      <obj_property name="ElementShortName">axi_arready</obj_property>
+      <obj_property name="ObjectShortName">axi_arready</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_to_mem/axi_arvalid">
+      <obj_property name="ElementShortName">axi_arvalid</obj_property>
+      <obj_property name="ObjectShortName">axi_arvalid</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_to_mem/axi_rready">
+      <obj_property name="ElementShortName">axi_rready</obj_property>
+      <obj_property name="ObjectShortName">axi_rready</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_to_mem/axi_rvalid">
+      <obj_property name="ElementShortName">axi_rvalid</obj_property>
+      <obj_property name="ObjectShortName">axi_rvalid</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/l2_to_mem/axi_awburst">
+      <obj_property name="ElementShortName">axi_awburst[1:0]</obj_property>
+      <obj_property name="ObjectShortName">axi_awburst[1:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/l2_to_mem/axi_rdata">
+      <obj_property name="ElementShortName">axi_rdata[31:0]</obj_property>
+      <obj_property name="ObjectShortName">axi_rdata[31:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/l2_to_mem/axi_awaddr">
+      <obj_property name="ElementShortName">axi_awaddr[31:0]</obj_property>
+      <obj_property name="ObjectShortName">axi_awaddr[31:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_to_mem/axi_awready">
+      <obj_property name="ElementShortName">axi_awready</obj_property>
+      <obj_property name="ObjectShortName">axi_awready</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_to_mem/axi_awvalid">
+      <obj_property name="ElementShortName">axi_awvalid</obj_property>
+      <obj_property name="ObjectShortName">axi_awvalid</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_to_mem/axi_wready">
+      <obj_property name="ElementShortName">axi_wready</obj_property>
+      <obj_property name="ObjectShortName">axi_wready</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_to_mem/axi_wvalid">
+      <obj_property name="ElementShortName">axi_wvalid</obj_property>
+      <obj_property name="ObjectShortName">axi_wvalid</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_to_mem/axi_wlast">
+      <obj_property name="ElementShortName">axi_wlast</obj_property>
+      <obj_property name="ObjectShortName">axi_wlast</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/l2_to_mem/axi_wdata">
+      <obj_property name="ElementShortName">axi_wdata[31:0]</obj_property>
+      <obj_property name="ObjectShortName">axi_wdata[31:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/l2_to_mem/axi_wstrb">
+      <obj_property name="ElementShortName">axi_wstrb[3:0]</obj_property>
+      <obj_property name="ObjectShortName">axi_wstrb[3:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_to_mem/write_in_progress">
+      <obj_property name="ElementShortName">write_in_progress</obj_property>
+      <obj_property name="ObjectShortName">write_in_progress</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/taiga_tb/l2_to_mem/write_transfer_complete">
+      <obj_property name="ElementShortName">write_transfer_complete</obj_property>
+      <obj_property name="ObjectShortName">write_transfer_complete</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/ddr_interface/write_request_count">
+      <obj_property name="ElementShortName">write_request_count[47:0]</obj_property>
+      <obj_property name="ObjectShortName">write_request_count[47:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/taiga_tb/ddr_interface/read_request_count">
+      <obj_property name="ElementShortName">read_request_count[47:0]</obj_property>
+      <obj_property name="ObjectShortName">read_request_count[47:0]</obj_property>
+   </wvobject>
+</wave_config>

tools/taiga_binary_converter.py

@@ -0,0 +1,122 @@
+#
+#  Copyright © 2017 Eric Matthews,  Lesley Shannon
+# 
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+# 
+#  http://www.apache.org/licenses/LICENSE-2.0
+# 
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+# 
+#  Initial code developed under the supervision of Dr. Lesley Shannon,
+#  Reconfigurable Computing Lab, Simon Fraser University.
+# 
+#  Author(s):
+#             Eric Matthews <ematthew@sfu.ca>
+#
+
+import argparse
+import re
+import sys
+import subprocess
+import tempfile
+
+def stringByteSwap(s):
+    pairs = [s[i:i+2] for i in range(0, len(s), 2)]
+    return ''.join(pairs[::-1])
+
+parser = argparse.ArgumentParser(description='Converts binary into init files for simulation and BRAMs')
+
+#objdump prefix
+parser.add_argument('toolPrefix', help='the prefix for objdump')
+
+#base adder required
+parser.add_argument('baseAddr', help='the base address')
+#ram size required
+parser.add_argument('ramSize', help='the ram size')
+
+# input file required
+parser.add_argument('inputFile', help='The executable')
+
+# output file names
+parser.add_argument('outputFile', help='The ram init file')
+parser.add_argument('simFile', help='The sim data file')
+
+parser.add_argument('--quiet', '-q', help='Suppresses diagnostic output ', action="store_true")
+
+args = parser.parse_args()
+
+# open input file
+subprocess.run([args.toolPrefix + 'objdump', '-Dzs', args.inputFile], stdout=open(args.inputFile + '.dumpDzs', "w"))
+subprocess.run([args.toolPrefix + 'objdump', '-d', args.inputFile], stdout=open(args.inputFile + '.dumpd', "w"))
+
+
+try:
+    program_input = open(args.inputFile + '.dumpDzs', 'r')
+    opcode_input = open(args.inputFile + '.dumpd', 'r')
+except IOError:
+    print('Could not open files: ', args.inputFile + '.dumpDzs ', args.inputFile + '.dumpd')
+    sys.exit()
+
+    program_output = args.inputFile + '.bin'
+    sim_output = args.inputFile + '.sim'
+    
+if (args.outputFile) :
+    program_output = args.outputFile
+if (args.simFile) :
+    sim_output = args.simFile
+    
+
+# open output file
+try:
+    program_output = open(program_output, 'w')
+    sim_output = open(sim_output, 'w')
+except IOError:
+    print('Could not create files: ', program_output, sim_output)
+    sys.exit()
+    
+print('array size ', int(int(args.ramSize)/4))
+
+ramData = ['00000000'] * int((int(args.ramSize)/4));
+
+lineRegex = re.compile(r'\s+')
+instLineRegex = re.compile(r'\s+|:\s+')
+dataLineRegex = re.compile(r' [a-f0-9]{8}\s+')
+
+hexRegex = re.compile(r'[a-f0-9]{8}')
+
+#parses the block output format
+for line in program_input:
+    lineContents = lineRegex.split(line)
+
+    if (dataLineRegex.match(line) != None) :
+        index = int((int(lineContents[1],16) - int(args.baseAddr,16))/4)
+
+        for entry in lineContents[2:]: #skip address
+            if (hexRegex.match(entry)) :
+                ramData[index] = stringByteSwap(entry)
+                index+=1
+
+program_output.write('\n'.join(str(line) for line in ramData))
+
+#overwrite instruction entries with instruction info
+#<ins hex> <opcode> <instruction details>...
+for line in opcode_input:
+    lineContents = instLineRegex.split(line)
+    if (hexRegex.match(lineContents[0])) :
+        index = int((int(lineContents[0],16) - int(args.baseAddr,16))/4)
+    
+        for entry in lineContents[1:]: #skip address
+                ramData[index] = lineContents[1] + ' ' + ' '.join(lineContents[2:])
+
+sim_output.write(' --\n'.join(str(line) for line in ramData))
+sim_output.write(' --')
+
+print('Done')
+    
+