mirror of
https://github.com/openhwgroup/cva5.git
synced 2025-04-20 03:57:18 -04:00
verilator cleanups
This commit is contained in:
Eric Matthews
parent
5ba13cf90a
commit
d87f03bf29
6 changed files with 104 additions and 102 deletions
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@ -1,17 +1,20 @@
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#include "axi_ddr_sim.h"
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#include "ddr_page.h"
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#include <stdint.h>
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#include <iostream>
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#include <cstdlib>
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#include <assert.h>
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#include "verilated.h"
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#include "verilated_vcd_c.h"
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#include "Vtaiga_sim.h"
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#include "axi_ddr_sim.h"
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#include "ddr_page.h"
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using namespace std;
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template <class TB>
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axi_ddr_sim<TB>::axi_ddr_sim(TB * tb){
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axi_ddr_sim::axi_ddr_sim(Vtaiga_sim * tb){
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this->tb = tb;
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}
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template <class TB>
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void axi_ddr_sim<TB>::init_signals(){
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void axi_ddr_sim::init_signals(){
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tb->ddr_axi_bresp = 0;
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tb->ddr_axi_bvalid = 0;
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tb->ddr_axi_rvalid = 0;
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@ -22,8 +25,8 @@ void axi_ddr_sim<TB>::init_signals(){
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tb->ddr_axi_rvalid = 0;
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}
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template <class TB>
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axi_ddr_sim<TB>::axi_ddr_sim(string filepath, uint32_t starting_memory_location, int number_of_bytes, TB * tb){
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axi_ddr_sim::axi_ddr_sim(string filepath, uint32_t starting_memory_location, int number_of_bytes, Vtaiga_sim * tb){
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ifstream input_memory_file;
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input_memory_file.open(filepath);
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string line;
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@ -51,8 +54,8 @@ axi_ddr_sim<TB>::axi_ddr_sim(string filepath, uint32_t starting_memory_location,
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}
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template <class TB>
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axi_ddr_sim<TB>::axi_ddr_sim(ifstream & input_memory_file, TB * tb){
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axi_ddr_sim::axi_ddr_sim(ifstream & input_memory_file, Vtaiga_sim * tb){
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string line;
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uint32_t max_pages = DDR_SIZE/PAGE_SIZE;
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@ -84,8 +87,8 @@ axi_ddr_sim<TB>::axi_ddr_sim(ifstream & input_memory_file, TB * tb){
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fflush(stdout);
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}
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template <class TB>
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int axi_ddr_sim<TB>::get_data(uint32_t data_address){
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int axi_ddr_sim::get_data(uint32_t data_address){
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uint32_t starting_address = (data_address / PAGE_SIZE) * PAGE_SIZE;
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if(ddr_pages.count(starting_address)){ //If page exists
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return ddr_pages[starting_address].return_data(data_address%PAGE_SIZE/4);
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@ -97,8 +100,8 @@ int axi_ddr_sim<TB>::get_data(uint32_t data_address){
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return ddr_pages[starting_address].return_data(data_address%PAGE_SIZE/4);
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}
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}
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template <class TB>
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void axi_ddr_sim<TB>::set_data(uint32_t data_address, uint32_t set_data, uint32_t byte_enable){
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void axi_ddr_sim::set_data(uint32_t data_address, uint32_t set_data, uint32_t byte_enable){
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uint32_t data = get_data(data_address);
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uint32_t starting_address = (data_address / PAGE_SIZE) * PAGE_SIZE;
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data = (data & ~byte_enable) | (set_data & byte_enable);
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@ -106,16 +109,16 @@ void axi_ddr_sim<TB>::set_data(uint32_t data_address, uint32_t set_data, uint32
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};
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template <class TB>
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ddr_page axi_ddr_sim<TB>::get_page(uint32_t page_address){
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ddr_page axi_ddr_sim::get_page(uint32_t page_address){
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return ddr_pages[page_address];
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}
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template <class TB>
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void axi_ddr_sim<TB>::parse_input_signals(){
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void axi_ddr_sim::parse_input_signals(){
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//If the master has a write requests
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if(tb->ddr_axi_awvalid && wd_ad_channel_queue.size() < MAX_INFLIGHT_WD_REQ){
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if(tb->ddr_axi_awvalid && wr_ad_channel_queue.size() < MAX_INFLIGHT_WR_REQ){
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AXI_write_address_channel_signals elem{tb->ddr_axi_awaddr, tb->ddr_axi_awlen, tb->ddr_axi_awsize, tb->ddr_axi_awburst,tb->ddr_axi_awcache,tb->ddr_axi_awid};
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wd_ad_channel_queue.push(elem);
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wr_ad_channel_queue.push(elem);
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}
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//If the master has write data
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if(tb->ddr_axi_wvalid){
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@ -128,8 +131,8 @@ void axi_ddr_sim<TB>::parse_input_signals(){
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rd_ad_channel_queue.push(elem);
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}
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}
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template <class TB>
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void axi_ddr_sim<TB>::parse_output_signals(){
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void axi_ddr_sim::parse_output_signals(){
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if(tb->rst ==1){
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tb->ddr_axi_wready = 0;
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tb->ddr_axi_arready = 0;
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@ -149,7 +152,7 @@ void axi_ddr_sim<TB>::parse_output_signals(){
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tb->ddr_axi_wready = 1;
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//Write Req
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if(wd_ad_channel_queue.size() < MAX_INFLIGHT_WD_REQ)
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if(wr_ad_channel_queue.size() < MAX_INFLIGHT_WR_REQ)
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tb->ddr_axi_awready = 1;
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else
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tb->ddr_axi_awready = 0;
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@ -202,8 +205,8 @@ void axi_ddr_sim<TB>::parse_output_signals(){
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}
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}
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}
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template <class TB>
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void axi_ddr_sim<TB>::handle_read_req(){
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void axi_ddr_sim::handle_read_req(){
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if(rd_ad_channel_queue.size() > 0 ){
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if(current_read_parameters.delay_cycles_left == 0){
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AXI_read_data_channel_signals elem;
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@ -241,8 +244,8 @@ void axi_ddr_sim<TB>::handle_read_req(){
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}
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}
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template <class TB>
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void axi_ddr_sim<TB>::handle_write_req(){
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void axi_ddr_sim::handle_write_req(){
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//cout << "w_data_channel_queue size: " << w_data_channel_queue.size() << endl;
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//cout << "current_write_parameters.number_of_bursts_left: " << current_write_parameters.number_of_bursts_left << endl;
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if(w_data_channel_queue.size() > 0 && current_write_parameters.number_of_bursts_left > 0){
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@ -270,15 +273,15 @@ void axi_ddr_sim<TB>::handle_write_req(){
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set_data(current_write_parameters.address, elem.wdata, byte_enable);
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current_write_parameters.number_of_bursts_left--;
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if(wd_ad_channel_queue.front().awburst == 0 ){//FIXED
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if(wr_ad_channel_queue.front().awburst == 0 ){//FIXED
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//do nothing
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}
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else if(wd_ad_channel_queue.front().awburst == 1){ //INCR
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else if(wr_ad_channel_queue.front().awburst == 1){ //INCR
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//Increment Address by number of bytes in a burst(arsize)
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current_write_parameters.address += current_write_parameters.increment;
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}
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else if(wd_ad_channel_queue.front().awburst == 2){ //WRAP
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else if(wr_ad_channel_queue.front().awburst == 2){ //WRAP
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current_write_parameters.address += current_write_parameters.increment;
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if(current_write_parameters.address == current_write_parameters.wrap_boundary + current_write_parameters.number_bytes * current_write_parameters.burst_length){
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current_write_parameters.address = current_write_parameters.wrap_boundary;
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@ -289,7 +292,7 @@ void axi_ddr_sim<TB>::handle_write_req(){
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AXI_write_response_channel_signals resp_elem;
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resp_elem.bid = elem.wid;
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resp_elem.bresp = 0;
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wd_ad_channel_queue.pop();
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wr_ad_channel_queue.pop();
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w_res_channel_queue.push(resp_elem);
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}
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}
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@ -299,8 +302,8 @@ void axi_ddr_sim<TB>::handle_write_req(){
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}
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}
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template <class TB>
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void axi_ddr_sim<TB>::update_current_read_parameters(){
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void axi_ddr_sim::update_current_read_parameters(){
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//If I can serve a new read request
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if(rd_ad_channel_queue.size() > 0 && current_read_parameters.number_of_bursts_left == 0){
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current_read_parameters.address = rd_ad_channel_queue.front().araddr;
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@ -322,32 +325,32 @@ void axi_ddr_sim<TB>::update_current_read_parameters(){
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}
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}
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}
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template <class TB>
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void axi_ddr_sim<TB>::update_current_write_parameters(){
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void axi_ddr_sim::update_current_write_parameters(){
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//If I can serve a new read request
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if(wd_ad_channel_queue.size() > 0 && current_write_parameters.number_of_bursts_left == 0){
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current_write_parameters.address = wd_ad_channel_queue.front().awaddr;
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current_write_parameters.number_of_bursts_left = wd_ad_channel_queue.front().awlen +1;
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if(wr_ad_channel_queue.size() > 0 && current_write_parameters.number_of_bursts_left == 0){
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current_write_parameters.address = wr_ad_channel_queue.front().awaddr;
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current_write_parameters.number_of_bursts_left = wr_ad_channel_queue.front().awlen +1;
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current_write_parameters.delay_cycles_left = write_distribution(generator);
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if(wd_ad_channel_queue.front().awburst == 0 ){//FIXED
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if(wr_ad_channel_queue.front().awburst == 0 ){//FIXED
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current_write_parameters.increment = 0;
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}
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else if(wd_ad_channel_queue.front().awburst == 1){ //INCR
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else if(wr_ad_channel_queue.front().awburst == 1){ //INCR
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//Increment Address by number of bytes in a burst(arsize)
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current_write_parameters.increment = pow(2,wd_ad_channel_queue.front().awsize);
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current_write_parameters.increment = pow(2,wr_ad_channel_queue.front().awsize);
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}
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else if(wd_ad_channel_queue.front().awburst == 2){ //WRAP
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current_write_parameters.increment = pow(2,wd_ad_channel_queue.front().awsize);
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current_write_parameters.number_bytes = pow(2,wd_ad_channel_queue.front().awsize);
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current_write_parameters.burst_length = wd_ad_channel_queue.front().awlen +1;
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else if(wr_ad_channel_queue.front().awburst == 2){ //WRAP
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current_write_parameters.increment = pow(2,wr_ad_channel_queue.front().awsize);
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current_write_parameters.number_bytes = pow(2,wr_ad_channel_queue.front().awsize);
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current_write_parameters.burst_length = wr_ad_channel_queue.front().awlen +1;
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current_write_parameters.wrap_boundary = (int)(current_write_parameters.address/(current_write_parameters.number_bytes * current_write_parameters.burst_length)) * (current_write_parameters.number_bytes * current_write_parameters.burst_length);
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}
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}
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}
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template <class TB>
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void axi_ddr_sim<TB>::step(){
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void axi_ddr_sim::step(){
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parse_input_signals();
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update_current_read_parameters();
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@ -30,8 +30,12 @@
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#include <cmath>
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#include <map>
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#include <random>
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#include "verilated.h"
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#include "verilated_vcd_c.h"
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#include "Vtaiga_sim.h"
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#include "axi_interface.h"
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#include "ddr_page.h"
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using namespace std;
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@ -44,18 +48,18 @@ struct addr_calculation_parameters{
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int number_of_bursts_left;
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int delay_cycles_left;
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};
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template <class TB>
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class axi_ddr_sim{
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public:
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//Functions--------------------------------------------------------------
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//Init instructions-----------------
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axi_ddr_sim();
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//Initialize DDR
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axi_ddr_sim(TB * tb);
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axi_ddr_sim(Vtaiga_sim * tb);
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//Initialize DDR from file
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axi_ddr_sim(string filepath, uint32_t starting_memory_location, int number_of_bytes, TB * tb);
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axi_ddr_sim(ifstream & input_memory_file, TB * tb);
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axi_ddr_sim(string filepath, uint32_t starting_memory_location, int number_of_bytes, Vtaiga_sim * tb);
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axi_ddr_sim(ifstream & input_memory_file, Vtaiga_sim * tb);
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void step();
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int get_data(uint32_t data_address);
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@ -79,7 +83,7 @@ template <class TB>
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uniform_int_distribution<int> write_distribution;
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//Pointers to Data
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map<uint32_t,ddr_page> ddr_pages;
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TB *tb;
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Vtaiga_sim *tb;
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void parse_output_signals();
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void parse_input_signals();
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@ -94,7 +98,7 @@ template <class TB>
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//Read Request Queue
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queue<AXI_read_address_channel_signals> rd_ad_channel_queue;
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//Write Request Queue
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queue<AXI_write_address_channel_signals> wd_ad_channel_queue;
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queue<AXI_write_address_channel_signals> wr_ad_channel_queue;
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//Read Data Queue
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queue<AXI_read_data_channel_signals> r_data_channel_queue;
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//Write Data Queue
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@ -105,5 +109,4 @@ template <class TB>
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unsigned starting_location = 0x80000000;
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};
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#include "axi_ddr_sim.cc"
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#endif
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@ -23,16 +23,14 @@
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#include <iostream>
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#include "TaigaTracer.h"
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//#define TRACE_ON
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template <class TB>
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bool TaigaTracer<TB>::check_instruction_issued(uint32_t inst) {
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bool TaigaTracer::check_instruction_issued(uint32_t inst) {
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return (tb->instruction_data_dec == inst && tb->instruction_issued);
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}
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template <class TB>
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bool TaigaTracer<TB>::has_terminated() {
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bool TaigaTracer::has_terminated() {
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if (check_instruction_issued(ERROR_TERMINATION_NOP)) {
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std::cout << "\n\nError!!!!\n\n";
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@ -45,8 +43,8 @@ bool TaigaTracer<TB>::has_terminated() {
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return false;
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}
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template <class TB>
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bool TaigaTracer<TB>::has_stalled() {
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bool TaigaTracer::has_stalled() {
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if (!tb->instruction_issued) {
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if (stall_count > stall_limit) {
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stall_count = 0;
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@ -62,22 +60,22 @@ bool TaigaTracer<TB>::has_stalled() {
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return false;
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}
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template <class TB>
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void TaigaTracer<TB>::reset_stats() {
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void TaigaTracer::reset_stats() {
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for (int i=0; i < numEvents; i++)
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event_counters[i] = 0;
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}
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template <class TB>
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void TaigaTracer<TB>::update_stats() {
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void TaigaTracer::update_stats() {
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if (collect_stats) {
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for (int i=0; i < numEvents; i++)
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event_counters[i] += tb->taiga_events[i];
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}
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}
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template <class TB>
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void TaigaTracer<TB>::print_stats() {
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void TaigaTracer::print_stats() {
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std::cout << " Taiga trace stats\n";
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std::cout << "--------------------------------------------------------------\n";
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for (int i=0; i < numEvents; i++)
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@ -87,8 +85,8 @@ void TaigaTracer<TB>::print_stats() {
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}
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template <class TB>
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void TaigaTracer<TB>::reset() {
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void TaigaTracer::reset() {
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tb->clk = 0;
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tb->rst = 1;
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for (int i=0; i <reset_length; i++){
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@ -101,21 +99,21 @@ void TaigaTracer<TB>::reset() {
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}
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template <class TB>
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void TaigaTracer<TB>::set_log_file(std::ofstream* logFile) {
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void TaigaTracer::set_log_file(std::ofstream* logFile) {
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this->logFile = logFile;
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}
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template <class TB>
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void TaigaTracer<TB>::update_UART() {
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void TaigaTracer::update_UART() {
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if (tb->write_uart) {
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std::cout << tb->uart_byte << std::flush;
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*logFile << tb->uart_byte;
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}
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}
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template <class TB>
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void TaigaTracer<TB>::update_memory() {
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void TaigaTracer::update_memory() {
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tb->instruction_bram_data_out = instruction_r;
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if (tb->instruction_bram_en)
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instruction_r = mem->read(tb->instruction_bram_addr);
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@ -127,8 +125,8 @@ void TaigaTracer<TB>::update_memory() {
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}
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}
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template <class TB>
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void TaigaTracer<TB>::tick() {
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void TaigaTracer::tick() {
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cycle_count++;
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tb->clk = 1;
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@ -165,8 +163,8 @@ void TaigaTracer<TB>::tick() {
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update_memory();
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}
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template <class TB>
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void TaigaTracer<TB>::start_tracer(const char *trace_file) {
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void TaigaTracer::start_tracer(const char *trace_file) {
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#ifdef TRACE_ON
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verilatorWaveformTracer = new VerilatedVcdC;
|
||||
tb->trace(verilatorWaveformTracer, 99);
|
||||
|
|
@ -175,24 +173,24 @@ void TaigaTracer<TB>::start_tracer(const char *trace_file) {
|
|||
}
|
||||
|
||||
|
||||
template <class TB>
|
||||
uint64_t TaigaTracer<TB>::get_cycle_count() {
|
||||
|
||||
uint64_t TaigaTracer::get_cycle_count() {
|
||||
return cycle_count;
|
||||
}
|
||||
|
||||
template <class TB>
|
||||
TaigaTracer<TB>::TaigaTracer(std::ifstream& programFile) {
|
||||
|
||||
TaigaTracer::TaigaTracer(std::ifstream& programFile) {
|
||||
#ifdef TRACE_ON
|
||||
Verilated::traceEverOn(true);
|
||||
#endif
|
||||
|
||||
|
||||
tb = new TB;
|
||||
tb = new Vtaiga_sim;
|
||||
|
||||
#ifdef DDR_LOAD_FILE
|
||||
axi_ddr = new axi_ddr_sim<Vtaiga_sim>(DDR_INIT_FILE,DDR_FILE_STARTING_LOCATION,DDR_FILE_NUM_BYTES);
|
||||
axi_ddr = new axi_ddr_sim(DDR_INIT_FILE,DDR_FILE_STARTING_LOCATION,DDR_FILE_NUM_BYTES);
|
||||
#else
|
||||
axi_ddr = new axi_ddr_sim<Vtaiga_sim>(programFile, tb);
|
||||
axi_ddr = new axi_ddr_sim(programFile, tb);
|
||||
|
||||
#endif
|
||||
programFile.clear();
|
||||
|
|
@ -203,8 +201,8 @@ TaigaTracer<TB>::TaigaTracer(std::ifstream& programFile) {
|
|||
data_out_r = 0;
|
||||
}
|
||||
|
||||
template <class TB>
|
||||
TaigaTracer<TB>::~TaigaTracer() {
|
||||
|
||||
TaigaTracer::~TaigaTracer() {
|
||||
#ifdef TRACE_ON
|
||||
verilatorWaveformTracer->flush();
|
||||
verilatorWaveformTracer->close();
|
||||
|
|
|
|||
|
|
@ -25,6 +25,9 @@
|
|||
#include <stdlib.h>
|
||||
#include <iostream>
|
||||
#include <iterator>
|
||||
#include "verilated.h"
|
||||
#include "verilated_vcd_c.h"
|
||||
#include "Vtaiga_sim.h"
|
||||
#include "SimMem.h"
|
||||
#include "AXI_DDR_simulation/axi_ddr_sim.h"
|
||||
//#define TRACE_ON
|
||||
|
|
@ -73,7 +76,6 @@ static const char * const eventNames[] = {
|
|||
static const int numEvents = arraySize(eventNames);
|
||||
|
||||
//Testbench with Taiga trace outputs on toplevel
|
||||
template <class TB>
|
||||
class TaigaTracer {
|
||||
public:
|
||||
TaigaTracer(std::ifstream& programFile);
|
||||
|
|
@ -91,9 +93,9 @@ public:
|
|||
uint64_t get_cycle_count();
|
||||
|
||||
//DDR Simulation
|
||||
TB *tb;
|
||||
Vtaiga_sim *tb;
|
||||
private:
|
||||
axi_ddr_sim<TB> * axi_ddr;
|
||||
axi_ddr_sim * axi_ddr;
|
||||
SimMem *mem;
|
||||
#ifdef TRACE_ON
|
||||
VerilatedVcdC *verilatorWaveformTracer;
|
||||
|
|
@ -114,7 +116,4 @@ private:
|
|||
uint32_t data_out_r;
|
||||
|
||||
};
|
||||
#include "TaigaTracer.cc"
|
||||
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,13 +1,12 @@
|
|||
|
||||
#include <stdlib.h>
|
||||
#include <iostream>
|
||||
#include <fstream>
|
||||
#include "Vtaiga_sim.h"
|
||||
#include "verilated.h"
|
||||
#include "verilated_vcd_c.h"
|
||||
#include "Vtaiga_sim.h"
|
||||
#include "TaigaTracer.h"
|
||||
|
||||
TaigaTracer<Vtaiga_sim> *taigaTracer;
|
||||
TaigaTracer *taigaTracer;
|
||||
|
||||
//For time index on assertions
|
||||
double sc_time_stamp () {
|
||||
|
|
@ -62,7 +61,7 @@ int main(int argc, char **argv) {
|
|||
}
|
||||
|
||||
// Create an instance of our module under test
|
||||
taigaTracer = new TaigaTracer<Vtaiga_sim>(programFile);
|
||||
taigaTracer = new TaigaTracer(programFile);
|
||||
taigaTracer->set_log_file(&logFile);
|
||||
#ifdef TRACE_ON
|
||||
taigaTracer->start_tracer(argv[4]);
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ DELAY_SEED = 867583
|
|||
ddr_size_def = DDR_SIZE=\(long\)$(DDR_SIZE_GB)*\(long\)1073741824
|
||||
page_size_def = PAGE_SIZE=\($(PAGE_SIZE_KB)*1024\)
|
||||
max_inflight_read_requests = MAX_INFLIGHT_RD_REQ=$(MAX_READ_REQ)
|
||||
max_inflight_write_requests = MAX_INFLIGHT_WD_REQ=$(MAX_WRITE_REQ)
|
||||
max_inflight_write_requests = MAX_INFLIGHT_WR_REQ=$(MAX_WRITE_REQ)
|
||||
mix_delay_read = MIN_DELAY_RD=$(MIN_RD_DELAY)
|
||||
max_delay_read = MAX_DELAY_RD=$(MAX_RD_DELAY)
|
||||
min_delay_write = MIN_DELAY_WR=$(MIN_WR_DELAY)
|
||||
|
|
@ -46,7 +46,7 @@ delay_seed = DELAY_SEED=$(DELAY_SEED)
|
|||
#ddr_start_loc = DDR_FILE_STARTING_LOCATION=$(DDR_FILE_STARTING_LOCATION)
|
||||
#ddr_num_bytes = DDR_FILE_NUM_BYTES=$(DDR_FILE_NUM_BYTES)
|
||||
|
||||
CFLAGS = -g0 -O3 -std=c++11 -march=native -D$(ddr_size_def) -D$(page_size_def) -D$(max_inflight_read_requests) -D$(max_inflight_write_requests)\
|
||||
CFLAGS = -g0 -O3 -std=c++14 -march=native -D$(ddr_size_def) -D$(page_size_def) -D$(max_inflight_read_requests) -D$(max_inflight_write_requests)\
|
||||
-D$(mix_delay_read) -D$(max_delay_read) -D$(min_delay_write) -D$(max_delay_write) -D$(delay_seed)
|
||||
|
||||
#(to-do)-D$(ddr_init_file) -D$(ddr_start_loc) -D$(ddr_num_bytes)
|
||||
|
|
@ -90,7 +90,7 @@ $(TAIGA_SIM): $(TAIGA_HW_SRCS) $(TAIGA_SIM_SRCS)
|
|||
verilator --cc --exe --Mdir $(TAIGA_SIM_DIR) -DENABLE_SIMULATION_ASSERTIONS --assert \
|
||||
-o taiga-sim \
|
||||
$(VERILATOR_LINT_IGNORE) $(VERILATOR_CFLAGS) \
|
||||
$(TAIGA_INCLUDED_SIM_SRCS) \
|
||||
$(TAIGA_SIM_SRCS) \
|
||||
$(TAIGA_HW_SRCS) $(VERILATOR_DIR)/taiga_sim.sv --top-module taiga_sim
|
||||
$(MAKE) -C $(TAIGA_SIM_DIR) -f Vtaiga_sim.mk
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue