misc fixes

core/decode.sv

@@ -1,5 +1,5 @@
 /*
- * Copyright © 2017, 2018, 2019 Eric Matthews,  Lesley Shannon
+ * Copyright © 2017-2019 Eric Matthews,  Lesley Shannon
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -283,7 +283,7 @@ module decode(
     end
 
     always_ff @ (posedge clk) begin
-       if (instruction_issued)
+       if (instruction_issued_with_rd & ~rd_zero)
            register_in_use_by_load_op[future_rd_addr] <= new_request[LS_UNIT_WB_ID] & basic_load;
     end
 

core/div_algorithms/div_radix2.sv

@@ -59,7 +59,7 @@ module div_radix2
 
     always_ff @ (posedge clk) begin
         if (start) begin
-            PR <= {{(C_WIDTH-2){1'b0}}, A[C_WIDTH-1]};
+            PR <= {{(C_WIDTH){1'b0}}, A[C_WIDTH-1]};
             Q <= {A[C_WIDTH-2:0], 1'b0};
             B_r <= B;
         end
@@ -100,4 +100,4 @@ module div_radix2
         end
     end
 
-endmodule
+endmodule

core/load_store_unit.sv

@@ -74,6 +74,7 @@ module load_store_unit (
     logic units_ready;
     logic issue_request;
     logic load_complete;
+    logic store_complete;
 
     logic [31:0] virtual_address;
     logic [3:0] be;
@@ -137,6 +138,7 @@ module load_store_unit (
     //Primary Control Signals
     assign units_ready = &unit_ready;
     assign load_complete = |unit_data_valid;
+    assign store_complete = stage2_attr.is_store & load_attributes.valid;
 
     //When switching units, ensure no outstanding loads so that there can be no timing collisions with results
     assign unit_stall = (current_unit != last_unit) && ~load_attributes.empty;
@@ -230,7 +232,7 @@ module load_store_unit (
     assign load_attributes.data_in = load_attributes_in;
 
     assign load_attributes.push = issue_request;
-    assign load_attributes.pop = load_complete | (stage2_attr.is_store & load_attributes.valid);
+    assign load_attributes.pop = load_complete | store_complete;
 
     assign stage2_attr  = load_attributes.data_out;
 
@@ -322,7 +324,7 @@ module load_store_unit (
     always_ff @ (posedge clk) begin
         exception_complete <= (input_fifo.valid & ls_exception_valid & stage1.load);
     end
-    assign ls_done = load_complete | exception_complete |  (stage2_attr.is_store & load_attributes.valid);
+    assign ls_done = load_complete | exception_complete | store_complete;
 
     assign wb.done_next_cycle = csr_done | ls_done;
     assign wb.id = csr_done ? csr_id : stage2_attr.instruction_id;

core/taiga_fifo.sv

@@ -83,8 +83,8 @@ module taiga_fifo #(parameter DATA_WIDTH = 32, parameter FIFO_DEPTH = 4, paramet
                     write_index <= '0;
                 end
                 else begin
-                    read_index <= read_index + fifo.pop;
-                    write_index <= write_index + fifo.push;
+                    read_index <= read_index + LOG2_FIFO_DEPTH'(fifo.pop);
+                    write_index <= write_index + LOG2_FIFO_DEPTH'(fifo.push);
                 end
             end
             assign fifo.data_out = lut_ram[read_index];

core/write_back.sv

@@ -156,7 +156,7 @@ module write_back(
     //Register file interaction
     assign rf_wb.rd_addr = retired_instruction_packet.rd_addr;
     assign rf_wb.id = retired_id_r;
-    assign rf_wb.commit = retired_r & ~retired_instruction_packet.is_store;
+    assign rf_wb.commit = instruction_complete;
     assign rf_wb.rd_nzero = retired_instruction_packet.rd_addr_nzero;
     assign rf_wb.rd_data = rds_by_id[retired_id_r];