removed old lut_ram

core/lut_ram.sv

@@ -1,54 +0,0 @@
-/*
- * Copyright © 2017 Eric Matthews,  Lesley Shannon
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * Initial code developed under the supervision of Dr. Lesley Shannon,
- * Reconfigurable Computing Lab, Simon Fraser University.
- *
- * Author(s):
- *             Eric Matthews <ematthew@sfu.ca>
- */
-
-module lut_ram #(
-        parameter WIDTH = 32,
-        parameter DEPTH = 32,
-        parameter READ_PORTS = 2
-        )
-        (
-        input logic clk,
-
-        input logic[$clog2(DEPTH)-1:0] waddr,
-        input logic[$clog2(DEPTH)-1:0] raddr [READ_PORTS],
-
-        input logic ram_write,
-        input logic[WIDTH-1:0] new_ram_data,
-        output logic[WIDTH-1:0] ram_data_out [READ_PORTS]
-
-        );
-
-    (* ramstyle = "MLAB, no_rw_check" *) logic [WIDTH-1:0] ram [DEPTH-1:0];
-
-    initial ram = '{default: 0};
-    always_ff @ (posedge clk) begin
-        if (ram_write)
-            ram[waddr] <= new_ram_data;
-    end
-
-    always_comb begin
-        for (int i = 0; i < READ_PORTS; i++) begin
-            ram_data_out[i] = ram[raddr[i]];
-        end
-    end
-
-endmodule

core/lutrams/lutram_1w_mr.sv

@@ -60,7 +60,7 @@ generate if (FPGA_VENDOR == XILINX) begin : xilinx_gen
 end
 else if (FPGA_VENDOR == INTEL) begin : intel_gen
 
-    for (genvar i = 0; i < NUM_READ_PORTS; i++) begin
+    for (genvar i = 0; i < NUM_READ_PORTS; i++) begin : lutrams
         lutram_1w_1r #(.WIDTH(WIDTH), .DEPTH(DEPTH))
         write_port (
             .clk(clk),

core/tlb_lut_ram.sv

@@ -60,7 +60,7 @@ module tlb_lut_ram
     logic hit;
     logic [WAYS-1:0] replacement_way;
 
-    logic [$bits(tlb_entry_t)-1:0] ram_data [WAYS-1:0][1];
+    logic [$bits(tlb_entry_t)-1:0] ram_data [WAYS-1:0];
     tlb_entry_t ram_entry [WAYS-1:0];
     tlb_entry_t new_entry;
 
@@ -91,16 +91,16 @@ module tlb_lut_ram
     genvar i;
     generate
         for (i=0; i<WAYS; i=i+1) begin : lut_rams
-            lut_ram #(.WIDTH($bits(tlb_entry_t)), .DEPTH(DEPTH), .READ_PORTS(1))
-            ram_block (
+            lutram_1w_1r #(.WIDTH($bits(tlb_entry_t)), .DEPTH(DEPTH))
+            write_port (
                 .clk(clk),
                 .waddr(tlb_addr),
+                .raddr(tlb_addr),
                 .ram_write(tlb_write[i]),
                 .new_ram_data(new_entry),
-                .raddr('{tlb_addr}),
                 .ram_data_out(ram_data[i])
             );
-            assign ram_entry[i] = ram_data[i][0];
+            assign ram_entry[i] = ram_data[i];
         end
     endgenerate
 

test_benches/verilator/taiga_sim.sv

@@ -448,7 +448,11 @@ module taiga_sim
     genvar i, j;
     generate  for (i = 0; i < 32; i++) begin
         for (j = 0; j < EXAMPLE_CONFIG.NUM_WB_GROUPS; j++) begin
-            assign translation[i] = cpu.renamer_block.spec_table_ram.xilinx_gen.ram[i];
+            if (FPGA_VENDOR == XILINX)
+                assign translation[i] = cpu.renamer_block.spec_table_ram.xilinx_gen.ram[i];
+            else if (FPGA_VENDOR == INTEL)
+                assign translation[i] = cpu.renamer_block.spec_table_ram.intel_gen.lutrams[0].write_port.ram[i];
+
             assign sim_registers_unamed_groups[j][i] = 
             cpu.register_file_block.register_file_gen[j].reg_group.register_file_bank[translation[i].phys_addr];
         end

tools/taiga_compile_order

@@ -74,7 +74,6 @@ core/clz.sv
 core/div_core.sv
 core/div_unit.sv  
 
-core/lut_ram.sv  
 core/tlb_lut_ram.sv  
 core/mmu.sv